RU1789991C - Device for digital processing of the signals - Google Patents

Abstract

The invention relates to computer technology and is intended to solve the problems of digital signal processing, including the implementation of the fast Fourier transform (FFT) algorithm. The aim of the invention is to increase the speed of the digital signal processing processor by parallelizing the algorithm for performing the basic operation by computing units, which allows both the real and imaginary parts of the output sample to be formed and the duration of the basic operation to be significantly reduced. At the same time, the processing time of the group of input samples is comparable with the time of their formation, which allows the proposed processor to digitally process .ttj at t

Description

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Signal bots work in real time. The digital signal processing processor contains an analog-to-digital converter 1, synchronization block 2, register block 3, computing blocks 4.1 ... 4.8, input 5 of the processed analog signal, input 6 of the Start signal, input 7 of the Stop signal, the first 8 and second 9 group outputs block 3 registers, the first 10.1, 10.8, the second 11U1 ... 11.8 and the third 12.1 ... 12.8 outputs of the computing modules 4.1, .. 4.8, group output 13 of the synchronization block 2 and the corresponding communications. Block 3 of the registers contains the first 18.1 and second 18.2 group of registers, each of the groups of registers consists of N 8 registers 18.1.N and 18.2.N, respectively, the first 19 and second 20 elements And and their relationships. The synchronization module contains an RS-flip-flop 21, a clock generator 22, a counter 23, a first 24, a second 25, a third 26, a fourth 27, a fifth 28 and a sixth 29 elements I, trigger 30 and their communications. Each control module (for example, the first 15.1 is disclosed) contains a counter 37, a counter 38, a first 39, a second 40 triggers, an EXCLUSIVE OR 41 element, an OR element 42, a first 43, a second 44, a third 45, a fourth 46, a fifth 47, a sixth 48, seventh 49, eighth 50, ninth 51, tenth 52 and eleventh 53 element AND, first 54 and second 55 triggers and their connections, a group of 56 ... 65 inputs of the group output of the control module. All computing units 4 are identical. The invention relates to computer technology and is intended to solve the problems of digital signal processing, including the implementation of the Fast Fourier Transform (FFT) algorithm.

Known processor for digital signal processing, containing N processor modules and a control unit connected to control inputs

processor modules.

. ; .

The disadvantages of the processor is poor performance.

A known processor for digital signal processing, comprising an input unit, N buses, N processor modules, first inputs connected to the output of the input unit, a control device, an output connected to the control inputs of the processor modules.

The disadvantage of the processor is the low performance due to the long duration of the exchange interval

us. For example, consider 4.1, it contains the first 68, second 69, third 70 and fourth 71 registers, the first 72 and second 73 computational modules, the first 74 and second 75 registers of the result and their relationships. The first computing module comprises a coefficient generating unit 76, a first 87 switch, a third 88 switching unit, a first 89 and a second 90 multiplying units, a register 93, a register 94, a register 95, a register 96, a coefficient generating unit comprises a counter 95, a memory unit 96, a register 97, first 98, second 99, 2-AND-OR element, the first switch contains the first 10 and second 101 2-OR-elements, the third switch contains the first 102, second 103 and the third 104 2-OR elements. The second computing module comprises a second 106 switch (first 110, second 111, third 112 and fourth 113 2-OR elements), first 106 and second 107 adders-subtractors, fifth 108, sixth 109 intermediate result registers and corresponding communications. New in the digital signal processing processor is the introduction of second multipliers and adder-subtracters, a register block, second, third and fourth registers of intermediate results, output sample registers, a third switch, a unit for generating conversion coefficients and the associated relationships in the computing units. 1 s.p. f-ly, 14 ill.

data between processor modules.

The closest to the invention in technical essence is a processor

for digital signal processing, containing N computing units (where IM is the dimension of the transformation) and a synchronization unit, N groups of outputs of which are connected to groups of control inputs

corresponding N computing units, the first information output of the Kth (K 1, N / 2) computing unit is connected to the first information inputs of the 2nd and (2K-1) computing units / first

the information output of the Mth (M N / 2 + 1, N) computing unit is connected to the second information inputs of the (2M-N / 2) -ro and (2M-N / 2 + 1) -th computing units, each computing unit contains four input registers, two switches, the first multiplier, the first adder-subtractor and two buffer registers, the information inputs of the first and second input registers being the first and second information inputs of the computing unit, the first outputs of the second and third input registers are connected respectively to the firstand second information inputs of the first switch, the first output of which is connected to the information input of the first buffer register, the first outputs of the first and fourth input registers are connected respectively to the first and second information inputs of the second switch, the first output of which is connected to the first information input of the first adder-subtractor, output which is connected to the information input of the second buffer register, the output of which is connected to the third information input of the second switch, the inputs are synchronization from the first to fourth input registers, the first and second buffer registers, interconnected the control input of the first switch and the first control input of the second switch, the second control input of the second switch and the control input of the first adder-subtractor are respectively the ninth control inputs of the computing unit group.

The processing time of the group of input samples by this processor is much longer than the time of formation of this group, as a result of which the input samples must be accumulated in the register nodes. Thus, a significant drawback of this processor is its low performance and the inability to use it for real-time digital signal processing.

The purpose of the invention is to increase productivity.

The essence of the invention is to increase the speed of the digital signal processing processor by parallelizing the algorithm for performing the basic operation by computing units, which allows both real and imaginary parts of the output sample to be formed, and significantly shortening the duration of the basic operation. Moreover, the processing time of the group of input samples is comparable with the time of their formation, which allows the proposed digital signal processor to operate in real time.

The introduction of the second multipliers and adders-subtracters in the computing units allowed us to simultaneously form the real and imaginary parts of the input samples.

The introduction of a block of registers allows the formation of a stream of input samples in the form of groups of 2N samples in each.

The introduction of the second, third, and fourth 5th registers of intermediate results allows us to record the results of intermediate calculations of output samples.

The introduction of output sample registers allowed us to take into account the time difference in the formation of the Fourier coefficients by the computing units.

The introduction of the third switch made it possible to organize the distribution of the results of intermediate distributions

5 between adders-subtractors in such a way as to ensure the execution of a parallel algorithm of implementations of the basic operation.

The introduction of a transformation coefficient forming unit provides the formation of transformation weight coefficients in accordance with the algorithm for implementing basic operations.

Thus, the claimed object complies with the criterion of significant differences, since in the known technical solutions there was no increase in speed due to the parallelization of the algorithm for implementing the basic operation

0 computing units. This is achieved by introducing the above set of features that are not found in the known analogues and prototype. When using the proposed technical solution, a positive effect can be obtained consisting in an almost twofold increase in speed.

Figure 1 shows the structure of a digital signal processor; on the

0 figure 2 - structure of the synchronization unit; Fig. 3 is a functional block diagram of the registers; Fig. 4 is a functional diagram of a synchronization module of a synchronization unit; Fig. 5 is a functional diagram of a control module; on figb - structure of the computing unit module; Fig.7 is a functional diagram of the first; on Fig - the second computing modules, respectively; Figures 9-13 are timing diagrams of processor operation; in FIG. 14 is a graph diagram of an FFT algorithm implemented by a processor.

The processor (figure 1) contains an analog-to-digital converter 1, block 2 of sync 5 clock, block 3 registers, N 8 computing blocks 4.1 ... 4.8, input 5 of the processed analog signal, input 6 of the start signal, input 7 of the Stop signal, the first 8 and the second 9 group outputs of the block 3 registers, the first 10.1, 10.8, the second

11.1 ... 11.8 and third 12.1 ... 12.8 outputs of computing modules 4.1 ... 4.8, group output 13 of control unit 2.

Block 3 registers (Fig. 3) contains the first 18.1 and second 18.2 groups of registers, each of the groups of registers consists of N 8 registers 18.1 N and 18.2 N, respectively, the first 19 and second 20 elements I.

The synchronization module (Fig. 4) contains an RS-flip-flop 21, a clock generator 22, a counter 23, a first 24, a second 25, a third 26, a fourth 27, a fifth 28 and a sixth 29 elements AND, a trigger 30.

Each control module (the first 15.1 of them is disclosed for example) (Fig. 5) contains a counter 37, a counter 38, a first 39, a second 40 triggers, an EXCLUSIVE OR element 41, an OR element 42, a first 43, a second 44, a third 45 , fourth 46, fifth 47, sixth 48, seventh 49, eighth 50, ninth 51, tenth 52 and eleventh 53 element AND, first 54, second 55 triggers, group 56 ... 65 inputs of the group output of the control module .- .

All computing units are identical. Each of them contains the first 4.1 (Fig.6), it contains the first 68, second 69, third 70 and fourth 71 registers, the first 72 and second 73 computational modules, the first 74 and second 75 registers of the result first 76 and second 77 outputs of the first 68 register, the first 80 and second 81 outputs of the second 69 registers, the first 78 and second 79 outputs of the third 70 registers, the first 82 and second 83 outputs of the fourth 71 registers, the first 84 and second 85 outputs of the first 72 computing module ....

The first computing module (Fig. 7) comprises a coefficient generating unit 86, a first 87 switch, a third 88 switching unit, a first 89 and a second 90 multiplication unit, a first 91, a second 92, a third 93 and a fourth 94 register, the coefficient generating unit comprises a counter 95. a memory unit 96, a register 97, a first 98 and a second 99 2-OR elements, the first switch contains a first 100 and a second 101 2-OR elements, a first 102, a second 103 and a trey 104 2-OR elements.

The second computing module (FIG. 8) contains a second 105 switch, a first 106 and a second 107 adder-subtracters, the fifth 108 and sixth 109 registers of intermediate results, the second switch contains the first 110, second 111, third 112 and fourth 113 elements 2I -OR.

In Figs. 9-13, the designations introduced in Figs. 1-8 are used.

In FIG. 14 symbols X1, X2, ..., X1 b denote elements of the input sequence, symbols Y1, Y2, ..., Y16 - elements of the output sequence of Fourier coefficients.

Consider the purpose of the main processor nodes. An analog-to-digital converter (ADC) 1 is designed to receive an analog signal with an amplitude lying within a given range and to form an equivalent digital

0 signal; those. n-bit parallel binary signal, i.e. an n-bit parallel binary word representing this signal. Taken at fixed discrete time instants, they represent a sequence of input samples of the processor. ADC control and timing circuits are not shown.

. The control device 2 is intended for forming a sequence

0 signals for control and synchronization of the operation of block 3 registers and groups 4.1 ... 4.8 computing blocks.

Consider the order of operation of the synchronization unit.

5 In the initial position, all triggers and counters are in the zero state.

By the start signal received at input 6, the trigger 21 switches to the single state (the timing diagram of the functioning of the synchronization unit 14 is shown in Fig. 11).

From a single signal from its direct output, the clock generator 22 of the mm pulse begins to generate a sequence

5 clock pulses.v

Changes in the states of the clock counters and the processor registers occur along the trailing edge of the corresponding clock pulse.

0 Counter 23 at the output of the first bit divides the input sequence of clock pulses into two, at the output of the second - at four, at the output of the third - at eight, at the output of the fourth - at sixteen, at output 5, at thirty-two.

Element And 25 serves to isolate clock pulses whose sequence number is A p 8, where p 1,2,3, ... Thus, the eighth pulse from the sync sequence through element And 26 will go to input 35, and the sixteenth through element And 27 - to the input 34, the twenty-fourth pulse will go back to the input 35 of the first bus, etc. Element And 24 serves to isolate the clock with a serial number of twenty. According to this pulse, trigger 30 is brought into a single state and allows the synchronization sequence to pass from the output of the generator 22, starting from the 21st pulse through the And 28 element to the input

33 of the first output bus. Element And 29 serves to highlight a sequence of clock pulses with serial numbers G 7 + n 16, n 0,1, ..., which is fed to the input 36 of the first bus. According to the Stop signal 5 received at the input of the processor 7, the triggers 21 and 30 are brought to the zero state. Clock generator 22 stops working, counter 23 is reset. The synchronization unit transitions to the initial 10 state. By the trigger signal at the input of the processor 6, the operation of the block will resume, as described above.

. Each 15.1 from the group 15.1 ... 15.8 of the control modules is designed to form a sequence of signals that control the operation of the corresponding 4.1, I 1.8 computing unit. Let us consider the order of operation of the module as an example of the first 15.1. In the initial state, the counters are 20 "and 37 and 38, the triggers 39 and 40 are reset. The first pulse coming from the output bus 33 output through the AND element 44 to the first clock input of the counter 37 transfers it to the next state, in which a single 25 signal appears at its first output, at the second pulse at the second, at the third - on the first and second, fourth pulse, counter 37 is reset to zero. According to the next pulse passing to the sync input of counter 37, the order of its operation is repeated as described above. An exception is the situation when at the moment when counter 37 is reset, a single signal appears at input 17.5, then the next 35 pulse is extinguished and the counter remains in the zero state until the signal value at output 17.5 changes. The zero state of counter 37 is the identifier for the start of the next iteration. The damping of the pulse leads to the possibility of controlling the start time of the iteration.

. When a single signal is present at the output of the first bit of counter 37, and a zero signal at the second, an impulse will arrive through the And 52 element to the 45 and C-inputs of trigger 40, which will translate it into a single state, - (a. A single signal from the direct The output of the flip-flop 40 will allow the clock to go through when the counter 37 bu: 50 is in the described state at the input 61 of the bus 13.1.

When a single signal from the output of the element And 45 arriving at the D-input of the trigger 39, according to the clock pulse from the output 33 55 of the input bus, the trigger 39 will switch to the single state, by the same pulse, the counter 37 will go to the next state at the D-input of the trigger 39 the zero signal is detected, thus, at the next pulse from the output bus 33 of the input bus, the trigger 39 will return to its original state. Let A denote the sequence of signals from the first output, through B the sequence from the second direct output of the counter 37 - and B is the inverse one, we will denote the sequence of pulses from output 33 of the input bus as C. Then element AND 46 implements the function Fi ABC. The counter 38, according to the first pulse of the FI sequence, will enter the state when a single signal is detected at its first output, at the second at the second, at the third at the first and second, at the fourth it will return to its initial state, etc.

In this case, a single signal at the output of the And 49 element will be present only at the moment when a single signal is present at the first output of counter 38, and a zero signal at the second.

Element AND 47 implements the function Fa AC. Element And 51 implements the function Fa AB.

The EXCLUSIVE OR element 41 implements the function F4 A fV, where the symbol f denotes the summation operation. Modulo two.

By a single signal from the output bus 7 of the input bus, counter 37, counter 38, flip-flop 39, flip-flop 40 will return to the initial state.

Consider the order of operation of the synchronization unit as a whole. Each 15.1 of the control modules for the signals arriving at their first inputs from the first output of the synchronization unit 14 forms on its first group output 13.1 a sequence of control signals for the corresponding 4.1.1 1.8 computing unit. The beginning of the basic operation in this 4.I computing unit is determined based on the presence of conditions for its implementation. These conditions are considered:

a) the presence at the moment of the initial reference AI, where I is the iteration number.

b) at least four measures have passed since the beginning of the (S) th iteration. The presence of the At1 count is determined by 1 single signal at the second output 17.J of the corresponding 15.J control module, (j is determined from the BFT algorithm implemented by the processor). The second condition is realized by the transition of the counter 37 to its initial state).

If the first condition is realized at the fifth beat of the (1-1) th iteration, then due to the blanking of the clock pulse by the counter, counter 37, as described above, is delayed by one clock cycle of the beginning of the 1st iteration. Thus the device

The control allows, depending on the operating conditions of the corresponding computing units, to determine for them the start of the next iteration, which provides the flexibility of controlling the processor ..

The register block (FIG. 3) serves to form two packets of input samples: X1 ... X8 ... and X9 ... X1 b, which are perceived by the processor as B1 ... B8 and A1 ... A8 ..

The information input of the block of registers from the ADC input samples X1 ... X16. According to the zero value of the signal at the output 32 of the input control bus through the And 19 element, the first eight clock pulses will go to the sync inputs of the first group of registers 18.1.1 ... 18.1.8. Input samples, sequentially rewriting from register to register, starting from the first, at the end of the eighth measure will be recorded in the following order: X1 - in the register 18.1.8 ... X8-in the register 18.1.1. Then, at output 32, a single signal appears and the second eight samples X9 ... X16 similarly turn out to be recorded in the second group of registers 18.2.1 ... 18.2.8. After that, the signal at the output 32 again changes sign and the process of forming packets of input samples is repeated.

the computational unit 4.1 is used to perform the ith basic operation on input samples A and B. Consider the operation of the computing unit when performing the basic operation.

The basic operation of the FFT algorithm is to calculate by the formulas:

CR BR + ARWR-AiWi;

DR BR-ARWR + AiWi;

Ci Bi + ARWR + AiWi:

Di Bi-ARW | -AiWR where.

A Ri (AR) + j1m (Ai),

B Ri (BR) + jlm (Bi)

- the initial data for the basic operation entering the computing unit 4.1 from the corresponding first 8.1 and second 9.1.1 1.8 register blocks;

C Ri (CR) + (Ci);

D Rt (DR) + jlm (Di)

- the results of the basic operation, issued by the computing unit as it is ready for the output of the legal entities, and taken as the initial data A and B for the basic operations by the corresponding blocks 4.J according to the FFT algorithm graph (Fig. 14) and the given processor bus arrangement.

In this way:

Bi Ci iBe Da1; B2 | +1 Di; B7M C /; AG De1: Vs + g C2; B81 + 1 04X 07; Aj + 1-Da B4 | +1 D2; AiM Cs1; A6I + 1 D7I:

B5I + 1 - C3; A2I + 1 D5; A7 +1 Ce;

where I 1,2,3,4 is the iteration number, subscript is the number of the computing unit equal to the number of the basic iteration.

After the last iteration

0 with number four, the outputs of the computing units receive the results - Fourier, and

YI SG, Y2 C54 Y3 Cz4 Y4 -, Y5 C24, Ye Ce4, Y C44, Y8 C84, YQ Di4. .

5 Yio D54, YH D34, Yi2 DT. Yi3 D24. Yi4 D64, De4 Each computing unit performs the basic operation in all iterations the same. The only exception is

0 that in the first iteration, the initial data A and B come from registers 68 and 69, respectively, and in the remaining iterations, respectively, from registers 70 and 71. The basic operation described above is calculated by

5 to the following algorithm. The whole iteration is divided into 4 steps, each of which carries out two operations:

1. BR - ARWR - KR; Bi - A | WR KI;

2. KR + AiWi DR; KI - ARW | - DI;

0 3. BR + ARWR LR; BI + ARWR Li; 5. LR - AiWi CR; LI + AiWi Ci The use of such an algorithm reduced the iteration duration to five clock cycles. In the future we will consider

5, the operation of the computing units on the example of unit 4.1, for this we turn to the time diagrams shown in Figs. 12 and 13.

The blocks of multipliers and adders-subtracters are not disclosed before the functional diagrams, since this is not of fundamental importance. As a multiplier, a ROM or a program - decision logic matrix (PLM) can be used,

5 a as a adder-subtracter is a summer, in which, at one of the information inputs, the number is represented in an additional code by the corresponding control signal.

In the initial state, all counters, triggers and registers of the computing unit are reset. According to the first clock pulse received from the output of the 35 bus 13.1 in the register

5 69 from input 8.1, the actual BIR and imaginary B and parts of the input sample X1 will be entered.

The second clock pulse received from the output 34 of the bus 13.1 in pernci p 68 from the input 8.1 is valid AiR1 and

imaginary An1 of the input sample part X9, at the same time according to the first clock pulse with v-. the path 56 of the bus 13.1 to the register 97 on the first and second input from the zero line of the block 96 of the memory will be entered respectively real 5 WR and imaginary Wi part of the first weight. The real ARI and imaginary Ats1 parts of the input sample are received at the first and third 76 and 77 information inputs of the first 87 of the switch 10, respectively. In the first iteration step of the zero signal from the output 62 of the bus 13.1, the real part of the weight coefficient WR will go through the coefficient switch to the first inputs of the first 89 and 15 of the second 90 blocks of multipliers, respectively, on the second inputs of which from the first and second outputs of the first switch, respectively, the valid AIR and imaginary Ats1 parts of the input sample are received. In 20 multiplication units 89 and 90, the real AIR and imaginary AC1 parts of the input sample are multiplied by the real WR part of the weight coefficient. From the zero value of the signal from the output 62 of the bus 13.1, along the 25 trailing edge of the pulse from the output 60 of the bus 13.1, the results of the calculations of AIR WR and An WR are entered into the registers 91 and 92, respectively. In the second cycle, in accordance with the zero signal at the output 62 and a single signal at the output of the 64 bus 13.1, the generated results of calculations from the outputs of the registers 91 and 92 through the third switch 38 are transmitted to the first information inputs of the first 106 and second 107 35 adders-subtracters respectively. On their second information inputs from inputs 80 and 81, single signals from outputs 61 and 64 respectively receive real W1 and imaginary W1 parts of 40 of the second input sample. On a single signal from the outputs 65 and 62 of the bus 13.1 in the first 106 and second 107 adders-subtractors x, the subtraction operation is performed:

45

BR-ARWR KR; B | A | WR-K | In the same clock cycle, on a single signal from the output of bus 62 13.1, an imaginary 50 part of Wi weight coefficient will be supplied to the first inputs of the first 89 and second 90 multipliers through the coefficient switcher and the real AiR1 and imaginary AC parts of the input sample will be multiplied by the imaginary Wi part of the weight coefficient. On the trailing edge of the pulse from output 63 55, according to a single signal from output 62 of bus 13.1, the results of multiplications ApWi and AiWi are recorded in registers 93 and 94, respectively. According to the pulse from output 63 of bus 13.1, counter 95 will go into a state in which a single signal appears at its first exit, i.e. the address of the first ruler is formed in the memory block 96, where the next coefficient is recorded. The intermediate values KR and K | on the trailing edge of the pulse from the output 57 of the bus 13.1 are entered into the registers 108 and 109, respectively. In the third clock cycle, the first inputs of the first 106 and second 107 adders-subtracters by the zero signal at the output 64 and the single output 62 of the bus 13.1 receive the results of AiWi and ApWi, respectively, and to the second inputs KR and Ki, respectively. In this cycle, the first adder-subtractor 06 operates in the adder mode, the second 107 in the subtractor mode. At the end of the clock, the real DR BR - ARWR + AiWi and the imaginary DI Bi - AiWR - ARWI portions of the converted sample arriving at the output 10.1 of the computing unit are formed respectively at the outputs of the first 106 and second 107 adders / subtracters.

In the fourth cycle, the first 106 and second 107 adders-subtracters operate in the adder mode (since there is a zero signal at the outputs 62 and 65 of bus 13.1), they calculate the first intermediate values of the second converted samples:

LR BR + ARWR, LI B | +. which, according to the clock pulse from the output 57 of the bus 13.1 will be entered in the registers 108 and 109, respectively. According to the pulse from the output 56 of bus 13.1, the generated second weight coefficient, its real and imaginary parts, will be entered in register 97. In the fifth step, the first 106 adder-subtractor works in the subtractor mode, and the second 107 in the Adder mode. Their first inputs will receive the result of AiWi. the second - intermediate LK and LI, respectively. At the end of the cycle, at the outputs of the first YuB and second 107 adders-subtracters, respectively, real Ср RR + ARWR - AiWi and imaginary Ci BI - + A | W | parts of the second converted reference. The input samples Ai and B1 are entered into the registers 70 and 71 by the pulses arriving from the outputs 58 and 59 of the bus 13.1, respectively. If the output sample At to the fifth step 1-1 of the iteration has already been generated and written to the register 70, then in this clock, along with the above operations of addition-subtraction, the first clock of the next I iteration begins in the same way as described above. Thus, iteration overlap occurs. Otherwise, the next iteration begins after a clock cycle.

At the end of the fourth iteration of the pulse from output 36, the first 54 and second 55 IK triggers in the corresponding control module will go to the single state, which will allow the recording of converted reports Df and Ci4, which will be Fourier coefficients Y1 and Y9, respectively, with respect to trailing edges of the signals from the outputs 16.1 and 17..1. of the bus, 13.1 in the registers 74 and 75 of the results, respectively. By the same signals, triggers 54 and 55 return to their original state.

Consider the order of operation of the processor as a whole. Figures 9 and 10 show a timing diagram for performing basic operations by computing units. On the general abscissa scale, numbers of computing units are marked N. For each of N computing units, iteration numbers I 1,2,3,4 are canceled along this axis. The y-axis is the time. The start signal is input to input b of control device 2. At the first output of this block, sequences of control signals appear. This input 5 of the analog-to-digital converter 1 receives the initial analog signal, from which it generates an equivalent digital signal in the form of an n-bit parallel binary word, which is the input sample. X |, I 1.16 for the computing part process. The first group X1 ... X16 of the input samples is accumulated in the register block 3 and, according to the signals from the second output 13 of the control device 2, is recorded in the corresponding first and second registers of the computing blocks.

All N 8 computing units begin to perform their basic operations in the first iteration. For the first group of input samples X1 ... X16 at the same time.

The conditions for performing basic operations of the next iteration are not provided for all computational units at the same time. Thus, only the second, fourth, sixth, and eighth computing units can start performing basic operations of the second iteration in the fifth step of the first iteration. The conditions for starting the implementation of the basic operations of the second iteration for the remaining odd computing units will be provided only at the end of the final fifth

measure of the first iteration. Thus, a temporary shift is formed at the beginning of the implementation of the basic operations of the next iteration by various computational

in blocks. The implementation of an iteration start delay in a computing unit has been described above. The basic operations of the third iteration in even-numbered computing units will also begin at the fifth step of the second iteration performed by these units. The start of the third iteration in the third and seventh processing units will also be possible at the fifth step of the second iteration in these units. Performance

the third iteration in the first and fifth computational blocks will begin at the end of the fifth step of the 2nd iteration in these blocks, thereby these blocks will lag behind even ones by two clock cycles, and from the third and seventh - by

one. The beginning of the fourth iteration in the fourth, sixth and eighth computational blocks coincides with the fifth clock cycle of the third iteration in these blocks. The second, third and seventh blocks will begin execution

this iteration through the clock, and the first block will be delayed by another clock. Part of the output samples of the first group of Yie, Yi4, Yts1 is on the 15th clock cycle of processing the first group of input samples. Samples Yi21,

YII, Yi3 - at the sixteenth, samples Ye1, Ye, Yin, Yy1 - at the seventeenth, samples. Ya1, Ys, Yg1 - on the eighteenth, sample Yr - on the nineteenth / Writing output samples in the result registers of the computing units allows you to compensate for the spread in time of their formation. The beginning of the implementation of the first iteration calculations for the second group of input samples in any other computing units coincides with the fifth clock cycle of the final iteration of processing the first group of input samples. Starting from this point in time, the processor retraction mode ends and then all the computing units

operate with a constant shift in the start of calculations in subsequent iterations, thereby the processor goes into stationary mode (Fig. 10). By the Stop signal at the input 7 of the control device, the generation of sequences of control signals stops, the elements of the processor return to their initial state. By the alternate Start signal, the processor will resume operation according to the above-described algorithm.

Claims (2)

The formula of the invention 1. A digital signal processing processor containing N computing units (where N is the dimension of the transformation) and a synchronization unit, N output groups of which are connected to the control input groups of the corresponding N computing units, the first information output of Kgo (K 1, N / 2) of the computing unit is connected to the first information inputs of the 2Kth and (2K-1) -th computing units, the first information output of the Mth (M N / 2 + 1.N) computing unit is connected to the second information inputs (2M -N / 2) -ron (2M -N / 2 + 1) unit, and each computing unit contains four input registers, doses of the switch, the first multiplier, the first adder-subtracter and de-buffer register, and the information inputs of the first and second input registers are - EOTNS, respectively, the first and second information inputs of the computing unit, the first outputs of the second and the third input registers are connected respectively to the first and second information inputs of the first switch, the first output of which is connected to the first input of the left multiplier, One of which is connected to the information input of the first buffer register, the first outputs of the first and fourth input registers are connected respectively to the first and second information inputs of the second switch, the first output of which is connected to the first information input of the first adder-subtractor, the output of which is connected to the information input of the second buffer register, the output of which is connected to ifpSTMw with the information input of the second switch, synchronization gatherings from the first to fourth input registers, the first and second of the first buffer registers, interconnected, the control input of the first switch and the first control input of the second switch, the second control input of the second switch and the control input of the first adder-reader are respectively the first through ninth control inputs of the computing group unit, characterized in that, in order to increase productivity, it further comprises a block of registers, and each computing unit further comprises a unit for generating conversion coefficients, the third to switch, second multiplier, second adder-subtractor, two output registers and third through sixth buffer registers, the information input of the register block being connected to the process information input, the first and second synchronization inputs of the register block are connected respectively to the first and second outputs of the synchronization block, the first and the second outputs of the register block are connected respectively to the third and fourth information inputs of the computing blocks, the second and third information outputs of which form a group and formation outputs of the processor, the third and fourth information inputs of each computing unit are connected to the information inputs of the third and fourth input registers respectively, the outputs of the first and second adders-subtracters form the first information output of the computing unit, the second and third information outputs of which are respectively the outputs of the first and second output registers, the information inputs of which are connected to the outputs of the first and second adders-subtracters, respectively, in the output of the second adder-subtractor is connected to the information input of the third buffer register, the output of which is connected to the fourth information input of the second switch, the fifth and sixth information inputs of which are connected to the second outputs of the first and fourth input registers, the second output of the second switch is connected to the first information input the second adder-subtractor, the second information inputs of the first and second adders-subtractors are connected respectively to the first and second outputs tr of this switch, the second output of the first switch is connected to the first input of the second multiplier, the output of which is connected to the information inputs of the fourth and fifth buffer registers, the outputs of which are connected respectively to the first and second information inputs of the third switch, the third and fourth information inputs of which are connected to outputs respectively per-. of the first and sixth buffer registers, the information input of the sixth buffer register is connected to the output of the first multiplier, the third and fourth information inputs of the first switch are connected to the second outputs of the second and third input registers respectively, the second inputs of the first and second multipliers are connected respectively to the first and second outputs of the forming unit conversion coefficients, the synchronization input of the third buffer register is connected to the sixth control input of the computing unit group, interconnected control input of the transform coefficient generating unit, the first control input of the third switch, the sample inputs of the first, fourth, fifth and sixth buffer registers and the control input of the second adder; the tenth control input of the group of the computing unit, the first synchronization input of the unit for generating conversion coefficients and the synchronization inputs of the fifth and sixth buffer registers are the eleventh control input of the group of the computing unit, the second control input of the third switch is connected to the eighth control input computing block groups, the fourth buffer register synchronization block is connected to the fifth control input of the computing block group, twelfth unit the input input of the group of which is connected to the second synchronization input of the transform coefficient generation unit, the sampling inputs and synchronization inputs of the first and second output registers are the thirteenth to sixteenth control inputs of the computing unit group, the start and stop inputs of the synchronization unit are the processor inputs of the same name . 2. The processor according to claim 1, wherein fieri is such that the transform coefficient generating unit comprises a counter, five coefficients, a register and a switch, the first and second outputs of which are the first and second outputs of the node, respectively the control input of which is connected to the control input of the switch, the first and second information inputs of which are connected respectively to the first and second outputs of the register, the first and second information inputs of which are connected respectively to the first and second outputs of the memory coefficient com, the address input of which is connected to the output of the counter, the count input of which is the first synchronization input of the node, the second synchronization input of which is connected to the register synchronization input.  3} 4J / in W.8 9.8. 8.8. w Fie.Z 9tfr. $: L. 16668U Is  8 Web iet Mr. jfc.-.- ™ 4 7 A- & , „ t a fg ,,, ........ .. fcI s. 4Jif - j, I5.JE | rir- “A ----------, --------- --.--- 1 ----------: ----- Sp ztf It Јfe-- "--- 8g | , Ј-y «--- in --- l & Tg1G: L12g} g-1, . jr. +.,. & Jy i y ..: ... - v tfrir17: fg- v f. , v & -I --- fK. i f v - i ---- Av- &   j fcJbrV -yjL-- U.i44gt /, irtaoyuiiuuuuuuinnnrinruuuuuuinn jiT I'm 9 Jn0l Zf G and: m Sp ztf It , v / f If " iЈ 1 1666811 I am 6 t TdO ss 3 35 1 8 16 24 PPPPPPPPPPPPPPPPPPPPPPPPM 1 I Jl Jl pppppdppp, p Fi g. 11 pppppdppp, p Jl 31 LSH Ш5 ЯШ Ш1 G1 & 95 35 №86 No. Number 107 HZ T 7J vu. mi and 35 56 51 And 61 59 36 60 58 61 W 63 t 55 75.7 FIG. AND