RU1781692C - Device for studying of fundamentals of computer engineering - Google Patents

Abstract

The invention relates to educational and laboratory equipment and can be used in the educational process, as well as in the modeling and debugging of discrete devices built on integrated circuits. The device allows expanding didactic opportunities by introducing a new discipline of automatic identification of racing situations. The device comprises an operator panel, a unit for presenting information (external input signals), a switch, a typesetting field, logic elements, memory units and racing control units of the logic converter. 8 ill.

Description

The invention relates to educational and laboratory equipment and can be used in the educational process, as well as in the modeling and debugging of discrete devices built on integrated circuits.

A device for teaching the basics of computer technology is known, comprising an operator- remote control consisting of a single pulse generator, a continuous pulse train generator, a type of work switch, a zero generator, a control keyboard and a trigger block, an indication unit, a switch, a dial-up field, logical modules elements consisting of two switches, logic elements and an indication unit, trigger modules consisting of two switches, a memory element, indicators and a prediction unit, consisting on of the inverter, and the two elements and the OR.

The disadvantage of this device is the low didactic capabilities for

due to the lack of identification of racing situations in the logic converter when modeling discrete devices. Also known is a device for teaching the basics of computer technology, containing an operator console, a unit for presenting information (external input signals), a switch, a dial-up field, logic elements and memory units. The operator panel comprises a single pulse generator, a pulse train generator, a zero generator, a switch, an AND element, a control keyboard; a register, a memory element racing control unit comprising a switch, a group of modulo-2 addition elements, first and second indicators, a read-only memory, a switch, a trigger, a continuous pulse generator, an AND element, and an audible alarm unit. The logic element contains two commutators. logical node indicator. The memory block contains two switches, a memory element, two indicators and a forecast node.

VI OE

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vani containing an inverter, two AND elements, an OR element.

A disadvantage of such a device is its low didactic capabilities due to the lack of identification of racing situations of the logic converter when modeling discrete devices.

Closest to the invention is a device for teaching the basics of computing, comprising an operator panel, a unit for presenting information (external input signals), a switch, a dial-up field, logic elements, memory units, and racing control units of the logic converter. The operator panel contains continuous pulse train generators, a zero generator, a switch, first and second AND elements, an audible alarm unit, a switch, an OR element, a trigger, a control keyboard, a register and a memory element racing control unit containing a switch, a group of elements modulo 2 additions, indicator, read-only memory node, switch, trigger and indicator. The logical element contains the first and second switches, a logical node and an indicator. The memory unit contains the first and second switches, the memory element, the first and second indicators and the prediction unit containing the inverter, the first and second AND elements, and the OR element. The racing control unit of the logic converter contains the first and second switches, the first, second and third triggers, a switch, an AND element, an NAND element and an indicator, the first output of the operator panel being connected to the corresponding inputs of the presentation unit and the input floor, the second the output is with the corresponding input of the type-setting field, and the outputs of the group are with the corresponding inputs of the group of the block of presentation of information and with the corresponding inputs of the first group of the type-setting field, the inputs of the group of the operator panel are corresponding the input inputs of the first group of the device, the inputs of the second and third groups and the outputs of the first and second groups of the dialed field are the corresponding inputs and outputs of the device, the inputs of the first switch are the corresponding inputs of the first group of the device, the inputs of the group of the OR element are connected to the corresponding outputs of the first switch, and the output is with the third output of the operator console, the single input of the trigger is connected to the output of the IL AND element, the zero input is connected to the 7th output of the output of the operator console, and the zero and single outputs are connected to the first the second input of the operator console,

accordingly, the inputs of the second switch are the corresponding inputs of the fifth group of the device, the outputs of the third switch are the corresponding

the outputs of the third group of devices, the first inputs of the elements AND are connected to the outputs of the corresponding switches, the unit inputs of the first group of triggers are connected to the corresponding outputs

0 of the second switch, and the zero inputs are to the outputs of the corresponding AND elements, the zero inputs of the second group of triggers are connected to the unit outputs of the corresponding triggers of the first group,

5 single inputs - with zero outputs of the corresponding triggers of the first group, the first inputs of the AND elements are NOT connected1 to the single outputs of the corresponding triggers of the second group, and the second inputs 0 to the zero outputs of the corresponding triggers of the second group and the second inputs of the corresponding elements AND, the installation inputs of the third group of triggers are connected to the corresponding outputs of the second switch of the 5th switch, and the sync inputs are connected to the outputs of the corresponding NAND elements, the inputs of the limiting elements are connected to a high-level input such as devices, and outputs - to information inputs

0 corresponding triggers of the third group, the outputs of which are connected to the corresponding inputs of the third switch and the inputs of the corresponding indicators. A disadvantage of such a device is5 with low didactic capabilities due to the lack of identification of racing situations such as risk at zero in the logic converter when modeling discrete devices.

0 This drawback is due to the following circumstances.

The technical means of the prototype make it possible to record racing situations of the risk type in a unit in a logic converter. However, in a simulated discrete device, racing situations such as risk at zero may occur.

Then, for fixing racing situations of both types, two situations are possible:

0 1. By the number of prototype blocks of the risk type racing control in a unit in the logic converter, it is necessary to place and assemble into the circuit a similar number of risk type control blocks of 5 risk type zero, from which the NOT element is additionally introduced. However, this significantly increases the hardware costs.

2. In each of the blocks of the prototype of racing control of the risk type, a switch and an element NOT are additionally introduced in the unit, which allow the block to fix the racing situations of the risk type at zero. But then the trainee must double-check the synthesized discrete device, performing three operations:

-analysis of a racing situation such as risk in a unit;

-connection on each of the racing control units of the logical converter of the element NOT to the useful signal circuit;

-analysis of racing situations such as risk at zero.

In this case, the analysis time of the performance of the synthesized learners of the discrete automaton substantially increases and the didactic capabilities of the device decrease.

The aim of the invention is to expand the didactic capabilities of the device.

This goal is achieved in that in a known device for teaching the basics of computer technology, comprising an operator console, the first output of which is connected to the corresponding inputs of the typesetting field and the presentation unit, the second output, the outputs of the first group and the inputs of the first and second groups, respectively, with input of the input field, inputs of the first group of the input field and inputs of the group of the presentation unit and the corresponding outputs of the input field, switches, first and second switches, triggers of the first groups whose outputs are connected to the inputs of the corresponding indicators of the first group, and the second group of triggers, according to the invention, a group of NOT elements, a first and a second group of delay elements, a group of OR elements and a second group of indicators whose inputs are connected to the outputs of the corresponding triggers of the second group and the first are introduced the inputs of the corresponding elements OR, the second inputs of which are connected to the outputs of the corresponding triggers of the first group, and the outputs to the corresponding inputs of the second switch, the outputs of the first the switch are connected to the inputs of the corresponding switches, the outputs of which are connected to the inputs of the corresponding elements NOT, the corresponding delay elements of the first group and to the zero inputs of the corresponding triggers of the first group, the single inputs of which are connected to the outputs of the corresponding delay elements of the first group and to the inputs of the corresponding delay elements of the second group, zero inputs triggers second

groups are connected to the outputs of the corresponding elements NOT, and single inputs are connected to the outputs of the corresponding delay elements of the second group.

5 In FIG. 1 shows a functional

scheme of the proposed device for teaching the basics of computer technology. In FIG. Figure 2 shows the timing diagrams of the operation of the control unit for racing elements of the vehicle. In FIG. Figure 3 shows the timing diagrams of the operation of the racing control unit of the logic converter, fixing the risk type races in the unit. In FIG. A functional diagram of a logic converter synthesized by a trainee and having a racing situation of the risk type in unit is shown. In FIG. 5 shows a time chart of the occurrence of risk type races in a unit in a logical

0 transducer synthesized by the student. In FIG. b shows the timing diagrams of the operation of the racing control unit of the logic converter, fixing the risk race at zero. In FIG. 7 depicts a functional diagram of a logic converter synthesized by a student and having a racing situation such as risk at zero. In FIG. 8 shows a timeline of the occurrence of races

0 type risk at zero in the logic converter synthesized by the learner.

A device for teaching the basics of computer technology includes an operator console 1, a unit 2 for presenting information (external input signals), a switch 3, a dial-up field 4, logic elements 5, memory blocks 6 and logic control racing blocks 7. The console 1 contains a generator of 8 single pulses, generators 9, 10 (a continuous sequence of pulses), a generator 11 (zero), a switch 12, elements 13.14 AND, a node 15 of an audio alarm, a switch 16, an element 17 OR,

5, a trigger 18, a control keyboard 19, a register 20, and a memory racing unit 21.

Block 21 comprises a switch 22, a group of modular addition elements 23

0 2, indicator 24, read-only memory block 25, switch 26, trigger 27 and indicator 28.

Logic element 5 comprises a switch 29, logical node 30, indicator 31

5 and switch 32.

Block 6 comprises a switch 33, a memory element 34, a switch 35, an indicator 36, 37, and a prediction unit 38. The node 38 contains an inverter 39, elements 40, 41 AND and element 42 OR. Indicators 36, 37 are structurally integrated into the display unit 43, and the elements 23 are the adder 44.

Block 7 contains switches 45, 46, triggers 47.48, switch 49, first 50 and second 51 indicators, element 52 NOT, first 53 and second 54 delay elements and OR element 55. The switches 3, 16. 22 are structurally placed on the typesetting field 4.

The operator panel 1 is designed to control the operation of the device for teaching the basics of computer technology and monitoring the racing of memory elements in solving problems of non-race coding and is structurally made in the form of a plastic case.

The presentation unit 2 is intended to display only input signals and synchronization signals, i.e. external input signals of simulated finite state machines, and can be performed, for example, on ALS102 LEDs.

The switch 3 is intended for switching input signals and synchronization signals and can be performed, for example, at the contacts of the plug connectors.

The type-setting field 4 is designed to accommodate and supply power to blocks 5, 6, 7 and can be implemented on the contacts of the plug connectors to which the plugs of its blocks are connected.

Logic elements 5 are designed to accommodate switches 29, 32, logical nodes 30 and indicator 1 of era 31 and are structurally made in the form of a plastic case, equipped with power supply terminals in addition to the input and output field contacts, with the help of which they are installed on a set-up field 4, which has special nests. On the top cover of the module is shown a graphical representation of the chip.

Blocks 6 are designed to accommodate switches 33, 35, memory elements 34, prediction and indication units 38, and are structurally similar to logic elements 5.

Blocks 7 are designed to detect races in logic converters and place switches 45, 46, triggers 47, 48, switch 49, indicators 50, 51, elements 52 NOT, delay elements 53, 54 and element 55 OR, are structurally made similar to logic elements 5.

The generator 8 is designed to generate single pulses and their supply to the memory elements 34 and can be implemented, for example, in the form of a button without fixing, connected by an input contact to

bus -, and the output contact to the input contact of the switch 12.

The generator 9 is designed to generate rectangular pulses with an amplitude equal to the voltage of the logical 1 and can be implemented, for example, on the 155LAZ chip.

The generator 10 is designed to generate pulses of sound frequency and can be implemented, for example, on the logic elements 155LN1.

The generator 11 is designed to set the elements 34 at the inputs to the state corresponding to the code of the first row of the transition-output table and can be implemented on a limiting resistor connected at one end to the bus - and the other to the output of the operator console 1. The switch 12 is designed to switch the mode of verifying the fulfillment of the given operating conditions of the synthesized automaton from manual to automatic and vice versa and can be implemented, for example, on microtummer MT1,

5 Element 13 And is intended to control the operation of the device.

Element 14 And is intended to control the operation of the audible alarm unit 15.

0 The audio alarm unit 15 is designed to provide an audio signal when a racing situation occurs and can be implemented, for example, on a dynamic head.

5 The switch 16 is designed to connect the blocks 7 racing control of the logical Converter to the console 1 of the operator and can be implemented, for example, on the sockets of the plug connectors,

0

The trigger 18 is designed to control the operation of the elements 13 and 14 I. As the trigger 18, for example, the element 155TM2 can be used.

5 OR element 17 is intended to control the operation of trigger 18.

The control keyboard 19 is designed to set the input signal and is a register of buttons with a latch.

The register 20 is designed to eliminate the chatter of contacts of the control keyboard 19 and contains triggers for the number of bits of the control keyboard 19.

5 Block 21 is designed to detect memory element races in solving problems of non-race coding,

The switch 22 is designed to connect the racing control unit to the switches 35 memory blocks 6

Modular elements 2 23 are designed to fix memory elements 34 that change their state, and can be implemented, for example, on AND-NOT elements.

The indicator 24 is intended to display the state of the addition elements 23 modulo 2 and can be implemented, for example, on the ALS LEDs 102.

The read-only memory unit 25 is designed to generate a single signal at the output if at least 2 logical unit signals are input, and can be implemented, for example, on the K556PT5 integrated circuit.

The unused address inputs of the node 25 must be connected to the bus - the power source, to which the chip sampling input is connected.

The switch 26 is for translating the triggers 18, 27 to the zero state.

The trigger 27 is designed to capture racing situations of the memory elements 34. As a trigger 27, for example, the element 155TM2 can be used.

The indicator 28 is designed to supply a light signal in the event of a racing situation and can be implemented, for example, on the ALS LEDs 102.

The switch 29 is designed for switching logic elements in solving the problem of logical synthesis of discrete devices and can be implemented, for example, on the socket connectors.

Logic node 30 is designed to implement the developed functional diagram of a discrete device. The logical node can be implemented, for example, on integrated circuits 155LA1. 155LA2, 155LAZ, 155LR1, 155LR2, etc.

The indicator 31 is designed to display the output state of each of the nodes 30 and can be implemented, for example, on the ALS LEDs 102.

The switch 32 is intended for switching the outputs of the logical nodes 30 when a functional circuit is set and can be implemented, for example, on the socket sockets.

The switch 33 is intended for switching the inputs of the memory elements 34 when a set of the developed functional circuit is set, and can be implemented, for example, on the socket connectors.

The memory element 34 is intended to implement the developed functional diagram. As a memory element 34

You can use, for example, K trigger 155TV1.

The switch 35 is intended for switching the outputs of the current and predicted 5 states of the memory elements 34 and can be implemented, for example, on the socket connectors.

The indicator 36 is intended to display the single state of the 0 elements of the memory 34 in the current clock cycle and can be implemented, for example, on the ALS102 LED.

The indicator 37 is intended to display the single state of the memory elements 5 in the predicted (next) clock cycle and can be implemented, for example, on the ALS102 LED.

 Prediction unit 38 is for predicting the state of memory elements 34.

The inverter 39 is designed to invert the signal from the input of the memory element 34.

Element 40 is intended for 5 logical multiplication of signals of memory element 34.

Element 41 And is intended for the logical multiplication of signals from the outputs of the inverter 39 and element 0 of the memory 34.

The OR element 42 is intended for the logical addition of signals from the outputs of the elements 40 and 41 I.

The indicating unit 43 structurally integrates 5 indicators 36 and 37 displaying the state of the memory element 34 in the current and next clock cycles.

The adder 44 constructively combines the addition elements 23 modulo 2, fixing the memory elements 34, changing their state.

The switch 45 is designed to connect the logic control unit 7 of the logic converters and the switches 32 5 of the logic elements 5 and can be implemented, for example, on the socket sockets.

The switch 46 is intended for switching the outputs of the racing control units 7 of the logic converters when racing situations occur and can be implemented, for example, on the socket sockets.

The trigger 47 is designed to record 5 the fact of the presence of risk races in the unit at the input of the race control unit 7 of the logic converters and can be implemented, for example, on element 155TV1.

Trigger 48 is designed to record the presence of risk-type races at zero on

the input of block 7 and can be implemented, for example, on the element 155TM2.

The switch 49 is designed to reset the flip-flops 47 and 48 to the zero state and can be implemented, for example, on a push-button switch with changeover type contacts.

The indicator 50 is designed to supply a light signal in the event of a risk situation in the unit in the logic converters and can be implemented, for example, on AL C 102 LEDs.

The indicator 51 is designed to supply a light signal when a risk situation occurs such as risk at zero in logic converters and can be implemented, for example, on ALS102 .. LEDs.

Element 52 is NOT intended to control the zeroing input of trigger 48.

The delay element 53 is for controlling the trigger input of the trigger 47.

Delay element 54 is used to control the clock input of the second trigger 48.

The OR element 55 is intended for the logical addition of signals from the outputs of flip-flops 47 and 48, fixing racing situations such as risk at one and risk at zero, respectively.

Connections are made by connecting wires, which in FIG. 1 are not shown.

A device for teaching the basics of computer technology works as follows.

1. Normal operation. The student, having solved the problem of logical synthesis of the functional diagram according to the given working conditions, draws it on the typesetting field 4 of blocks 5 and 6 using connecting wires (not shown) connecting the switches 3,29,32,33 and 35 in accordance with the received functional diagram.

Then he presses the switch 26 to set the triggers 27 and 18 to the zero position, providing the passage of the enable signal to the element 13 AND and the inhibitory signal to the indicator 28 and element 14 I. To build a mathematical model of the synthesized automaton, the student sets the elements using generator 11 zero 34, by inputs, the state corresponding to the code of the first row of the jump-output table. This binary state is displayed on indicators 36.

Then the student provides the input signals using the control keyboard 19, while register 20 eliminates the bounce of the keyboard contacts and acts through the block 2, which displays the binary code of the input signal, on the external inputs of the machine connected to the switch 3. At the same time, the prediction nodes 38 perceive input and output signals of the elements 34. The inverter 39 inverts the signal from the input of the element 34, the element 40 performs a logical multiplication operation on the signals from the output of the inverter 39 and the output of the element 34. Element 41 pr performs a logical multiplication operation on the signals of element 34. Element 42 performs an operation of logical addition of signals coming from the outputs of elements 40 and 41.

The function implemented by the node 34 assumes a value of logical zero if the element 34 in the subsequent clock is set to the zero state, while the indicator 27 is not lit, and the value of the logical unit is otherwise, while the indicator 27 is lit. Therefore, by reading the information on indicators 27, the trainee receives binary information marked in each cell of the transition-output table without additional operations, only by changing the combination of input signals. This makes it possible to obtain a mathematical model of the synthesized automaton, during the construction of which the trainee performs debugging of the automaton, using additional indicators 31 that display the output states of each of the nodes 30. Then, the fulfillment of the given operating conditions of the synthesized automaton in synchronous manual and automatic modes is performed using the generator 8 single pulses, generator 9 and switch 12, supplying synchronization signals through element 13 AND to the synchronization inputs of memory elements 34 with utatora 3.

In this way, the device operates similarly to the prototype.

2. The mode of analysis of the correctness of solving the problem of non-racing encoding.

The student, having typed on a typesetting field 4 of blocks 5 and b, a functional diagram of the developed discrete device with the solution of the problem of non-race coding in memory elements and constructing its mathematical model in accordance with the normal operating mode, connects the first and the second outputs of the switches 35 of the second group of devices with corresponding pairs of inputs of the switch 22 of the memory element racing control unit 21. In this case, the signals yi (t + 1) corresponding to the subsequent (predicted) state of the triggers 34, where I 17p, are removed from the first outputs of the switches 35 of the second group of the device, and the signals yi (t) corresponding to the current are taken from the second switches 35 of the second group of the device trigger state 34.

Then, by pressing the switch 26, the triggers 27 and 18 are brought back to their initial (zero) state. As a result, a zero (inhibitory) signal to the And element 14 is removed from the direct output of the trigger 18, and a single signal to the And element 13 is removed from the inverse output, allowing the device to operate. A zero signal is taken from the direct output of the trigger 27, so the indicator 28 does not light up.

After that, it is checked that the specified conditions for the operation of the synthesized automaton are fulfilled in synchronous manual and automatic modes using a single pulse generator 8, a generator 9 and a switch 12, supplying synchronization signals through element 13 AND to the synchronization inputs of memory elements 34 from switch 3 in the same way prototype (normal operation).

Suppose a memory element 34 of block 6.1 transfers from a single current state corresponding to yi (t) (Fig. 2a) to the next next state y; (r + 1) (Fig. 26). While the memory element 34 of block 6.2 (not shown) remains in the zero state both in t (Fig. 2c) and t + 1-cycles (Fig. 2d), which correspond to signals ya (t) and ya (t + 1) and all other triggers 34 of blocks 6 do not change their state. Then only at the output of the addition element 23.1 modulo 2 does a single signal appear (Fig. 2e), which is fed to the input of the AI of the read-only memory node 25, while the corresponding LED of the indicator 24 is highlighted. However, since all other inputs of the read-only memory unit 25 there are logical zero signals, then a logical zero signal is generated at its output (Fig. 2h), allowing signals from generators 8 and 9 to pass through switch 12 and AND element 13 (Fig. 2l) for the device to operate.

However, if a student made a mistake in constructing a functional diagram of the machine, which, when checking the passage of signals, leads to a simultaneous change in the state of more than one memory element 34, for example, blocks 6.1 and 6.2, i.e. element 34 of block 6.1 goes from the single state to the zero state (yi (t) 1, y1 (: + 1) 0) (Figs. 2a, b), and element 34 of block 6.2 goes from the zero state to the single state (y2 (t ) 0, y2 (t + 1) 1) (Fig. 2c, d), then at the outputs of the respective elements 23 of addition modulo 2 of the block 21 for monitoring the memory elements (element 23.2 in Fig. 1 is not shown) appear signals of a logical unit (Fig. 2e, e), arriving at the corresponding inputs of the read-only memory node 25 and displaying the LEDs of the indicator 24. The read-only memory node 25 is programmed so that upon receipt at its inputs two or more unit signals, in any combination resulting in the appearance at its output a single signal (FIG. 2g), which in a single state needs to trigger 27 (Fig. 2s), flashing the indicator 28.

In this case, the direct output of the trigger 18 is activated through the OR element 17, which supplies an enable signal to the second input of the AND element 14, allowing the passage of pulses from the generator 10 (Fig. 2i) to the audible alarm unit 15 (Fig. 2k).

In this case, the logic zero signal from the inverse output of the trigger 18 removes the permission for the pulses from the generators 8 and 9 to pass to the switching unit 3 through the 13 And circuit 13 (Fig. 2l), thereby blocking the operation of the machine. After that, the learner checks the correctness of the solution of the problem, turns off the power, re-solves the synthesis problem, re-dials the functional diagram on the input field and then again checks the fulfillment of the given conditions for the synthesized automaton to operate in synchronous manual and automatic modes.

Thus, the operation of the device is similar to the work of the prototype.

3. The analysis mode of the absence of the fact of racing in the logic converter.

The student, having received the task of synthesizing a discrete device with no races in the logic converter and having typed on a typesetting field 4 of elements 5 and blocks 6, a functional diagram of the developed discrete devices based on his constructed mathematical model in accordance with the usual operating mode, places the required number on the typesetting field (by the number of outputs of the logical converter) of the blocks 7 of the race control of the logical converter, Connects the outputs of the switches using connecting wires (not shown) 32 with the corresponding inputs of the switches 45 and the outputs of the switches 46 of the blocks 7 with the corresponding inputs of the switch 16 of the remote

1 operator. In this case, the outputs of the logic converter are removed from the outputs of the switches 32. Then, switches 26 and 49 are pressed, which returns the device to its initial state, while the signals from switch 49 reset the flip-flops 47 and 43, and then the fulfillment of the set conditions of the synthesized automaton in the Synchronous manual and automatic modes is checked using a single pulse generator 8 , generator 9 and switch 12, supplying synchronization signals through element 13 AND to the synchronization inputs of memory elements 34 from switch 3 similarly to the operation of the prototype (normal operation).

3.1. The analysis mode of the absence of the fact of racing type risk in a unit in the logic converter.

We agree that the risk in the unit corresponds to the occurrence of a logical zero for a period corresponding to (1-2) t, where r is the delay time on one logical element.

Assume that the output signal of block 7 has the form shown in FIG. For with a logical zero duration less than or equal to 2 clock cycles. Then the element 53, tuned to a delay equal to 3 t, sends a logic zero signal (Fig. Za-b) to the trigger sync input 47, putting it into a single state (Fig. Za-c), since there is a signal at its input logical unit (Fig. Za-a).

The installation of trigger 47 in a single state indicates the presence of a racing situation of the risk type in the unit in the logic converter of the discrete device under study. In this case, indicator 50 lights up, signaling the presence of risk situations such as risk in the unit in the specific output of the logic converter, and the output of the elements 55 (FIGS. Za-d) and 17 OR, which provide an enable signal to the direct input of trigger 18, is activated single state. From the direct output of flip-flop 18 (Fig. Za-d), an enable signal is supplied to the input of And element 14, allowing the passage of pulses (Fig. Za-g) from the generator 10 (Fig. Za-e) to the audible signaling unit 15. And from the inverse output of the trigger 18, a logic zero is removed, blocking the element 13 And (Fig. 3-h), stopping the operation of the device.

After that, the trainee checks the correctness of the problem solution, turns off the power, re-solves the problem of synthesizing a discrete device with no races in the logic converter, re-enters the functional diagram on the typed field and then re-checks the fulfillment of the given operating conditions of the synthesized automaton in the synchronous manual. and automatic modes.

When a logical zero signal lasting longer than 3 clocks appears, the device works differently (Fig. 36). The difference is that in the fourth measure

trigger sync input 47 is activated, but it

. remains in the zero (initial) state beyond

account feed logical zero (Fig. Zb-a) on

priority input of setting trigger 47 in

zero state (Fig. 3b-c).

Consider an example of a specific implementation. Suppose the student synthesized the logic converter shown in FIG. 4. Obviously, this circuit has a risk situation of the risk type one.

under condition a 1, c 1. A timing diagram of this situation is shown in FIG. 5. 3.2. The analysis mode of the absence of the fact of racing type risk at zero in the logic converter.

Assume that the input signal of block 7 has the form shown in FIG. ba-a with a logical unit duration of less than or equal to 2 measures. Then, at the output of element 52, NOT shifted by 1

a clock signal of a logical zero of similar duration (Fig. ba-b). Element 53, tuned to a delay of 3, supplies a signal of a logic unit to the sync input of trigger 47, which does not change its state, and the input of element 54 (Fig. Ba-c), which shifts this signal by another 1 clock cycle (Fig. ba-d) and feeds it to the trigger input of the trigger 48, at the priority input of setting the trigger to the zero state of which a logic unit signal is applied (Fig. 6a-b). As a result, the trigger 48 is brought into a single state, which indicates the presence of a risk situation of zero risk type in the logic converter of a discrete device. In this case, the indicator 51 is highlighted, signaling the presence of risk situations such as risk at zero in a specific output of the logic converter, and the output of the OR elements 55 (Fig. 6a-e) and 17 is activated, which provide an enable signal to the direct input of trigger 18, translation its in a single state. From the direct output of trigger 18 (FIG. Ba-g), an enable signal is supplied

to the input of element 14 AND, allowing the passage of pulses (Fig. ba-i) from the generator 10 (Fig. ba-z) to the audio signal assembly 15. And from the inverse output of the trigger 18 is removed a logical zero blocking element

13 And (Fig. Ba-k), stopping the operation of the device.

After that, the trainee checks the correctness of the solution of the problem, turns off the power, re-solves the problem of synthesizing a discrete device with no races in the logic converter, re-enters the function diagram on the typed field and then re-checks the fulfillment of the given operating conditions of the synthesized machine in synchronous manual and automatic modes.

When a logical unit signal appears that lasts more than 5 clocks, the device works differently (Fig. 66). The difference is that in the fourth cycle, the trigger input of trigger 48 is energized, but zeroing is not performed, since the logical O signal is applied to the priority input of setting trigger 48 to zero (Fig. Bb-b).

Consider an example of a specific implementation. Assume that the student has synthesized the logic converter shown in FIG. 7. It is obvious that this circuit has a racing situation of the risk type at zero under condition a 0, c 0, d 1. The timing diagram of this situation is shown in FIG. 8.

Claims (1)

The claims A device for teaching the basics of computer technology, comprising an operator console, the first output of which is connected to the corresponding inputs of the dialed field and the presentation unit, and the second output, the outputs of the first group and the inputs of the first and second groups, respectively, with the input of the type-setting field, the inputs of the first group of the type-setting field and the inputs of the group of the presentation unit, the corresponding outputs of the type-setting field, switches, first and second switches, triggers of the first group, the outputs of which are connected to the inputs of the corresponding indicators of the first groups, and a second group of triggers, characterized in that, in order to expand the didactic capabilities of the device, a group of NOT elements, the first and second groups of delay elements, an electronic group ORs and a second group of indicators, the inputs of which are connected to the outputs of the corresponding triggers of the second group and the first inputs of the corresponding OR elements, the second inputs of which are connected to the outputs of the corresponding triggers of the first group, and the outputs - to the corresponding inputs of the second switch, the outputs of the first switch are connected to the inputs of the corresponding switches, the outputs of which are connected to the inputs of the corresponding elements NOT, the corresponding delay elements of the first group and to the zero inputs of the corresponding triggers of the first group, the single inputs of which are connected to the outputs of the corresponding delay elements of the first group and with the inputs of the corresponding delay elements of the second group, the zero inputs of the triggers of the second group are connected to the outputs of the corresponding elements of NOT, and the single inputs to the outputs of the corresponding delay elements of the second group.  IT YY -.- Y v # Si FIG. 4 & & 2f sixteen mind & W No gz 23g 2. 27, Yu Yu N thirteen Jl ) "; ; imniniiniiiiimi Fig-z Pu. " 3 Jl 8 8r & FIG. 4 0  / Thebes 6 and 9 I f FIG. 7 so you 4 2 5 Zx (P