RU1775728C - Device for teaching computer engineering principles - Google Patents

Abstract

The invention relates to educational and laboratory equipment and can be used in the educational process, as well as in design offices for modeling and debugging discrete devices built on integrated circuits. The device allows expanding didactic possibilities. The device comprises an operator panel, a unit for presenting information (external input signals), a switch, a typesetting field, logic elements, memory units and racing control units of the logic converter 5 or.

Description

The invention relates to educational laboratory equipment and can be used in the educational process, as well as in design bureaus for modeling and debugging discrete devices built on integrated circuits.

A device for teaching the basics of computer technology is known, comprising an operator console consisting of a single pulse generator, a continuous pulse train generator, a type of work switch, a zero generator, a control keyboard and trigger blocks, an indication unit, a switch, a dial-up field, logic elements modules, consisting of two switches, logic elements and a display unit, trigger modules, consisting of two switches, a memory element, indicators and a prediction unit, consisting of the inverter, and the two elements and the OR

The disadvantage of this device is the low didactic capabilities for

due to the lack of identification of racing situations in the logic converter when modeling discrete devices. A device for teaching the basics of computer technology is also known, comprising an operator console, a unit for presenting information (external input signals), a switch, a dial-up field, logic elements and memory units. The operator panel contains a single pulse generator, a continuous pulse train generator, a zero generator, a switch, an AND element, a control keyboard, a register, a memory element racing control unit comprising a switch, a group of addition elements modulo 2, the first and second indicators, a constant block memory, switch, trigger, continuous pulse generator, AND element, and an audible alarm unit. A logical element contains two switches, a logical node, an indicator. The memory block contains two switches, a memory element, two indicators and a node

to

WITH

H

VI ate VI

go with

prediction comprising an inverter, two AND elements, an OR element.

A disadvantage of such a device is its low didactic capabilities due to the lack of "identification of the genetic situations of the logic converter when modeling discrete devices."

Closest to the technical essence of the present invention is a device for teaching the basics of computer technology, comprising an operator console, a unit for presenting information (external input signals), a switch, a dial-up field. logic elements, memory blocks and logic control racing blocks The operator panel contains continuous pulse train generators, a zero generator, a switch, first and second AND elements, an audio signaling unit, a switch, an OR element, a trigger, a control keyboard, a register and a memory element racing control unit containing a switch, a group of elements modulo 2 additions, indicator, read-only memory, switch, trigger and indicator. The logical element contains the first and second switches, a logical node and an indicator. The memory unit contains the first and second switches, the memory element, the first and second indicators and the prediction unit containing the inverter, the first and second AND elements, and the OR element. The control unit of the race of the logical converter contains the first and second switches, the first, second and third triggers, a switch, an AND element, an AND-NOT element and an indicator, the first output of the operator panel being connected to the corresponding inputs of the information presentation unit and to the corresponding inputs of the first group the dialed field, the inputs of the group of the operator panel are the corresponding inputs of the first group of the device, the inputs of the second and third groups and the outputs of the first and second groups of the dialed field are with the corresponding inputs and the outputs of the device, the inputs of the first switch are the corresponding inputs of the first group of the device, the inputs of the group of the OR element are connected to the corresponding outputs of the first switch, and the input with the third output of the operator console, a single input of the trigger is connected to the output of the OR element, the zero input is to the fourth output operator panel, and the zero and single outputs are to the first and second inputs of the operator panel, respectively, the inputs of the second switch are the corresponding inputs of the fifth group of the device, the outputs of the third Mutator are the corresponding outputs of the third group of devices, the first inputs of AND elements are connected to the outputs of the corresponding switches, the unit inputs of the first group of triggers are connected to the corresponding outputs of the second switch, and the zero inputs are to the outputs of the corresponding elements of AND, the zero inputs of the second group of triggers are connected to the unit outputs the corresponding triggers of the first group, single inputs with zero outputs of the corresponding triggers of the first group, the first inputs of the elements are NOT connected to the individual outputs of the corresponding triggers of the second group, and the second inputs to the zero outputs of the corresponding elements AND, the installation inputs of the third group of triggers are connected to the corresponding outputs of the second switch, and the clock inputs are connected to the outputs of their elements AND, NOT, the inputs are restrictive elements are connected to the input of the device’s high voltage level, and the outputs are connected to the information inputs of the corresponding triggers of the third group, the outputs of which are connected to the corresponding inputs of the third switch and input rows of relevant indicators.

A disadvantage of such a device is its low didactic capabilities.

This drawback is due to the following considerations.

The technical means of the prototype make it possible to record racing situations of the risk type in a unit at the output of the logic converter, however, the duration of the risk pulse is not measured. Therefore, the trainee needs to spend a lot of time to determine the portion of the circuit of the synthesized discrete automaton that leads to the racing situation.

The aim of the invention is to expand the didactic capabilities of the device while reducing the debugging time of the synthesized discrete automaton.

The goal is achieved in that a device for teaching the basics of computer technology, containing an operator console, the first output of which is connected to the corresponding inputs of the dialed field and the presentation unit, and the second output, the outputs of the first group and the inputs of the first and second groups, respectively, with the second input the type-setting field, the inputs of the first group of the type-setting field and the inputs of the group of the presentation unit and the corresponding outputs of the type-setting field, the output of which is connected to the unit input of the first trigger, the left input of which is connected to the output of the And element, the first input of which is connected to the output of the first switch, the input of which is connected to the power bus, the output of the second trigger is connected to the second input of the And element, the output of the third trigger is connected to the third input of the dialed field and the indicator input, according to the invention group triggers, a second switch and group indicators, the inputs of which are connected to the unit outputs of the first trigger and the corresponding triggers with unit outputs of the first trigger and the corresponding their group triggers, the output of the type-setting field is connected to the sync inputs of the group triggers, the first, second and third triggers, the information input of the second trigger is connected to the power bus, the output is to the information input of the third trigger, the installation inputs of the third trigger and group triggers are connected to the output of the And element, the zero input to the second trigger is connected to the output of the first switch, and the single input is connected to the output of the second switch, one input of which is connected to the zero output of the first trigger and the single input of the first group trigger, in another input - to the zero output of the last group trigger, and the group inputs of the second switch are connected to the unit inputs of the corresponding group triggers, except the first, and the zero outputs of the corresponding triggers except the last.

Figure 1 shows a functional diagram of the proposed device for teaching the basics of computer technology. Figure 2 shows the timing diagrams of the operation of the memory element racing control unit. Fig. 3 shows the timing diagrams of the operation of the racing control unit of the logic converter, fixing a false negative signal with a duration of less than or equal to 5 and ignoring a useful zero signal. Fig. 4 shows a functional diagram of a logic converter synthesized by a student and having a racing and risk type situation in the unit with a false signal duration of 2 clock cycles. Fig. 5 is a timing chart of the occurrence of risk type races in unit with a spurious signal duration of 2 clocks in a logic converter synthesized by a student.

A device for teaching the basics of computer technology includes an operator console 1, a unit 2 for presenting information (external input signals), a switch 3, a dial-up field 4, logic elements 5, memory blocks 6 and logic control racing blocks 7.

The console 1 contains a generator 8 of single pulses, a generator 9, 10 (continuous pulse train), a generator 11 (zero), a switch 12, elements 13, 14 AND, a sound alarm unit 15, a switch 16, an OR element 17.

a flip-flop 18, a control keyboard 19. a register 20 and a memory element racing control unit 21.

Block 21 comprises a switch 22, a group of modular 2 addition elements 23, an indicator 24, a read-only memory block 25, a switch 26, a trigger 27, and an indicator 28.

Logic element 5 comprises a switch 29, logical node 30, indicator 31

and switch 32.

Block 6 comprises a switch 33, a memory element 34, a switch 35, indicators 36, 37, and a prediction unit 38. The node 38 contains an inverter 39, elements 40, 41 And and

element 42 OR. Indicators 36, 37 are structurally integrated into the display unit 43, and the elements 23 are the adder 44.

Block 7 contains switches 45, 46, triggers 47.1 ... 47 V, 48, 49 switches

50, 51, element 52 AND, indicator 53 and a group of indicators 54.1 ... 54. B.

Switches 3, 16, 22.29, 32.35, 45, and 46 are combined in the composing field 4.

Connections are made by connecting wires, which are not shown in Fig. 1.

A device for teaching the basics of computer technology works as follows.

1. Normal operation.

The student, having solved the problem of the logical synthesis of the functional diagram according to the given working conditions, collects it on the typesetting field 4 of blocks 5 and 6 using

connecting wires (not shown) connecting the switches 3,29,32,33 and 35 in accordance with the obtained functional diagram.

After that, he presses the switch 26 to set the triggers 27 and 18 to the zero position, ensuring the passage of the enable signal to the element 13 AND and the inhibitory signal to the indicator 28 and element 14 I. To build a mathematical model of the synthesized automaton, the student learns using the generator 11 zero elements 34 on inputs to the state corresponding to the code of the first row of the transition-output table.

This state in binary code is displayed on indicators 36

Then the learner supplies the input signals using the control keyboard 19, while the register 20 eliminates the bounce of the keyboard contacts and acts through the block 2, which displays the binary code of the input signal, on the external inputs of the machine connected to the switch 3. In this case, prediction nodes 38 are perceived input and output signals of the elements 34. The inverter 39 inverts the signal from the input of the element 34, the element 40 performs a logical multiplication operation on the signals from the output of the inverter 39 and the output of the element 34. Element 41 pr performs a logical multiplication operation on the signals of element 34. Element 42 performs an operation of logical addition of signals coming from the outputs of elements 40 and 41.

The implemented function assumes a value of logical zero if the element in the next measure is set to the zero state, while indicator 27 is not lit, and the value of the logical unit is otherwise, while indicator 27 is lit. Therefore, by reading the information on indicators 27, the trainee receives binary information marked in each cell of the transition-output table without additional operations, only by changing the combination of input signals. This makes it possible to obtain a mathematical model of the synthesized automaton, during the construction of which the trainee performs debugging of the automaton, using additional indicators 31 that display the output states of each of the nodes 30. Then, the fulfillment of the given operating conditions of the synthesized automaton in synchronous manual and automatic modes is performed using the generator 8 single pulses, generator 9 and switch 12, supplying synchronization signals through element 13 AND to the synchronization inputs of memory elements 34 with utatora 3.

Thus, the operation of the device is similar to the work of the prototype.

2. The mode of analysis of the correctness of solving the problem of non-racing encoding.

The student, having typed on a typing field 4 of blocks 5 and 6, a functional diagram of the developed discrete device, with the solution of the problem of non-race coding in memory elements and constructing its mathematical model in accordance with the usual

operation mode, connects using the connecting wires (not shown) the first and second outputs of the switches 35 of the second group of devices with the corresponding pairs of inputs of the switch 22 of the memory element racing control unit 21. In this case, signals corresponding to the last (predicted) state of the triggers 34 are removed from the first outputs of the switches 35 of the second device group, and signals corresponding to the current state of the triggers 34 are removed from the second outputs of the switches 35 of the second device group. Then, pressing switch 26, transfers 5 triggers 27 and 18 to the initial (zero) state. As a result, a zero (inhibitory) signal to the And element 14 is removed from the direct output of the trigger 18, and a single signal to the inverse output

0 element 13 AND, allowing the operation of the device. A zero signal is taken from the direct output of the trigger 27, so the indicator 27 does not light up. After that, the fulfillment of the given conditions for the operation of the synthesized automaton in the synchronous manual and automatic modes is checked using a single pulse generator 8, a generator 9 and a switch 12, supplying synchronization signals through the element

0 13 And to the inputs of the synchronization of memory elements 34 from the switch 3 similarly to the prototype (normal operation).

Suppose that the memory element 34 of block 6.1 goes from a single current state 5 (Fig. 2a) to the next zero state (Fig. 26). While the memory element 34 of the block 6.2 (not shown) remains in the zero state both in the next (Fig.2c) and the next (Fig.2d), and all the other triggers 34 of the blocks 6 do not change his condition. Then, only at the output of the addition element 23.1 modulo 2 does a single signal appear (Fig.2d), which is input to the read-only memory node 25, highlighting

5, the corresponding LED of the indicator 44. However, since the logic zero signals are present at all other inputs of the read-only memory block 25, a logic zero signal is generated at its output

0 (Fig. 2g), therefore, the trigger 27 remains in the zero (initial) state (Fig. 2h), allowing signals from the generators 8 and 9 to pass through the switch 12 and the And element 13 (Fig. 2l) for the operation of the device.

5 However, if the trainee, when constructing the functional diagram of the machine, made a mistake which, when checking the passage of signals, leads to a simultaneous change in the state of more than one memory element 34, for example,

61 and 62, i.e. the element 34 of the block 61 goes from the single state to the zero state (Fig. 2a. b), and the element 34 of the block 62 goes from the zero state to the single state (Fig. 2c, d), then at the outputs of the corresponding modular 2 addition elements 23 block 21 monitoring the memory elements (element 232 is not shown in FIG. 1), signals of a logical unit appear (Figs. 2e, e) arriving at the corresponding inputs of the read-only memory block 25 and displaying the corresponding indicator diodes 24. Block 25 the read-only memory is programmed in such a way that when two inputs are received or more single signals in any combination leads to the appearance of a single signal at its output (Fig. 2g), which puts the trigger 27 in a single state (Fig. 2h), illuminating indicator 28.

In this case, the direct output of the trigger 18 is excited through the OR element 17, which supplies an enable signal to the second input of the AND element 14, allowing the passage of pulses from the generator 10 (Fig. 2i) to the audible alarm unit 15 (Fig. 2k).

In this case, the logic zero signal from the inverse output of the trigger 18 removes the permit for the passage of pulses from the generators 8 and 9 to the switching unit 3 through the circuit 13 And (fig.2l), thereby blocking the operation of the machine. After that, the student checks the correctness of the solution of the problem, turns off the power, re-solves the synthesis problem, again dials the functional diagram on the dialed field and then again checks the fulfillment of the given conditions for the synthesized automaton to operate in synchronous manual and automatic modes.

Thus, the operation of the device is similar to the work of the prototype.

3. The analysis mode of the absence of the fact of racing in a logical converter of the risk type in unit.

The student, having received the task of synthesizing a discrete device with no races in the logic converter and typing 4 of blocks 5 and 6 on a typesetting field into the functional diagram of the developed discrete device based on constructing its mathematical model in accordance with the usual mode of work, places the required number of the number of outputs of the logical converter block 7 racing control of the logical converter. Connects through the wires (not shown) the outputs of the switches 32 with the corresponding

the inputs of the switches 45 and the outputs of the switches 45 blocks with the corresponding inputs of the switch 16 of the console 1 operator. In this case, the outputs of the logic converter are removed from the outputs of the switches 32. Then, having analyzed the discrete automaton, the student estimates the number of pairs of logical elements on which the signal can be delayed, and switches the switch 51 to the corresponding position. Suppose a student estimates that the signal can be delayed by 10 elements, and therefore sets the switch 51 to the fifth position, thereby connecting the inverse output of the group trigger 47.5 to the priority input of the installation in the single state of the trigger 48 (trigger 47.5 in figure 1 not shown). Then, the switches 25 and 50 are pressed, returning the device to its initial state, while the signal from the switch 50 through element 52 And resets the triggers 47.1 ... 47. B, 48.49, if they were not reset to zero from the trigger output 48, after which verification of fulfillment of the given operating conditions of the synthesized automaton in synchronous manual and automatic modes is performed using a single pulse generator 8, a generator 9 and a switch 12,

0 supplying synchronization signals through element 13 AND to the synchronization inputs of memory elements 34 from switch 3 similarly to the operation of the prototype (normal operation). Assume that the input signal on the switch 45 has the form shown in Fig. 3, and with a logic zero duration of 4 clock cycles. In this case, due to the appearance of a logical zero at the priority input of the unit to the single state

0 of the first 47.1 trigger of the group, it will be set to a single position (measure 2, figa-b), the first indicator of the group 55.1 will be highlighted, and in the third measure its inverse output will be reset to zero due to the inertial properties of logic elements, by which it is realized (measure 3, fig. Za-v).

The appearance of a logic zero at the inverted output of trigger 47.1 will cause a logical zero at the priority input of the unit to enter the single state of trigger 47.2, as a result of which, for the previously described reason, a logical unit of 4 cycles appears directly with the second 54.2 the group indicator to logical zero in a 5th cycle on the inverse outputs of the second 47.2 group trigger (Figs. Za-g, e), respectively.

But since in the next 5 clock cycle a single signal is restored (Fig. Za-a)

at the output of the switch 4, the acting non-sync input of the trigger 49, and a signal of a logical unit is constantly present at its information input; according to the latter, it is transferred to the single state (FIG. 3a) with the indicator 53 illuminating, signaling the presence of a risk situation of the risk type in the unit in a specific output from the logic converter of the discrete device under study. In this case, the two group indicators 54.1 and 54.2 highlighted signal that the logical zero signal has a duration equal to 4 clock cycles, i.e. the flashing of each group indicator corresponds to a logic zero signal duration of 2 clock cycles.

In this case, the output of the OR element 17 is excited, which supplies an enable signal to the direct input of the trigger 18, which is brought into a single state (Fig. Za-n). From the direct output of the trigger 18, an enable signal is supplied to the second input of the And element 14 (Fig. Za-p), allowing the passage of pulses from the generator 10 (Fig. Za-o) to the audible signaling unit 15, and a logic zero blocking from the inverse output element 13 AND (Fig. Za-p) stops the operation of the device

After that, the trainee checks the correctness of the solution of the problem, turns on the power, re-solves the problem of synthesizing a discrete device with no races in the logic converter, re-enters the function diagram onto the typed field, and then re-checks the fulfillment of the given conditions of the synthesized machine operation in the synchronous manual and automatic modes.

When a logical zero of a longer duration appears, for example, equal to 13 clock cycles, corresponding to a useful signal, the device works differently (Fig. Zb). The difference is that the appearance of a logical zero on the inverted output of the fifth 47.5 group trigger will cause a logical zero through the switch 51 at the priority input of the installation to the single state of the trigger 48, to the sync input of which a logic zero signal has been sent which translates the trigger 48 into a single state (Fig. Zb-l) from the inverse output of which a logic zero signal (Fig. 3b-m) through element 52 And transfers the triggers 47.1 ... 47, B to the initial (zero) state. At the same time, the indicators of group 54.1 ... 54. B do not have time to be highlighted due to their inertial

Claims (1)

properties. Then, from the output of the first switch 45, the leading edge of the signal of the logical unit (clock 14, Fig. Za-b) does not turn trigger 49 into a single state, since at its information input, a logic zero signal is supplied from the inverse output of trigger 48. At the same time, trigger 48 is reset. SUMMARY OF THE INVENTION A device for teaching the basics of computer technology, comprising an operator panel, the first output of which is connected to the corresponding inputs of the dialed field and the presentation unit, and the second output is the outputs of the first group and the inputs of the first and second groups, respectively, with the second input of the dialed field, inputs the first group of the dialed field and the inputs of the group of the presentation unit and the corresponding outputs of the dialed field, the output of which is connected to a single input of the first trigger, the zero input of which the second is connected to the output of the element And, the first input of the element And is connected to the output of the first switch, the input of which is connected to the power bus, the output of the second trigger is connected to the second input of the element And, the output of the third trigger is connected to the third input of the dialed field, and the indicator input, that, in order to expand the didactic capabilities of the device, group triggers, a second switch and group indicators, the inputs of which are connected to the unit outputs of the first trigger of the corresponding group triggers, are introduced into it, the output of the dial-up floor is connected to the sync inputs of the triggers of the group, the first, second and third triggers, the information input of the second trigger is connected to the power bus, the output is to the information input of the third trigger, the installation inputs of the third trigger and group triggers are connected to the output of the And element, zero input the second trigger is connected to the output of the first switch, and a single input is connected to the output of the second switch, one input of which is connected to the zero output of the first trigger and the single input of the first trigger of the group, second input - to a zero output of the last flip-flop group and a second group of switch inputs coupled to respective inputs of flip-flops unit group other than the first, and the respective outputs zero trig- gzrov except the last 5"./ -h ".g c 0 / rr + tS-t "" 5-1 a TT .-- T T.Y --- T 3 " Ffl il I  h i- -i ge /  ru . 9ui, / XX W 1 su (9J f / rf 1-j c t- L -us . I 5 4 7./-7 m Ej -j -j SL -J u so / ik fiN d e to