RU176149U1 - A device for processing a phase-shifted signal with discrete phase adjustment in an executive instrument of a radio control line - Google Patents

Abstract

The utility model relates to the field of information transmission systems over the radio channel and can be used in the construction of executive devices (IP) of radio control lines (RLS) working with phase-shift keyed signals. The technical result of the utility model is a substantial (almost two-fold) increase in the noise immunity of RLS. The relevance of increasing the noise immunity of the RLU is determined by the complex radio noise environment in the HF band, as well as the importance of the tasks to be solved related to the undermining of explosive and UPS charges. , shift register 3, reference generator 4, signal multiplier 5, adder 6, amplitude limiter 7, random access memory 8, block x injured command codes 9, comparison circuit 10, integrator 11 and threshold device 12. A device for processing a phase-shifted signal with discrete phase adjustment in an executive device of a radio control line can substantially, almost double, increase the noise immunity of a radio control line in comparison with a radio-frequency signal operating with an FM signal . 1 ill.

Description

The utility model relates to the field of information transmission systems over the radio channel and can be used in the construction of executive devices (IP) radio control lines (RLU), working with phase-shift keyed signals.

Radio lines are known for transmitting telemetric, connected, command, and other information when using various types of modulation and coding [1]. Also known are the BSFZ-04.10 set of quickly deployable technical means of physical protection and the AKRSS automated reconnaissance and signaling system [2, 3], the main disadvantage of which is operation at frequencies of about 400 MHz, which is associated with a large absorption of signals by the underlying surface on the radio path, as well as the propagation of radio waves deep into the ground.

The closest in technical essence to the claimed device is the RPZ-8 radio-electronic means selected as a prototype for detonating explosive charges (explosives) and engineering ammunition (UPS), simulating artillery fire and air strikes during military exercises. This tool works in the short-wave (HF) frequency range and is characterized by lower signal energy losses during the propagation of radio waves along the earth's surface and in the ground [4].

The signal processing device in RPZ-8 contains a frequency-manipulated (FSK) signal processing path in which the FSK signal is fed to the inputs of two matched filters SF ₁ and SF ₂ tuned to frequencies f ₁ and f ₂ , from SF _{1 the} signals are sent to series-connected squaring circuits KV ₁ and integrator INT ₁ , and from the output of SF ₂ , respectively, to squaring circuits KV ₂ , integrator INT ₂ and inverter INV, from the outputs of the integrator INT ₁ and inverter INV signals go to the adder SM, the output of which is connected to the amplitude ogre OGR nickel, the OGR output is connected to the RAM random access memory input, the RAM output is connected to the input of the SS comparison circuit, the second SS input receives a signal from the output of the BHCC command code storage unit, the signal from the output of the SS comparison circuit is fed to the input of the INT ₃ integrator, output INT _{3 is} connected to the input of the threshold device PU, the output of the PU is the output of the signal processing device [4].

The most significant drawback of this device is the low noise immunity, which is determined by the presence of non-linear devices (squaring circuits KV ₁ , KV ₂ ) in the processing path of the FSK signal, where a weak signal is suppressed by interference.

The technical result of the utility model is a substantial (almost two-fold) increase in the noise immunity of the RLU. The relevance of improving the noise immunity of the RLU is determined by the complex radio interference in the HF band, as well as the need to ensure a high probability of the correct reception of the control command (KU) by the RLU actuator at the installation site.

This technical result is achieved by the fact that instead of the signal processing device RPZ-8, instead of the signal processing path of the FSK signal (SF _1, SF ₂ , KV ₁ , KV ₂ , INT ₁ , INT ₂ , INV), an analog signal is introduced to process the phase-manipulated (PSK) signal -digital converter ADC, digital matching filter CSF, shift register RG, reference generator OG and multiplier signals PM.

In FIG. 1 shows a diagram of a device for processing a phase-shifted signal with discrete phase adjustment in an executive device of a control line, comprising an analog-to-digital converter 1, a digital matched filter 2, a shift register 3, a reference generator 4, a signal multiplier 5, an adder 6, an amplitude limiter 7, random access memory device 8, a storage unit for command codes 9, a comparison circuit 10, an integrator 11, and a threshold device 12.

A device for processing a phase-shifted signal with discrete phase adjustment in an executive device of a radio control line operates as follows. The input analog signal at an intermediate frequency f _{c is} fed to the input of the analog-to-digital converter 1, where signal samples with discreteness, for example, 16 samples per period, are formed. Digital matched filter 2 is matched with the spectrum of the input signal, duration T _e . The samples of the signal from the output of the digital matched filter 2 with a frequency f _zn = 16f _{c are} recorded in the shift register 3 with a capacity of 16 samples. Between the clock cycles of recording the signal samples in the shift register 3 with a frequency f _sc1 = 16f _zp , information is read from the shift register 3, which is fed to the input of the signal multiplier 5. The signal from the output of the reference generator 4 with the read frequency f _g is fed to the second input of the signal multiplier 5 = f _sc1 , that is, the signal period of the reference generator 4 will be multiplied in the signal multiplier 5 with 16 samples from the shift register 3 in the information reading mode. The results of multiplying 16 samples of the input signal with the signal of the reference generator are summed in the adder 6, the result is limited (0 - with a negative sum, 1 - with a positive sum) in the amplitude limiter 7 and is written to the random access memory 8.

After shifting the information in the shift register 3 by one bit, reading the signal samples, multiplying, summing, limiting and recording the result in the next cell of random access memory 8 is repeated. After 16 cycles of information shift in shift register 3 in 16 cells of RAM 8 (a cell in each row), information will be recorded characterizing the results of multiplying the input signal with the reference oscillation during a discrete phase shift of the input signal by 1/16 of the period. If there are k periods for a signal element of duration T _e , and the control command consists of n elements, then the required RAM capacity is defined as 16 xkxn bits (16 lines of kxn cells). At each shift of information in the shift register 3, it is necessary to read information from n cells of the line of RAM 8, taken evenly through k elements, which will correspond to the received code combination (QC). The read QC is compared in comparison circuit 10 with the reference code of the instruction code storage unit 9. Thus, for 16 cycles of changing information in shift register 3, from RAM 8 information from 16 lines of n elements will be read, which corresponds to shifts of the input signal by one period with discreteness of 1/16 period. The result of comparing each bit of the control command is accumulated in the integrator 11, and after comparing all n bits, the result goes to the input of the threshold device 12. When the set threshold is exceeded, a decision is made to receive the expected control command.

At each shift of information in the shift register 3, a write operation is performed in RAM 8 and parallel reading of n elements from RAM. Thus, the required speed of the device will be determined by the clock frequency n⋅f _zp . For example, with f _c = 10 kHz, n = 64 elements and a discrete phase adjustment after 1/16 of the signal period, the maximum clock frequency will be f _max = 10.24 MHz.

The change in the signal level at the output of the adder 6 depending on the stability of the frequency of the processed signal Δω and the number of discrete adjustments for the signal period is described by the expression

Where

n is the number of elements (bits) of duration T _e in the control command block;

ξ _p is a random number with a uniform distribution (0, 1);

K _ϕ is the number of discrete phase adjustments for the signal period (K _ϕ = 16).

Thus, a device for processing a phase-shifted signal with discrete phase adjustment in an executive device of a radio control line can substantially, almost double, increase the noise immunity of a radio control line in comparison with a radio-frequency signal operating with an FSK signal.

Literature.

1. Teplyakov N.M., Kalashnikov I.D., Roshchin B.V. Radio lines of space information transmission systems. Ed. THEM. Teplyakova. Textbook for universities. - M .: “Owls. Radio ", 1975. - 400 p.

2. BSF3-04.10. Manual. DAKZH.421452.004 RE.

3. AKRSS. Manual. DAKZH.421452.005 RE.

4. Radio-electronic means of undermining charges RP3-8. -M .: VIU, 2000 .-- 52 p.

Claims (1)

A device for processing a phase-shifted signal with discrete phase adjustment in an executive device of a radio control line, comprising an adder 6, the output of the adder 6 connected to the input of the amplitude limiter 7, the output of the limiter 7 connected to the input of random access memory 8, the output of random access memory 8 connected to the input of comparison circuit 10 , the second input of the comparison circuit 10 is connected to the output of the code combination storage unit 9, the output of the comparison circuit 10 is connected to the input of the integrator 11, the output of the integrator 11 connected to the input of the threshold device 12, the output of the threshold device 12 is the output of the device, clock pulses with a read / write frequency of ƒ _sc2 , ƒ _sn are fed to the control inputs of the random access memory 8, clock pulses with a read frequency are _sent to the control input of the code combination storage unit 9 ƒ _sch2, wherein the analog-to-digital converter 1, whose input is the input device, the output of analog-to-digital converter 1 is connected to the input of the digital matched filter 2, the output y matched filter 2 is connected to the input of the shift register 3, the output of the shift register 3 is connected to the input of the signal multiplier 5, the second input of the signal multiplier 5 is connected to the output of the reference generator 4, the output of the signal multiplier 5 is connected to the input of the adder 6, to the control inputs of analog-digital a converter 1 and a digital matched filter 2, clock pulses with a recording frequency of ƒ _{zp are supplied} , and clock pulses with a reading frequency of ƒ _cc1 are fed to the control inputs of the shift register 3 and the adder.

Images