RU2714302C1 - Method and device for receiving frequency-stabilized signals with binary phase-shift keying at unknown initial phase - Google Patents

Abstract

FIELD: radio engineering and communications.

SUBSTANCE: invention relates to systems for transmitting information over a radio channel and can be used in constructing executive devices (ED) of command control radio lines (CCRL) operating with binary phase-shift keying signals. When implementing the method of receiving frequency-stabilized binary phase manipulation signals in an unknown initial phase, a three-channel system for receiving frequency-stabilized binary phase-shift keyed signals is used, where signals of reference generators of each of channels have phase shift equal to π/3, relative to each other and operation of threshold devices in each of three channels is organized in direct and inverse mode. Power loss of the proposed device compared to the scheme of ideal synchronization of receiving the phase-shift keyed signal will make about 0.45 dB (by power), which is acceptable. Device for receiving frequency-stabilized signals with binary phase-shift keying at unknown initial phase contains analogue-to-digital converter of ADC 1, digital matched filter of DMF 2, a unit for storing code combinations USCC 8, a logical element OR 11 and three identical signal processing channels, each of which consists of a multiplier of signals MP 3, a reference generator G 4, a low-pass filter LPF 5, amplitude limiter AL 6, comparison circuit CC 7, integrator INT 9 and threshold device TD 10. Urgency of reducing hardware costs is determined by the need to implement ED CCRL in an autonomous version with minimum current consumption.

EFFECT: significant (almost fivefold) reduction of hardware costs when implementing a scheme for receiving frequency-stabilized signals with binary phase-shift keying at unknown initial phase.

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Description

The invention relates to the field of information transmission systems over the radio channel and can be used in the construction of executive devices (IP) command radio control lines (KRU), working with signals of binary phase shift keying.

Radio lines are known for transmitting telemetry, communication, command, and other information when using various types of modulation and coding [1]. Also known are a set of quickly deployable physical protection equipment BSFZ-04.10, an automated complex of reconnaissance and signaling devices AKRSS and electronic weapons RPZ-8 for detonating explosive charges (explosives) and engineering ammunition (UPS), simulating artillery fire and air strikes during military exercises [2, 3, 4], the main disadvantage of which is the work with signals of frequency telegraphy (BT). The most effective, from the point of view of noise immunity, are phase telegraphy (FT) signals, work with which allows you to get closer to the potential noise immunity. Working with FT signals places increased demands on the system for frequency instability and signal reception synchronization.

The closest in technical essence to the claimed method and device is a device for processing a phase-shifted signal with discrete phase adjustment in an executive device of a radio control line [5], selected as a prototype. This device allows you to receive phase-shifted signals that do not require frequency adjustment, but only phase adjustment.

A phase-manipulated signal processing device with discrete phase adjustment in an executive device of a radio control line contains an analog-to-digital converter (ADC) whose output is connected to the input of a digital matched filter (CSF), the output of which is connected to the input of the shift register RG, the output of which is connected to the first input of the signal multiplier (PM), the second input of which is connected to the output of the reference generator (G), the output of the PM is connected to the input of the adder (SUM), the output of which is connected to the input of the signal limiter ( GR), the output of which is connected to the input of random access memory (RAM), the output of which is connected to the input of the comparison circuit (CC), the second input of which is connected to the output of the code combination storage unit (BHCC), the output of the SS is connected to the input of the integrator (INT) output which is connected to the input of the threshold device PU.

The most significant drawback of this device is the large hardware costs required to implement a multi-channel discrete phase adjustment system. Sixteen channel system provides phase adjustment with an accuracy of no more than π / 32, which determines the acceptable loss of the level of the useful signal and the possibility of further signal processing.

The technical result of the invention is a substantial (almost five-fold) reduction in hardware costs when implementing a scheme for receiving frequency-stabilized signals with binary phase shift keying with an unknown initial phase. The relevance of reducing hardware costs is determined by the need to implement switchgear switchgear in an autonomous version with minimal current consumption.

This technical result is achieved by the fact that:

1) in the device for receiving frequency-stabilized signals with binary phase shift keying with an unknown initial phase, instead of sixteen channels of discrete phase adjustment, only three channels are used;

2) The threshold device (PU) makes a positive decision to transmit a control command (KU) when the required number of elements of the KU block matches or the same number of errors is made that will correspond to the inverse reception of the KU;

3) making the final decision on accepting KU in accordance with the positive decision on taking KU in at least one of the channels.

One of the main reasons for the deterioration of the noise immunity of digital communication systems is a phase synchronization error. The figure 1 shows the position of the points of the constellation of binary phase shift keying (FM-2) when the phase of the received signal deviates by an angle ϕ.

From figure 1 it can be seen that the distance to the boundary between the decision areas on the zero / unit value of the transmitted bit in the presence of a phase error decreases in proportion to its cosine. Thus, in the formula for the probability of a bit error, it is necessary to multiply the argument of the Q-function by cosφ:

If the phase error is a random variable with probability density p _ϕ (ϕ), it is necessary to average (1) in accordance with the probabilistic properties of ϕ [6]:

For a uniform distribution of the phase error, this expression takes the form:

where a, b are the boundaries of the change in the random value of the phase ϕ.

The graph of the probability of a bit error P _b (ϕ) depending on the random value of the phase ϕ is presented in figure 2, according to expression (1). The calculation was performed by the method of numerical integration in the Matlab program for the signal-to-noise ratio (S / N) (E _b / N ₀ = -2 dB).

An analysis of the graph (figure 2) of the bit error probability P _b (ϕ) versus phase shows that this function is symmetric as well as the cos function with respect to ϕ = 0. The minimum probability of a bit error P _b (ϕ = 0) is observed at zero bias (perfect synchronization), which corresponds to the theoretical value of P _b (depending on the S / N ratio E _b / N ₀ ). The maximum probability of a bit error P _{b is} not the worst case scenario, since it can be stated that the bit was received incorrectly. With a phase shift ϕ equal to plus, minus π / 2, the probability of a bit error is equal to P _b = 0.5, which is the uncertainty and the worst case of signal reception. Thus, taking into account the possibility of working with inverse signals, a discrete adjustment of the signal must be performed in the range of phase change ϕ from 0 to π / 2.

(3) для одного канала приема ФТ сигнала представлена в таблице (фигура 3) (фаза имеет равномерный закон распределения, интегрирование в пределах ϕ от 0 до π/2. Этот интеграл был вычислен численно, программа кода написана на языке Matlab. Анализ вероятности битовой ошибки P_b при идеальной синхронизации и одноканальном приеме ФТ сигнала со случайной фазой показал энергетический проигрыш последней системы в среднем на 5 дБ.Theoretical Average Bit Error Probability

(3) for one channel of FT signal reception is presented in the table (figure 3) (the phase has a uniform distribution law, integration within ϕ from 0 to π / 2. This integral was calculated numerically, the code program is written in Matlab. Bit probability analysis errors P _b with perfect synchronization and single-channel reception of a FT signal with a random phase showed an energy loss of the last system by an average of 5 dB.

To ensure discrete phase adjustment, it is necessary to increase the number of receive channels. Figures 4 ... 7 show graphs of the probability of a bit error P _b (ϕ) depending on the phase ϕ with two, three, four and six receive channels spaced at π / 2, π / 3, π / 4 and π / 6 ( respectively). With an increase in the number of receiving channels, the total probability of a bit error P _b (ϕ) decreases over the entire range of phase changes ϕ equal to plus, minus π and is indicated by a thick line.

для n канальной системы приема ФТ сигнала можно выполнять интегрирование в таких же пределах изменения фазы ϕ равном плюс, минус π/2, либо интегрированием для одного канала согласно (3) в пределах возможной девиации фазы ϕ равном плюс, минус π/4, π/6, π/8, π/12 (соответственно). Результаты расчетов общей теоретической усредненной вероятности битовой ошибки

для n канальной системы дискретной подстройки фазы, представлены в таблице (фигура 3).For numerical determination of the total theoretical averaged probability of bit error

for an n-channel FT signal reception system, integration can be performed within the same range of phase change ϕ equal to plus, minus π / 2, or integration for one channel according to (3) within the possible phase deviation ϕ is equal to plus, minus π / 4, π / 6, π / 8, π / 12 (respectively). Results of calculations of the total theoretical averaged probability of bit error

for n channel discrete phase adjustment systems are presented in the table (figure 3).

Analysis of the obtained values of the table (figure 3) suggests that with a two-channel discrete phase adjustment system, the energy loss will be on average 1 dB, for a three-channel discrete phase adjustment system, the energy loss will be 0.45 dB, for a four-channel discrete phase adjustment system the energy loss will be 0.25 dB, and for a six-channel discrete phase adjustment system, the energy loss will be about 0.1 dB.

A generalized graph of the theoretical probability of a bit error P _b (ϕ) depending on the ratio (E _b / N _o ) for a different number of reception channels for discrete phase adjustment is shown in the figure (figure 8).

Given the energy gain from increasing the reception channels and hardware costs, it is rational to adopt a three-channel system for receiving frequency-stabilized signals with binary phase shift keying with an unknown initial phase. The energy loss of the proposed device compared with the ideal synchronization scheme for receiving a phase-shifted signal will be about 0.45 dB (in power), which is acceptable.

The method is implemented in 3 stages:

1) processing of a frequency-stabilized signal with binary phase shift keying in three independent receive channels phase-separated by ϕ = π / 3;

2) the operation of the threshold device of each channel in direct and inverse mode: making a positive decision on the reception of KU when the required number of elements of the block KU coincides or the same number of errors are made that will correspond to the inverse reception of KU;

3) making the final decision on accepting KU in accordance with the positive decision on accepting KU at least one of the channels.

The figure 9 presents a diagram of a device for receiving frequency-stabilized signals with binary phase shift keying with an unknown initial phase, containing an analog-to-digital converter ADC 1, a digital matched filter CSF 2, a storage unit for code combinations BHKK 8, a logical element OR 11 and three identical processing channels a signal, each of which consists of a PM 3 signal multiplier, a G 4 reference generator, a low-pass filter, an LPF 5, an OGR 6 amplitude limiter, a SS 7 comparison circuit, an INT 9 integrator, and a threshold PU construction 10.

A device for receiving frequency-stabilized signals with binary phase shift keying with an unknown initial phase works as follows. The input analog signal at an intermediate frequency ƒ _{pce is} fed to the input of the analog-to-digital converter of the ADC 1, where the signal is digitized. The digital matched filter CSF 2 is matched with the spectrum of the input signal, duration T _e . The samples of the signal from the output of the digital matched filter CSF 2 are fed to the first input of the PM 3 signal multiplier of each of the three channels. The second input of the PM 3 signal multiplier receives a signal from the reference generator G 4. The signals of the reference generators G 4 in each channel differ only in the initial phase shift ϕ of π / 3. The results of multiplying the samples of the input signal with the signal of the reference generator G 4 are filtered in the low-pass filter of the low-pass filter 5, the result is limited (0 - with a negative component, 1 - with a positive component) in the amplitude limiter OGR 6. Next, the signal goes to the comparison circuit CC 7, where compares with the reference code combination coming from the storage unit code combinations BHKK 8, which is common to all channels. The result of the comparison of the control command is accumulated in the INT 9 integrator and the result is fed to the input of the threshold device PU 10. The operation of the threshold device PU 10 of each channel is organized in direct and inverse mode: a positive decision on receiving the KU when the required number of elements of the KU block matches or such is allowed the same number of errors, which will correspond to the inverse reception KU. All outputs of the processing channels are reduced to a single logical block OR 11, where the final decision is made to receive the KU in accordance with the positive decision to receive the KU in at least one of the channels.

Thus, a device for receiving frequency-stabilized signals with binary phase-shift keying with an unknown initial phase can significantly, almost double, increase the noise immunity of systems compared to switchgear operating with BT signals and reduce hardware costs by a factor of five compared to a phase-manipulated signal processing device with discrete phase adjustment in the executive device of the radio control line.

Literature

1. Teplyakov N.M., Kalashnikov I.D., Roshchin B.V. Radio lines of space information transmission systems. Ed. THEM. Teplyakova. Textbook for universities. - M .: “Owls. Radio ", 1975. - 400 p.

2. BSF3-04.10. Manual. DAKZH.421452.004 RE.

3. AKRSS. Manual. DAKZH.421452.005 RE.

4. Radio-electronic means of undermining charges RPZ-8. - M .: VIU, 2000 .-- 52 p.

5. A device for processing a phase-shifted signal with discrete phase adjustment in an executive device of a radio control line / A.V. Leushin, A.V. Kravtsov, V.I. Anisimov. - No. 176149; Priority from 09/18/2017 // Patent for utility model. - 2017 .-- 8 p.

6. Sergienko A.B. Digital Communication: Textbook. allowance. SPb .: Publishing house S32 SPbGETU "LETI", 2012.164 s.

Claims (2)

1. A method of receiving frequency-stabilized signals with binary phase shift keying with an unknown initial phase, based on parallel processing of a phase telegraphy (FT) signal in an n channel system having different phase shifts of the reference generator and making a positive decision about receiving a control command (CC) positive reception KU at least one of the channels characterized in that it uses a three-channel system for receiving frequency-stabilized signals with binary phase shift keying, where the signals of the reference g the non-radiators of each channel have a phase shift equal to π / 3 relative to each other and the operation of the threshold devices in each of the three channels is organized in direct and inverse mode: making a positive decision on the reception of the KU when the required number of elements of the KU block matches or such the same number of errors, which will correspond to the inverse reception KU. 2. A device for receiving frequency-stabilized signals with binary phase shift keying with an unknown initial phase, comprising an analog-to-digital converter (ADC) 1, the output of which is connected to the input of a digital matched filter (CSF) 2, characterized by the presence of three identical signal processing channels, each of which consists of a signal multiplier (PM) 3, the first input of which is connected to the output of a digital matched filter (CSF) 2, the second input of a signal multiplier (PM) 3 is connected to the output of a reference generator (G) 4, In each channel, the signals of the reference generator (G) 4 differ only in the initial phase shift equal to π / 3, the output of the signal multiplier (PM) 3 is connected to the input of the low-pass filter (LPF) 5, the output of which is connected to the amplitude limiter (OGR) 6, the output which is connected to the first input of the comparison circuit (CC) 7, the output of the code combination storage unit (BHCC) 8 is connected to all second inputs of the comparison circuit (CC) 7 of the three signal processing channels, the output of the comparison circuit (CC) 7 is connected to the integrator input (INT ) 9, the output of which is connected to the input stratum device (PU) 10, the output of the threshold device (PU) 10, each of the signal processing channels connected to the first, second and third input of the OR gate 11, respectively.

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