RU2753594C1 - Frequency synthesizers summing unit - Google Patents

Abstract

FIELD: frequency synthesizers summing unit.

SUBSTANCE: invention relates to a summing unit for frequency synthesizers.

EFFECT: improves the processing speed of constant numbers. The summing unit contains an n-bit adder, a multiplexer and a register, as well as an (n+1)-bit adder, the n least significant bits of the sum output of which are bitwise connected to the first information input of the multiplexer, the second information input of which is connected to the sum output of the n-bit adder, and the output of the multiplexer is connected to the information input of the register, the output of which is connected to the input of the first term of the n-bit adder and is the information n-bit output of the device, the clock input of the register is the clock input of the device, and the input of zeroing the register is the input to zeroing the device, a logical zero is fed to the transfer input of the n-bit adder, and the input of its second term is the information n-bit input of the device, while an additional n-bit adder is introduced, the input of the first term is combined with the information input of the device, and the input of the second term is the bitwise inverted binary code of the module is fed, over which the summation is carried out, a logical unit is fed to the transfer input of the additional adder, and its output of the sum is bitwise connected to the n least significant bits of the input of the first term of the (n+1)-bit adder, the least significant n bits of the input of the second term of the (n+1)-bit adder are bitwise connected to the register output , in this case, a logical zero is supplied to the transfer input of the (n+1)-bit adder, as well as to the high-order bit of the input of its second addend, a logical unit is fed to the high-order bit of the input of the first term of the (n+1)-bit adder, and its high-order bit is the sum output is connected to the multiplexer control input.

1 cl, 2 dwg

Description

The invention relates to computer technology and can be used in frequency synthesizers and frequency dividers with a fractional division factor.

Known accumulating adders [1], [2], [3], containing binary adders and registers.

The disadvantage of these devices is that they add modulo numbers equal to a natural power of two, whereas many applications require modulo summation of other numbers.

The closest in technical essence to the claimed invention is an accumulating adder modulo [4], the diagram of which is shown in FIG. 1, where it is indicated:

1 - n-bit adder;

2 - (n + 1) -bit adder;

3 - multiplexer;

4 - n-bit register;

5 - n-bit information input of the device;

6 - logical zero input;

7 - input of the bitwise inverted binary code of the module;

8 - logical unit input;

9 - clock input of the device;

10 - device zeroing input;

11 - n-bit information output of the device.

When describing the operation of the prototype device and the claimed device, the abbreviation generally accepted in technical (including patent) documentation will be used, in which a multi-bit input (output) of a block is described as an input (output) of a block without a multi-bit definition.

младших разрядов суммы сумматора 2 поразрядно соединены с первым информационным входом мультиплексора 3. Выход переноса сумматора 2 соединен с управляющим входом мультиплексора 3, выход которого соединен с информационным входом регистра 4. Тактовый вход регистра 4 является тактовым входом 9 устройства, а его вход обнуления является входом обнуления 10 устройства.The prototype device contains an adder 1, the input of the first term of which is connected to the output of register 4 and is the output 11 of the device, and the input of the second term is the information input 5 of the device. A logical zero is fed to the transfer input of the adder 1 from the input 6 of the device, and the output of the sum of the adder 1 is bitwise connected to the second information input of the multiplexer 3 and the n least significant bits of the first addend of the adder 2. The most significant bit of the first addend of the adder 2 is connected to the transfer output of the adder 1, and to the input of the second addend of the adder 2 from the input 7 of the device is fed to the bitwise inverted binary code of the module, over which the summation is carried out. A logical unit is supplied to the transfer input of the adder 2 from the input 8 of the device. Outputs

the least significant bits of the sum of the adder 2 are bitwise connected to the first information input of the multiplexer 3. The transfer output of the adder 2 is connected to the control input of the multiplexer 3, the output of which is connected to the information input of the register 4. The clock input of register 4 is the clock input 9 of the device, and its zeroing input is the input zeroing device 10.

This device sums up the input sequence {A (k); k = 1, 2,…} n-bit numbers modulo an arbitrary natural number P lying in the interval [2, 2 ⁿ - 1]. In this case, the numbers themselves take values from the interval [0, P - 1].

The disadvantage of the device is its low speed in comparison with the accumulating adder [3], containing only n-bit adder and register. This is because the propagation delay is increased by the amount of delay in the (n + 1) -bit adder and multiplexer.

The objective of the invention is to increase the speed in the case when a constant number A is supplied to the input of the device. This situation occurs in digital frequency synthesizers [2], as well as frequency dividers with a fractional division factor. The change in the number A in these devices is carried out only when the value of the frequency or division ratio is changed.

To solve the posed problem in an accumulating adder for frequency synthesizers containing an n-bit adder, a multiplexer and a register, as well as an (n + 1) -bit adder, the n least significant bits of the output of the sum of which are bitwise connected to the first information input of the multiplexer, the second information input of which is connected to the output of the sum of the n-bit adder, and the multiplexer output is connected to the information input of the register, the output of which is connected to the input of the first addend of the n-bit adder and is the information n-bit output of the device, the clock input of the register is the clock input of the device, and the register zeroing input is the input to zero the device, while a logical zero is fed to the transfer input of the n-bit adder, and the input of its second term is the information n-bit input of the device, according to the invention, an additional n-bit adder is introduced, the input of the first term is combined with the information input of the device , a a bitwise inverted binary code of the module is fed to the input of the second term, over which the summation is carried out, a logical unit is fed to the transfer input of the additional adder, and its output of the sum is bitwise connected to the n least significant bits of the input of the first term of the (n + 1) -bit adder, the least significant n bits the inputs of the second term of the (n + 1) -bit adder are bitwise connected to the register output, while a logical zero is applied to the transfer input of the (n + 1) -bit adder, as well as to the high-order bit of the input of its second addend, a logical zero is applied to the high-order bit of the input of the first term The (n + 1) -bit adder is fed with a logical unit, and the most significant bit of its sum output is connected to the multiplexer control input.

FIG. 2 shows a diagram of the claimed device, in which the following designations are introduced:

1 - n-bit adder;

2 - (n + 1) -bit adder;

3 - multiplexer;

4 - n-bit register;

5 - n-bit information input of the device;

6 - logical zero input;

7 - input of the bitwise inverted binary code of the module;

8 - logical unit input;

9 - clock input of the device;

10 - device zeroing input;

11 - n-bit information output of the device;

12 - additional n-bit adder.

At the input 5 sequentially, synchronously with the clock pulses supplied to the input 9, a sequence of numbers {A (k); k = 1, 2,…} to be accumulated. Then it is fed to the input of the second addend of the adder 1 and the input of the first addend of the adder 12. At the input of the second addend of the adder 12, the bitwise inverted binary code of the module is supplied, over which the summation is carried out. A logical unit is fed to the transfer input of the adder 12 from the input 8 of the device, and the output of the sum of the adder 12 is connected to the n least significant bits of the input of the first addend of the adder 2. The lower n bits of the input of the second addend of the adder 2 are connected to the output of the register 4, to the transfer input of the adder 2, and also, a logical zero is fed to the most significant bit of the input of its second term from the input 6 of the device. The input of the first addend of the adder 1 is connected to the output of the register 4 and the output 11 of the device, and a logical zero is fed to its transfer input from the input 6 of the device. The output of the sum of the adder 1 is connected to the second information input of the multiplexer 3, the first information input of which is connected to the n least significant bits of the output of the sum of the adder 2. The output of the multiplexer 3 is connected to the information input of the register 4, and its control input is connected to the output of the most significant bit of the sum of the adder 2. On the input of the most significant bit of the first term of the adder 2 is fed by a logical unit from the input 8 of the device. The clock input of the register 4 is connected to the clock input 9 of the device, and the zeroing input of the register 4 is connected to the zeroing input 10 of the device.

The device works as follows.

Before starting work, a pulse is sent to input 10 of the device, which zeroes the contents of register 4. Clock pulses are sent to input 9 of the device, which synchronize the operation of the device. With each clock pulse, input 5 receives the code of the next n-bit number A (k) satisfying the condition 0 ≤ A (k) <P. It arrives at the input (B ₁ ... B _n ) of adder 1 and the input (A ₁ ... A _n ) adder 12. At the input (B ₁ ... B _n ) adder 12 bit-inverted binary code of the module P is fed, and at the carry input - a logical unit. At the output of the sum (S ₁ ... S _n ) of the adder 12, a binary complementary code of the difference A (k) - P without a sign digit is formed. Since A (k) <P, the number A (k) - P is always negative, therefore its sign bit is equal to one. At the output of the sum (S ₁ ... S _n ) of the adder 1, the code of the number A (k) + S (k) is generated, where S (k) is the number written in register 4. At the output of the sum (S ₁ ... S _{n + 1} ) adder 2 forms a binary complementary code of the number A (k) + S (k) - P, and the bit S _{n + 1} determines the sign of the number. If A (k) + S (k) <P, then the difference A (k) + S (k) - P is negative and _{a logical unit is formed at the output of the most significant bit S n + 1 of the} sum of adder 2, under the influence of which on the output of multiplexer 3 the second input (Y ₁ ... Y _n ) is switched, and the code of the number A (k) + S (k) is sent to the information input of register 4, which is written into the register by the next clock pulse.

If A (k) + S (k) ≥ P, then the difference A (k) + S (k) - P is greater than or equal to zero, therefore, at the output of the most significant bit S _{n + 1 of the} sum of adder 2, a logical zero is formed, and at the output the multiplexer is switched to its first input (X ₁ ... X _n ).

The information input of register 4 receives the code of a non-negative number A (k) + S (k) - P, which is written into the register by the next clock pulse.

Thus, at the output of the register 4 and, accordingly, the output 11 of the device, the code of the next element of the output sequence {S (k); k = 1, 2, ...}

(1)

(1)

Let us show that the values of the elements of the sequence {S (k); k = 1, 2, ...} is less than P.

After the arrival of a zeroing pulse at the output of register 4, the zero number code S (1) = 0 is set.

If we assume that S (k) <P, then, taking into account that A (k) <P, the inequality A (k) + S (k) - P <P is true. Therefore, in accordance with formula (1), S ( k + 1) <P. According to the method of mathematical induction, all elements of the sequence {S (k); k = 1, 2, ...} is less than P.

According to the definition of the sum modulo P

This means that the claimed device implements the function of an accumulating adder modulo P, where P is an arbitrary natural number from the interval [2, 2 ⁿ - 1].

The speed of the device increases when the numbers A (k) are the same and equal to a certain number A. In this case, the output of the adder 12 is set to a constant number equal to A - P without a sign bit, so the delay of the signals in the adder 12 does not affect the speed. The increase in performance is carried out due to the simultaneous calculation of the numbers A + S (k) and A + S (k) - P, while in the prototype device first the number A + S (k) is calculated, and then the number A + S (k ) - P.

REALIZATION

To evaluate in practice the gain in speed, simulation was carried out in the Quartus II automatic design system using the EP2C8F256I8 programmable logic integrated circuit (FPGA) of the Altera Cyclon II family (analogue of the domestic FPGA 5578TC024).

The number P = 30,000 was chosen as the module over which the summation is carried out, which corresponds to n = 15.

The simulation result showed that the maximum possible clock frequency of the prototype device is 135 MHz, and the claimed device is 190 MHz. Thus, the performance gain is 1.4 times.

SOURCES OF INFORMATION

1. Reference book on integrated circuits / B.V. Tarabrin, S.V. Yakubovsky, N.A. Barkanov and others; Ed. B.V. Tarabrina. - 2nd ed., Rev. and add. - M .: Energy, 1981. - 816 p., Ill., Fig. 5-250, p. 741.

2. Puhalskiy G.I., Novoseltseva T.Ya. Design of discrete devices on integrated circuits: Handbook. - M .: Radio and communication, 1990. - 304 p .: ill., Fig. 4.80, p. 268.

3. Naumkina L.G. Digital circuitry. Lecture notes on the discipline "Circuitry" - M .: "Gornaya Kniga". Publishing house of the Moscow State Mining University, 2008, Fig. 6.9, p. 228.

4. Patent RU 2500017 C1. Accumulator modulo. Published on November 17, 2013. Bul. No. 33.

Claims (1)

Accumulating adder for frequency synthesizers containing n-bit adder, multiplexer and register, as well as (n + 1) -bit adder, n least significant bits of the sum output of which are bitwise connected to the first information input of the multiplexer, the second information input of which is connected to the sum output n -bit adder, and the multiplexer output is connected to the information input of the register, the output of which is connected to the input of the first term of the n-bit adder and is the information n-bit output of the device, the clock input of the register is the clock input of the device, and the register zeroing input is the device zeroing input, in this case, a logical zero is fed to the transfer input of the n-bit adder, and the input of its second term is the information n-bit input of the device, characterized in that an additional n-bit adder is introduced, the input of the first term of which is combined with the information input of the device, and the input the second term is fed bitwise inverted binary code of the module over which the summation is carried out, a logical unit is fed to the transfer input of the additional adder, and its output of the sum is bitwise connected to the n least significant bits of the input of the first term of the (n + 1) -bit adder, the least significant n bits of the input of the second term (n +1) -bit adder are bitwise connected to the register output, while a logical zero is fed to the transfer input of the (n + 1) -bit adder, as well as to the high-order bit of the input of its second addend, a logical zero is fed to the high-order bit of the input of the first addend (n + 1) -bit adder, a logical unit is supplied, and the most significant bit of its sum output is connected to the multiplexer control input.

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