RU2642366C1 - Adder accumulator - Google Patents

Abstract

FIELD: electricity.

SUBSTANCE: device contains two n-bit adders, (n+1)-bit half-adder, 2n-bit register.

EFFECT: reduced equipment and reduced energy consumption.

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Description

The invention relates to computer technology and can be used in digital computing devices, as well as in digital frequency synthesizers of broadband communication systems.

A known accumulating adder containing 2 adders and a register (Pukhalsky GI, Novoseltseva T.Ya. Designing discrete devices on integrated circuits: Reference book. -M.: Radio and communications, 1990, Fig. 4.80, p. 263).

The disadvantage of this device is the low speed.

The closest in technical essence and the achieved result to the invention is an accumulating adder (Patent RU 2544748 according to the application 2014111953/08, 03/27/2014. Publ. 20.03.2015. Bull. No. 8). The device contains three n-bit adders, a 2n-bit register and an (n + 1) -bit two-input multiplexer.

The disadvantage of this accumulating adder is the large amount of equipment.

The technical result of the invention is to reduce the amount of equipment and, as a consequence, reduce energy consumption by eliminating the (n + 1) -bit multiplexer, one n-bit adder and introducing one (n + 1) -bit half-adder.

To achieve a technical result, an accumulating adder containing the first and second n-bit adders and a 2n-bit register, wherein the first information inputs of the first n-bit adder are connected to the k / 2 least significant bits of the device information input, where k = 2n is the bit depth of the input numbers , the information outputs of the first n-bit adder are connected to the lower n information inputs of the 2n-bit register, the lower n information outputs of which are k / 2 lower bits of the output of the sum of the device and are connected to about the second information inputs of the first n-bit adder, the transfer input of which is the first input of the device transfer, the first information inputs of the second n-bit adder are connected to k / 2 high bits of the device information input, the clock input of the 2n-bit register is the device clock input, input resetting the 2n-bit register is the input of resetting the device, the highest n information outputs are k / 2 senior bits of the output of the sum of the device and are connected to the second information inputs the second n-bit adder, to the transfer input of which a logical zero signal is supplied from the second input of the device transfer, an (n + 1) -digit half-adder is introduced, the second information input of which is connected to the transfer output of the first n-bit adder, the lower n of the first information inputs connected to the information outputs of the second n-bit adder, the (n + 1) -th first information input is connected to the transfer output of the second n-bit adder, the lower n information outputs are connected to the senior n information inputs rows 2n-bit register, (n + 1) -th bit is the output of the transfer device.

The essence of the invention lies in the implementation of the following method of cumulative summation of the numbers A _i arriving sequentially in a parallel code with a capacity of k = 2n at the input of the accumulating adder. The lower k / 2 bits of the input number go to the first adder, while the higher k / 2 bits of the input number go to the second adder, which performs the summation taking into account the input transfer signal equal to logical zero. As a result, the summation result for the lower k / 2 digits and for the higher k / 2 digits is calculated simultaneously, i.e. eliminates the need to start the process of summing the highest k / 2 bits at the end of the summation of the lower k / 2 bits. The carry signal according to the results of summing the lower k / 2 bits is summed using an (n + 1) -bit half-adder, with the result of summing the highest k / 2 bits in the second adder. As a result, the final value of the upper bits of the sum is obtained, which, together with the lower bits, is recorded in a 2n-bit register. The second term for the first adder is the lower n bits of the number recorded in the register, and for the second adder, the highest n bits.

In FIG. 1 is a schematic of an accumulating adder.

The accumulating adder contains the first and second n-bit adders 1 and 2, (n + 1) -bit half-adder 3 and 2n-bit register 4, information input 5 of the device numbers A_i, divided by k / 2 junior (A_one…BUT_{k / 2}) bits and k / 2 senior (A_{k / 2 + 1}…BUT_k) bits, where k=2n-bit input numbers A_i, the first 6 and second 7 inputs of the transfer device, the clock input 8 of the device, input 9 zeroing device, output 10 of the sumS devices divided by k / 2 junior (S_one... S_{k / 2}) bits and k / 2 senior (S_{k / 2 + 1}... S_k) bits, output 11 of the transfer device. The first information inputs of the first n-bit adder 1 are connected to the k / 2 least significant bits of the device information input 5, the information outputs of the first n-bit adder 1 are connected to the lower n information inputs of the 2n-bit register 4, the lower n information outputs of which are k / 2 the least significant bits of the output 10 of the sum of the device and are connected to the second information inputs of the first n-bit adder 1, the transfer input of which is the first input 6 of the transfer device, the first information inputs of the second n the bit adder 2 is connected to k / 2 high bits of the information input 5 of the device, the clock input of the 2n-bit register is the clock input 8 of the device, the reset input of the 2n-bit register is the input 9 of the device zero, the highest n information outputs are k / 2 high bits of the output 10 sums of the device and are connected to the second information inputs of the second n-bit adder 2, to the transfer input of which from the second input 7 of the transfer of the device a logical zero signal is supplied. The second information input of the (n + 1) -bit half-adder 3 is connected to the transfer output of the first n-bit adder 1, the lower n of the first information inputs are connected to the information outputs of the second n-bit adder 2, the (n + 1) -th information input is connected to the transfer output of the second n-bit adder 2, the lower n information outputs are connected to the senior n information inputs of the 2n-bit register 4, the (n + 1) th bit is the transfer output 11 of the device.

The accumulating adder operates as follows.

Before the beginning of the accumulative summation procedure, a signal is received at the zeroing input 9 of the device, which resets the 2n-bit register 4. The summed k-bit numbers A _i are supplied sequentially in parallel code to the information input 5 of the device.

From the information input 5 of the device from the lower k / 2 digits (А ₁ ... А _{k / 2} ), the input number code is supplied to the first information inputs (А ₁ ... А _n ) of the first n-bit adder 1, and from the highest k / 2 digits ( And _{k / 2 + 1} ... А _k ) - the input number code is supplied to the first information inputs (A ₁ ... А _n ) of the second n-bit adder 2. The signal of the transfer of the second n-bit adder 2 is received from the second input 7 of the device transfer logical zero. The second information inputs (B ₁ ... B _n ) of the first n-bit adder 1 receive the code of the number from the lower k / 2 = n bits (Q ₁ ... Q _n ) of the 2n-bit register 4. The second information inputs (B ₁ ... B _n ) the second n-bit adder 2 receives the code of the number from the highest k / 2 = n bits (Q _{n + 1} ... Q _2n ) of the 2n-bit register 4. As a result, the summation result for the lower k / 2 bits and for the higher k / 2 bits, without taking into account the transfer signal, is calculated simultaneously. The transfer signal according to the results of summing the lower k / 2 bits from the transfer output of the first n-bit adder 1 is fed to the second information input of the (n + 1) -bit half-adder 3, the lower n first information inputs of which receive the result of summing the highest k / 2 bits with information outputs of the second n-bit adder 2 and the (n + 1) -th information input receives a signal from the transfer output of the second n-bit adder 2. As a result, the final value is formed at the outputs of the (n + 1) -digit half-adder 3 ummahs of higher k / 2 digits and a transfer signal. The clock pulses, next in synchronization with the input numbers, write the summation result in a 2n-bit register 4. The accumulative sum result (S ₁ ... S _k ) from the output of the 2n-bit register 4 goes to the output 10 of the sum of the device, and the signal 11 transfers the device transfer of P _o from the (n + 1) -th discharge of the (n + 1) -bit half-adder 3.

Consider the work of the accumulating adder on a specific example. Let the bit capacity of k input numbers be 4 bits. In the initial state, the 2n-bit register 4 is reset. Let the first input number A ₁ = 5 ₁₀ = 0101 ₂ . Then the lower digits A _ml = 01, and the senior digits A _st = 01. Younger portion of the input numbers A _ml = 01 is supplied to the first data inputs A ₁ ... A _n of the first n-bit adder 1, and the principal part of the input of A _{a =} 01 is supplied to the first data inputs A ₁ ... A _n of the second n-bit adder 2 . on the second information inputs B ₁ ... B _n of the first n-bit adder 1 and second data inputs IN ₁ ... _n The second n-bit adder 2 in the first cycle are fed with zeros information outputs 2n-bit information register 4. at the outputs of the first n-bit adder 1 the number 01 will appear, and on inform tional outputs the second n-bit adder 2 will be the number of outputs 01. In the information (n + 1) -bit half-adder 010. The number 3 appears in the result of the first cycle in the 2n-bit register 4 the number 0101 is written.

Let the second input number be the input number A ₂ = 7 ₁₀ = 0111 ₂ . Then, at the second clock, the information output of the first n-bit adder 1 will display the number 01 + 11 = 00, and a logical “1” signal will be generated at its transfer output. The information output of the second n-bit adder 2 will display the number 01 + 01 = 10, and a logical “0” signal will be generated at its transfer output. At the information output of the (n + 1) -bit half-adder 3, the number 1 + 010 = 011 will appear. As a result, on the second clock, the number 1100 will be written to the 2n-bit register 4. Logical “0” signal will be sent to the transfer output 11. As a result, the number 1100 ₂ = 12 ₁₀ will be written in the 2n-bit register 4, which is correct, since 5 + 7 = 12.

Evaluate the effectiveness of the proposed device in comparison with the prototype.

A single-bit half-adder contains 4 elementary logic elements, a single-bit full adder consists of two half-adders and an additional logical element, i.e. contains 9 elementary logic elements (Fig. 3.52, p. 274 and Fig. 3.53, p. 276, DA Bezuglov Digital devices and microprocessors / D.A. Bezuglov, I.V. Kalienko. - Ed. 2nd Rostov n / a: Phoenix, 2008 .-- 468 p.). One multiplexer contains 3 elementary logic elements per one bit and one logical element for the entire circuit (Fig. 3.8 b, p. 104, Pukhalsky GI, Novoseltseva T.Ya. Designing discrete devices on integrated circuits: Reference. - M. : Radio and communications. 1990 .-- 334 p.).

When constructing the proposed accumulating adder, one n-bit adder containing 9n elementary logic elements and one n + 1-bit multiplexer containing 3 (n + 1) + 1 = 3n + 4 elementary logic elements were excluded from the prototype device. At the same time, an n + 1-bit half-adder containing 4 (n + 1) elementary logic elements was introduced into the proposed device. In total, the number of elementary logic elements in the proposed device compared to the prototype device decreased by 9n + (3n + 4) -4 (n + 1) = 8n elementary logic elements.

Claims (1)

An accumulating adder containing the first and second n-bit adders and a 2n-bit register, the first information inputs of the first n-bit adder being connected to the k / 2 least significant bits of the device information input, where k = 2n is the bit depth of the input numbers, the information outputs of the first n -digit adder connected to the lower n information inputs of the 2n-bit register, the lower n information outputs of which are k / 2 lower bits of the output of the sum of the device and connected to the second information inputs of the first n-bit adder, the transfer input of which is the first input of the device transfer, the first information inputs of the second n-bit adder are connected to k / 2 high-order bits of the device information input, the clock input of the 2n-bit register is the clock input of the device, the reset input of the 2n-bit register is the zeroing input of the device, the highest n information outputs are k / 2 high bits of the output of the sum of the device and are connected to the second information inputs of the second n-bit adder d the transfer of which from the second input of the transfer of the device a logical zero signal is supplied, characterized in that a n-bit half-adder is inserted into it, the second information input of which is connected to the transfer output of the first n-bit adder, the lower n first information inputs are connected information outputs of the second n-bit adder, the (n + 1) -th first information input is connected to the transfer output of the second n-bit adder, the lower n information outputs are connected to the senior n information inputs 2n-bit register, the (n + 1) -th bit is the transfer output of the device.

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