RU2724597C1 - Multi-digit parallel adder modulo with serial transfer - Google Patents

Abstract

FIELD: computer equipment.SUBSTANCE: disclosed multi-digit parallel adder modulo with serial transfer realizes summation of input numbers A and B modulo M in two steps by performing summation operation in single-digit parallel adders modulo. At first step, expression value (A+B)-M is determined. If the obtained value is greater than or equal to zero, i.e. (A+B)-M≥0, desired value is obtained. If the obtained value is less than zero, i.e. (A+B)-M<0, then the desired value is obtained at the second step by repeated summation of the numbers A and B.EFFECT: providing a multi-digit parallel adder modulo with serial transfer.1 cl, 2 dwg, 1 tbl

Description

The invention relates to computer technology and can be used in digital computing devices, as well as in digital signal processing devices and in cryptographic applications.

A sequential multi-bit adder is known that contains n-bit shift registers of the operands X and Y, a result register S, a single-bit adder SM, and a two-stage D-trigger for storing the transfer. (Babich N.P., Zhukov I.A. Fundamentals of Digital Circuitry: Textbook. - M.: Dodeka-XXI Publishing House, Kiev: MK-Press, 2007. - Figure 4.45, p. 176).

The disadvantage of this adder is the limited functionality, namely the impossibility of summing modulo.

Also known is a multi-bit parallel adder with sequential transfer containing n single-bit parallel adders with corresponding connections (see Pukhalsky G.I., Novoseltseva T.Ya. Designing discrete devices on integrated circuits: Reference book. - M.: Radio and communication, 1990. Figure 3.45, p. 133).

The disadvantage of this adder is the limited functionality, namely the impossibility of summing modulo.

The closest in technical essence to the claimed invention is a multi-bit parallel adder modulo with sequential transfer, containing n + 1 parallel adders modulo with corresponding connections, performing the summation of the numbers A and B modulo M (multi-bit parallel adder modulo with sequential carry // Russian patent No. 2439661. 08/10/2011. Bull. No. 22. / Kopytov V.V., Petrenko V.I., Sidorchuk A.V.).

The disadvantage of this adder is its limited functionality, namely, incorrect calculation of the sum modulo in all cases except (A + B)> M, with the value M = F, since with (A + B) ≤M the adder will switch to the calculation mode ( A + BM), which does not correspond to the required result.

The technical result of the invention is to expand the functionality of the device due to the correct summation over the entire range of input numbers A and B.

To achieve a technical result, a multi-bit parallel adder modulo with sequential transfer, consisting of n single-bit parallel adders modulo, where n is the bit capacity of the device, the first inputs of the device are the inputs of the first summing number and connected to the first information inputs of single-bit parallel adders modulo, the second the inputs of the device are the inputs of the second number of summation and are connected to the second information inputs of single-bit parallel adders modulo, the third inputs of the device are inputs of the module and connected to the third information inputs of single-bit parallel adders modulo, the input of the transfer of the number of the device is connected to the input of the transfer of the number of the first one-bit parallel adder modulo, information outputs of single-bit parallel adders modulo connected to the information outputs of the device, control inputs of single-bit parallel adders modulo connected together and connected to the transfer output of the device module, the transfer output of the number of the i-th single-bit parallel adder modulo is connected to the transfer input of the number of the (i + 1) -th single-bit parallel adder modulo, the transfer output of the module of the i-one single-bit parallel adder modulo is connected to the transfer input of the module of the (i + 1) th single-bit parallel adder modulo, where i = 1, ... n-1, and the single-bit parallel adder modulo contains two single-bit parallel adders, the element "NOT" and the element "2I", and the first input of the first one-bit parallel adder is modulo connected to the first information input of the single-bit parallel adder modulo, the second input is connected to the second information input of the one-bit parallel adder modulo, the transfer input is connected to connected to the transfer input of the number of the first one-bit parallel adder modulo, the transfer output is connected to the transfer output of the number of one-bit parallel sums modulo ora, the sum output is connected to the second input of the second one-bit parallel adder, the transfer input of which is connected to the transfer input of the single-bit parallel adder modulo, the transfer output is connected to the transfer output of the single-bit parallel adder modulo, the input of the element “NOT” is connected to the third information input of a single-bit parallel adder modulo, and the first input of the element “2I” is connected to the control input of a single-bit parallel adder modulo, a delay element, RS-trigger, element “NOT”, element “2OR” and element “2I” are introduced, and the output the module transfer module of the n-th single-bit parallel adder is connected modulo to the second input of the “2OR” logic element, and the number transfer output is connected to the first input of the “2OR” element, the output of which is connected to the input of the “NOT” element, the output of which is connected to the first input of the element "2I", the output of which is connected to the R-input of the RS-trigger, the S-input of the RS-trigger is an input setting the device to its initial state, the output of the RS-flip-flop is connected to the control inputs of all n single-bit parallel adders modulo, to the transfer input module of the first single-bit parallel adder modulo and to the input of the delay element, the output of which is connected to the second input of the element “2I”, and in a single-bit parallel adder modulo the output of the element "NOT" is connected to the second input of the element "2I", the output of which is connected to the first input of the second single-bit parallel adder, the output of the sum is connected to the information output of the single-bit parallel adder modulo.

The invention consists in implementing the following method of summing the numbers A and B modulo M.

и

где n-разрядность устройства, соответственно первый и второй операнды суммирования, пусть

модуль, по которому проводится суммирование,

- сумма операндов A и B по модулю M.Let be

and

where the n-bit capacity of the device, respectively, the first and second operands of the summation, let

the module used to summarize

is the sum of the operands A and B modulo M.

As a result of the operation, you need to get the amount

Способ суммирования двух чисел A и B по модулю M заключается в том, что вначале находят решение разности С(с₀, …, c_n) - M(m₀, …, m_n-1). Если полученное значение больше или равно нулю, то оно и является искомой суммой S(s₀, …, s_n-1). Если же полученное значение меньше нуля, то осуществляется повторное суммирование чисел A и B и искомой суммой S является сумма этих чисел S(s₀, …, s_n-1)=A(a₀, …, a_n-1)+B(b₀, …, b_n-1). В качестве индикатора превышения нуля используется старший разряд переноса сумматора.When adding two numbers represented in the form of binary codes A (a ₀ , ..., a _n-1 ) and B (b ₀ , ..., b _n-1 ), the sum C (c ₀ , ..., c _n ) is formed, equal to

The method of summing two numbers A and B modulo M is that first they find a solution to the difference C (c ₀ , ..., c _n ) - M (m ₀ , ..., m _n-1 ). If the obtained value is greater than or equal to zero, then it is the desired sum S (s ₀ , ..., s _n-1 ). If the obtained value is less than zero, then the summation of numbers A and B is carried out and the desired sum S is the sum of these numbers S (s ₀ , ..., s _n-1 ) = A (a ₀ , ..., a _n-1 ) + B (b ₀ , ..., b _n-1 ). As an indicator of excess zero, the highest digit of the adder transfer is used.

In FIG. 1 is a diagram of a multi-bit parallel adder modulo with sequential transfer.

A multi-bit parallel adder modulo with sequential transfer contains n single-bit parallel adders 1 modulo, where the n-bit capacity of the device, delay element 2, element "2I" 3, element "NOT" 4, RS-trigger 5, element "2OR" 6, inputs 7 and 8 of the second and first numbers of summation, respectively, input 9 of the device module, information outputs 10 of the device, input 11 transfer the number of devices, input 12 of the installation in the initial state. The device operand code A is supplied to the device input 8, the operand code B is sent to the device input 7. The module code M is sent to the device input 9. Logic zero is supplied to the device input 11, the PM _i module transfer input of the first one-bit parallel adder is connected to the control inputs W device and the input of the delay element 2, the input signal 12 is supplied to the input 12 of the installation in the initial state. The output port P _{o of the} transfer of the number of the j-th single-bit parallel adder 1 modulo is connected to the input P _{i of the} transfer of the number of the (j + 1) -th single-bit parallel adder 1 modulo, the output PM _{o of the} transfer module of the j-th single-bit parallel adder 1 modulo is connected with the input PM _i transfer module (j + 1) -th single-bit parallel adder 1 modulo, where j = 1, ..., n-1. The output PM _{o of the} transfer of the module of the n-th single-bit parallel adder 1 modulo is connected to the second input of the 2OR element 6, the output of P _{o of the} transfer of the number of the n-th single-bit parallel adder 1 modulo is connected to the first input of the 2OR element 6. Output of the element "2OR" 6 is connected to the input of the element "NOT" 4, the output of which is connected to the first input of the element "2I" 3, the output of which is connected to the R-input of the RS-trigger 5, the S-input of the RS-trigger 5 is the input of setting the device to the initial state 12, the output of the RS-flip-flop 5 is connected to the control inputs W of all n single-bit parallel adders 1 modulo, with the input PM _i of the module transfer of the first single-bit parallel adder modulo and the input of the delay element 2, the output of which is connected to the second input of the 2I element 3. The outputs S of single-bit parallel adders 1 modulo connected to the information outputs 10 of the device.

In FIG. 2. presents a diagram of a single-bit parallel adder 1 modulo.

The single-bit parallel adder 1 modulo contains a control input W, an input of a device module M, inputs A and B of the first and second summing numbers, respectively, inputs P _i and PM _i , which are transfer inputs of the number and module of the device, respectively, outputs P _o and PM _o , which are the outputs of the transfer of the number and module of the device, respectively, the output S, which is the information output of the device, two single-bit parallel adders 13, the element "NOT" 14 and the element "2I" 15, and the first input of the first single-bit parallel adder 13 is connected to the first information input of the single-bit parallel adder 1 modulo, the second input is connected to the second information input of a single-bit parallel adder 1 modulo, the transfer input is connected to connected to the transfer input of the number of the first one-bit parallel adder 1 modulo, the transfer output is connected to the transfer output of the number of one-bit parallel adder 1 modulo , the sum output is connected to watts the second input of the second single-bit parallel adder 13 modulo, the transfer input is connected to the transfer input module single-bit parallel adder 1 modulo, the transfer output is connected to the transfer output of the module single-bit parallel adder 1 modulo, the sum output is connected to the information output of the single-bit parallel adder 1 modulo the input of the element “NOT” 14 is connected to the third information input of the single-bit parallel adder 1 modulo, and the first input of the element “2I” 15 is connected to the control input of the single-bit parallel adder 1 modulo, and the output of the element “NOT” 14 is connected to the second input of the element “ 2I ”15, the output of which is connected to the first input of the second single-bit parallel adder 13, the output of which is connected to the information output 10 of the single-bit parallel adder 1 modulo.

Multi-bit parallel adder 1 modulo with sequential transfer works as follows. Before starting work, the device is set to its initial state by applying a control signal to input 12. Further, the codes of the summation operands A (a ₀ , ..., a _n-1 ) and B (b ₀ , ..., b _n-1 ) and the module code M (m ₀ , ..., m _n-1 ), respectively. Consistently for each discharge, each single-bit parallel adder modulo 1 in accordance with Table 1 generates a signal of the sum S and signals of the transfer of the number P _o and the transfer of the module PM _o . If a unit is formed at the output of the “2OR” element 6, then the value of the module M is subtracted from the sum (A + B). In the case when the signal at the output of the “2OR” 6 element is equal to zero, both operands A (a ₀ , ..., a _{n -1} ) and B (b ₀ , ..., b _n-1 ) are summed in the usual way. In this case, sequentially bitwise at the information outputs of device 10, the result of summing two numbers A (a ₀ , ..., a _n-1 ) and B (b ₀ , ..., b _n-1 ) modulo M (m ₀ , ..., m _{n -1} ).

(см. фиг. 1).Consider the operation of the device as an example, when

(see Fig. 1).

In the initial state, the RS-trigger 5 is in the zero state, logical zeros act on all inputs of the device.

Let A = 6 ₁₀ = 0110 ₂ , B = 4 ₁₀ = 0100 ₂ , M = 9 ₁₀ = 1001 ₂ . The device for this example will contain four single-bit parallel adders modulo.

Codes of numbers A = 0110 ₂ , B = 0100 ₂ , M = 1001 ₂ are fed to the inputs A, B and M of the four adders. A logic 0 signal is input to the input number P _{i of} transferring the number of the device, and the input 12 to the initial state, which is connected to the S-input of the RS-trigger 5, is supplied with a unit that transfers the RS-trigger 5 to a single state. The signal from the output of the RS-trigger 5 is supplied to the control inputs W of the device. At the output of the first one-bit parallel adder 1 modulo we obtain the following values of P _o = 0, PM _o = 0. At the output of the second one-bit parallel adder 1 modulo we obtain the values of P _o = 0, PM _o = 1. At the output of the third one-bit parallel adder 1 modulo we obtain the values of P _o = 1, PM _o = 1. At the output of the fourth one-bit parallel adder 1 modulo we obtain the values of P _o = 0, PM _o = 1, which are fed to the logic element "2OR" 6 and then to the input of the element "NOT" 4, where the received value is inverted. After that, the signal goes to the first input of the element "2I" 3, prohibiting the passage of the signal through its first input. The state of the RS-trigger 5 does not change. The summation of the numbers A and B modulo M is considered complete. As a result, at the information output of the first one-bit parallel adder in accordance with table 1, we get S = 1 (57 lines), at the information output of the second one-bit parallel adder in accordance with table 1, we get S = 0 (35 lines), at the information output of the third one-bit parallel the adder in accordance with table 1 we get S = 0 (52 line), at the information output of the fourth single-bit parallel adder in accordance with table 1 we get S = 0 (61 line). At the output of the device, the number 0001 ₂ = 1 ₁₀ appears.

Check: 6 + 4 = 10, 10≡1 mod 9.

(см. фиг. 1).Consider the operation of the device as an example, when

(see Fig. 1).

In the initial state, the RS-trigger 5 is in the zero state, logical zeros act on all inputs of the device.

Let A = 3 ₁₀ = 0011 ₂ , B = 4 ₁₀ = 0100 ₂ , M = 9 ₁₀ = 1001 ₂ . We use the truth table of the full single-bit adder 1 modulo (Table 1). The device for this example will contain four single-bit parallel adders modulo.

The codes of numbers A = 0011 ₂ , B = 0100 ₂ , M = 1001 ₂ are fed to the inputs of four adders. A logic 0 signal is input to the input number P _{i of} transferring the number of the device, and the input 12 to the initial state, which is connected to the S-input of the RS-trigger 5, is supplied with a unit that transfers the RS-trigger 5 to a single state. The signal from the output of the RS-trigger 5 is supplied to the control inputs W of the device. At the output of the first one-bit parallel adder 1 modulo we obtain the following values of P _o = 0, PM _o = 1. At the output of the second one-bit parallel adder 1 modulo we obtain the values of P _o = 0, PM _o = 1. At the output of the third one-bit parallel adder 1 modulo we obtain the values of P _o = 0, PM _o = 1. At the output of the fourth one-bit parallel adder 1 modulo we obtain the values of P _o = 0, PM _o = 0, which are fed to the logic element "2OR" 6 at the output of which remains a logical zero, and at the output of the logical element "NOT" 4 remains a logical unit, which acts on the first input of the “2I” element 3, to its second input through the delay element 2 a signal delayed by the device from the output of the RS-trigger 5 is received by the device. The signal of the logical unit from the output of the “2I” 3 signal is fed to the R-input RS trigger 5, translating it into zero state. After which the signal from the output of the RS-flip-flop 5 ceases to be supplied to the control inputs W of the device and the second round of summation begins. As a result, we get S = 1 at the information output of the first one-bit parallel adder, we get S = 1 at the information output of the second one-bit parallel adder, we get S = 1 at the information output of the third one-bit parallel adder, we get S = 0 at the information output of the fourth one-bit parallel adder. At the output of the device, the number 0111 ₂ = 7 ₁₀ appears.

Check: 3 + 4 = 7, 7≡7 mod 9.

Single-bit parallel adder 1 modulo works as follows (see figure 2). At the input A, the bit of the first operand of the summation A is fed, at the input B, the second operand of the summation B. The input P _i serves as the input of the transfer of the number P _i , the input PM _i serves as the transfer input of the module PM _i . The input of M is the discharge of module M. The input W is the control input W. The output P _o is the transfer output of the number P _o , the output PM _o is the transfer output of the PM _o module. Output S is the information output S of the device. The device operates in accordance with the truth table (Table 1), based on which it follows that in the case when a logical zero is input W, then the sum will be equal to S = A + B, if a logical one arrives, we get the sum S = (A + B) -M.

The technical result of the work is to expand the functionality of the modulo adder due to the correct summation over the entire range of summed numbers A and B. The proposed multi-bit parallel adder modulo with sequential transfer allows you to achieve this result in two cycles by performing the summation operation in single-bit parallel modulo adders.

Table 1. The truth table of the full single-bit adder modulo.

A B P _{i Po} M PM _i W PM _O S 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 1 1 1 0 0 0 0 0 0 1 1 1 1 0 1 0 0 0 0 0 0 0 1 0 0 0 0 1 1 0 1 1 1 0 0 0 0 0 1 0 1 1 0 0 0 0 0 1 1 1 1 0 0 0 1 1 0 0 0 0 1 0 0 0 0 0 1 0 0 1 0 0 0 1 1 0 0 0 1 0 0 0 1 1 1 0 1 1 0 0 0 0 0 0 1 0 1 0 0 0 1 0 1 1 1 1 0 0 0 0 1 0 1 1 1 0 0 0 0 1 1 1 1 1 0 0 0 1 0 0 0 0 0 1 0 1 0 0 1 0 0 0 1 0 1 1 1 0 0 0 0 1 0 1 1 1 1 0 1 0 1 0 1 0 0 0 1 0 0 1 0 1 1 0 1 1 1 0 1 0 1 0 1 0 1 1 0 1 0 1 0 1 1 1 1 0 1 0 1 1 0 0 0 0 1 1 0 0 0 0 1 0 0 1 1 0 1 1 1 0 0 0 1 1 0 1 1 1 1 0 1 1 1 0 0 0 0 0 1 0 1 1 0 1 1 0 1 1 1 1 1 0 0 0 1 0 1 1 1 1 0 0 0 1 1 1 1 1 1 0 1 1 0 0 0 0 0 0 1 0 1 0 1 0 0 0 0 1 1 0 1 0 0 0 0 0 1 1 0 1 1 0 1 0 0 1 0 1 0 0 1 0 0 0 1 1 0 0 1 1 1 0 0 1 0 1 1 0 1 1 0 0 1 0 1 1 1 1 1 0 0 1 1 0 0 0 0 0 1 0 1 0 0 0 1 0 0 1 0 1 0 1 1 0 0 0 1 0 1 0 1 1 1 0 1 1 0 1 0 0 0 0 1 0 1 0 1 0 1 0 1 1 1 1 0 1 0 0 1 0 1 1 1 0 1 0 0 1 1 1 1 1 0 1 0 1 0 0 0 0 0 1 1 1 0 0 1 0 0 0 1 1 1 1 1 0 0 0 0 1 1 1 1 1 1 0 1 0 1 1 1 0 0 0 1 0 0 1 1 1 1 0 1 1 1 0 1 1 1 0 1 0 1 1 0 1 1 1 0 1 1 1 1 0 1 1 1 1 0 0 0 0 1 1 1 0 1 0 1 0 0 1 1 1 1 0 1 0 0 0 1 1 1 1 0 1 1 0 1 1 1 1 0 1 0 0 1 0 1 1 1 1 0 0 1 1 1 1 1 1 0 1 1 0 1 1 1 1 1 0 1 1 1 1 1 1 1 1 1 0

Claims (1)

A multi-bit parallel adder modulo with sequential transfer, consisting of n single-bit parallel adders modulo, where n is the bit depth of the device, the first inputs of the device are inputs of the first summing number and are connected to the first information inputs of single-bit parallel adders modulo, the second inputs of the device are inputs of the second summing numbers and are connected to the second information inputs of single-bit parallel adders modulo, the third inputs of the device are inputs of the module and connected to the third information inputs of single-bit parallel adders modulo, the input of transferring the number of the device is connected to the input of the transfer of the number of the first one-bit parallel adder modulo single-bit parallel adders modulo connected to the information outputs of the device, the control inputs of single-bit parallel adders modulo connected together and connected to the transfer output m after the device is pulled, the output of the transfer of the number of the i-th single-bit parallel adder modulo is connected to the input of the transfer of the number of the (i + 1) -th single-bit parallel adder modulo, the transfer output of the module of the i-th single-bit parallel adder modulo is connected to the transfer input of the module (i +1) th single-bit parallel adder modulo, where i = 1, ... n-1, and the single-bit parallel adder modulo contains two single-bit parallel adders, the element "NOT" and the element "2I", and the first input of the first single-bit parallel adder connected to the first information input of a single-bit parallel adder modulo, the second input is connected to the second information input of a single-bit parallel adder modulo, the transfer input is connected to the transfer input of the number of the first one-bit parallel adder modulo, the transfer output is connected to the output of the transfer of the number of one-bit parallel adder modulo , the sum output is connected to the second input m of the second one-bit parallel adder, the transfer input of which is connected to the module transfer input of the single-bit parallel adder modulo, the transfer output is connected to the transfer output of the module of one-bit parallel adder modulo, the sum output is connected to the information output of the single-bit parallel adder modulo, the input of the element is NOT connected to the third information input of the single-bit parallel adder modulo, and the first input of the 2I element is connected to the control input of the single-bit parallel adder modulo, characterized in that a delay element, an RS-trigger, the element "NOT", the element "2OR ”And the“ 2I ”element, the module transfer output of the nth single-bit parallel adder modulo connected to the second input of the“ 2OR ”logic element, and the number transfer output connected to the first input of the“ 2OR ”element, the output of which is connected to the input of the“ NOT ", The output of which is connected to the first input of the 2I element, the output is cat It is connected to the R-input of the trigger, the S-input of the RS-trigger is the input of setting the device to its initial state, the output of the RS-trigger is connected to the control inputs of all n single-bit parallel adders modulo, with the transfer input module of the first single-bit parallel adder modulo and with the input of the delay element, the output of which is connected to the second input of the “2I” element, and in a single-bit parallel adder modulo the output of the element “NOT” is connected to the second input of the element “2I”, the output of which is connected to the first input of the second single-bit parallel adder, the output of the sum is connected with the information output of a single-bit parallel adder modulo.

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