RU2790638C1 - Multibit modular adder - Google Patents

Abstract

FIELD: computer engineering.

SUBSTANCE: digital computing devices, as well as digital signal processing devices, cryptographic applications and control systems. First, the value of the expression is determined as (A+B) - P. If the resulting value is greater than or equal to zero, i.e. (A+B) – P ≥ 0, then the desired value is obtained. If the resulting value is less than zero, i.e. (A+B) – P < 0, then the desired value is obtained by repeated summation of the A and B numbers. The device contains n full single-bit adders, (n+1)-bit adder, n-bit key, where n is the device capacity, delay element, RS-trigger, NE element and 2I element.

EFFECT: increasing the speed of the device, performing the summation operation in single-bit parallel adders.

1 cl, 1 dwg

Description

SUBSTANCE: invention relates to computer engineering and can be used in digital computing devices, as well as in digital signal processing devices, in cryptographic applications and in control systems.

A serial multi-bit adder is known, which contains n -bit shift registers of operands X and Y , a result register, a single-bit adder and a two-stage D -trigger for carrying carry [1].

The disadvantage of this adder is limited functionality, namely the impossibility of modulo summation.

Also known is a multi-bit parallel adder with serial transfer, containing n single-bit parallel adders with appropriate connections [2].

The disadvantage of this adder is limited functionality, namely the impossibility of modulo summation.

The closest in technical essence to the claimed invention is a multi-bit parallel modulo adder with serial transfer, containing ( n + 1) single-bit parallel modulo adders with appropriate connections, summing the numbers A and B modulo an arbitrary M [3].

The disadvantage of this device is the low performance caused by serial bitwise summation, as well as the presence in each single-bit modulo adder of two series-connected parallel single-bit adders.

The technical result of the invention is to improve performance.

To achieve a technical result in a multi-bit modulo adder containing n full single-digit adders, where n is the device capacity, RS is a flip-flop, the "2I" element, the "NOT" element, the delay element, the inputs of the first summation number, the inputs of the second summation number, the input module of the device, information outputs of the device, the input of setting the device to the initial state, and the inputs of the first summation number are connected to the first information inputs of n full single-bit adders, the inputs of the second summation number are connected to the second information inputs of n full single-digit adders, the input of setting the device to the initial state is connected with the input of setting to a single state of the RS flip-flop, the input of setting to the zero state of which is connected to the output of the "2I" element, the first information input of which is connected to the output of the "NOT" element, and the second information input is connected to the output of the delay element, an n -bit keys ( n + 1)-bit adder , the first information inputs of which are connected to the information outputs of n full one-bit adders, respectively, (2 ... ( n + 1))-th bits of the second information inputs of the ( n + 1)-bit adder are connected to the transfer outputs of the (1 ... n )-th one-bit adders , the first bit of the second information inputs is connected to the output of the RS flip-flop and the control input of the n -bit key, the transfer output is connected to the input of the "NOT" element, and the information outputs are the information outputs of the device, the information inputs of the n -bit key are connected to the input of the device module, information outputs are connected to the transfer inputs of n full single-digit adders, and the input of setting the device to the initial state is connected to the input of the delay element.

The essence of the invention lies in the implementation of the following method of summing the numbers A and B modulo P .

и

, где n-разрядность устройства, соответственно первый и второй операнды суммирования, причем

и

. Пусть

модуль, по которому проводится суммирование,

- сумма операндов A и B по модулю P.Let

And

, where n is the capacity of the device, respectively, the first and second summation operands, and

And

. Let

the modulus over which the summation is carried out,

is the sum of operands A and B modulo P .

As a result of the operation, you need to get the amount

. Способ суммирования двух чисел A и Bпо модулю P заключается в том, что вначале находят решение разности С(с _n , …, с ₀)–P(p _{n -1}, …, p ₀). Если полученное значение больше или равно нулю, то оно и является искомой суммой S(s _{n -1},…, s ₀). Если же полученное значение меньше нуля, то осуществляется повторное суммирование чисел A и B и искомой суммой S является сумма этих чисел S(s _{n -1},…, s ₀)=A(a _{n -1}, …, a ₀) + B(b _{n -1}, …, b ₀). В качестве индикатора превышения нуля используется выход переноса (n+1)-разрядного параллельного сумматора.When adding two numbers represented as binary codes A ( a _{n -1} , …, a ₀ ) and B ( b _{n -1} , …, b ₀ ), the sum С ( с _n , …, с ₀ ) is formed, equal to

. The method of summing two numbers A and B modulo P consists in first finding the solution of the difference С ( с _n , …, с ₀ ) – P ( p _{n -1} , …, p ₀ ). If the obtained value is greater than or equal to zero, then it is the desired sum S ( s _{n -1} ,…, s ₀ ). If the obtained value is less than zero, then the repeated summation of the numbers A and B is carried out and the desired sum S is the sum of these numbers S ( s _{n -1} ,…, s ₀ )= A ( a _{n -1} , …, a ₀ ) + B ( b _{n -1} , …, b ₀ ). The carry output of the ( n +1)-bit parallel adder is used as an indicator of exceeding zero.

In FIG. 1 shows a diagram of a multi-bit modulo adder. The modulo multi-bit adder contains an n -bit key 1, n full single-bit adders 2.1-2 .n , an RS flip-flop 3, ( n +1)-bit parallel adder 4, where n is the device capacity, element "2I" 5, element "NOT" 6, delay element 7, input 8 of the device module, inputs 9 and 10 of the second and first summation numbers, respectively, information outputs 11 of the device, input 12 of setting the device to its initial state.

At the input 10 and 9 of the device serves the codes of numbers A and B coming further on the first information input A and the second information input B of the corresponding j -th full single-digit adder 2.1-2 .n , where j =1, ..., n . At the same time, the inverse code of the module P is fed to the input 8 of the device, which is fed to the information inputs ( X ₁ ... X _n ) of the n -bit key 1. To the input 12 of the installation in the initial state, which is connected to the input of the delay element 7 and S the input of the installation in a single state of the RS -flip-flop 3, a signal is given to start the calculations.

The multi-bit modulo adder works as follows (see Fig. 1).

Before starting work, the device is set to its initial state by applying a control signal to input 12. The output RS -flip-flop 3 is set to a single signal. The information inputs 10, 9 and 8 of the device are supplied in binary form with the codes of the summation operands A ( a _{n -1} , ..., a ₀ ) and B ( b _{n -1} , ..., b ₀ ) and the inverse code of the module P ( p _{n - 1} , …, p ₀ ) respectively. For each digit at the outputs of full single-digit adders 2.1-2. n the sum signal S and the carry signals of the number P _about are formed. Since the RS flip-flop 3 is in a single state, the key 1 passes to the transfer inputs P _i full single-bit adders 2.1-2. n is the inverse code of the module P ( p _{n -1} , …, p ₀ ). As a result, the information outputs of full single-digit adders 2.1-2. n, bitwise sum signals are formed, and bitwise carry signals are formed at the transfer outputs. Signals from information outputs of full single-digit adders 2.1-2. n arrive at the first information inputs ( n +1)-bit adder 4. Signals from the transfer outputs of full single-bit adders 2.1-2. n arrive at the (2…( n +1))-th bit of the second information inputs of the ( n +1)-bit adder 4. The first bit B ₁ of the second information inputs of the ( n +1)-bit adder 4 from the output of the RS flip-flop 3 receives a logical unit signal. As a result, the outputs of ( n +1)-bit adder 4 form the value S =

, то на выходе переноса P _o(n+1)-разрядного сумматора 4 образуется сигнал логической единицы, который, проходя через элемент «НЕ» 6 закроет для прохождения на вход RRS-триггера 3 сигнала с выхода элемента задержки 7. Время задержки элемента задержки 7 выбирается не менее чем минимальное время прохождения входных сигналов через элементы 1, 2, 4. При этом на информационных выходах (n+1)-разрядного сумматора 4 образуется искомая сумма чисел A и B по модулю P.If

, then at the output of the transfer P _o ( n +1)-bit adder 4, a logical unit signal is formed, which, passing through the "NOT" element 6, will close the signal from the output of the delay element 7 to the input of the RRS -trigger 3. The delay time of the delay element 7 is selected not less than the minimum time of passage of the input signals through the elements 1, 2, 4. At the same time, at the information outputs of the ( n +1)-bit adder 4, the desired sum of the numbers A and B modulo P is formed.

, то на выходе переноса P _o(n+1)-разрядного сумматора 4 остаётся нулевой сигнал, который, инвертируясь через элемент «НЕ» 6, открывает элемент «2И» 5 для прохождения сигнала с выхода элемента задержки 7. Далее сигнал поступает на R вход RS-триггера 3, переводя его в нулевое состояние. При этом закрывается n-разрядный ключ 1 и на вход B ₁ вторых информационных входов (n+1)-разрядного сумматора 4 поступает нулевой сигнал. В результате на его информационных выходах формируется сумма чисел A и B, которая и является искомой суммой

If

, then at the output of the transfer P _o ( n +1)-bit adder 4 remains a zero signal, which, inverting through the element "NOT" 6, opens the element "2I" 5 for the signal to pass from the output of the delay element 7. Then the signal goes to R input RS -flip-flop 3, turning it into a zero state. This closes the n -bit key 1 and the input B ₁ of the second information inputs ( n +1)-bit adder 4 receives a zero signal. As a result, the sum of numbers A and B is formed at its information outputs, which is the desired sum

After receiving the result of summing the numbers A and B modulo P to the output from the device, the summation process can be resumed with other initial data.

(см. фиг. 1).Consider the operation of the device using an example when

(see Fig. 1).

In the initial state RS -flip-flop 3 is in the zero state, all inputs of the device are affected by logical zeros.

=0110₂. Устройство для данного примера будет содержать четыре полных одноразрядных сумматора 2.1-2.4.Let A =6 ₁₀ =0110 ₂ , B =4 ₁₀ =0100 ₂ , P =9 ₁₀ =1001 ₂ ,

=0110 ₂ . The device for this example will contain four full single bit adders 2.1-2.4.

=0110₂. На вход 12 установки в начальное состояние, который соединён с S входом RS-триггера 3, подаётся единица, которая переводит RS-триггер 3 в единичное состояние. Сигнал с выхода RS-триггера 3 поступает на управляющий вход Wn-разрядного ключа 1 и первый разряд B ₁ вторых информационных входов (n+1)-разрядного сумматора 4. На выходах первого полного одноразрядного сумматора 2.1 получаем значения S=0, P _о=0. На выходах второго полного одноразрядного сумматора 2.2 получаем значения S=0, P _о=1. На выходах третьего полного одноразрядного сумматора 2.3 получаем значения S=1, P _о=1. На выходах четвёртого полного одноразрядного сумматора 2.4 получаем значения S=0, P _о=0. Сигналы суммы S и сигналы переноса числа P _о поступают на первые информационные входы (A ₁ …A _n ) и вторые информационные входы (B ₂ …B _{n + 1})(n+1)-разрядного сумматора 4. Таким образом, на входах (n+1)-разрядного сумматора 4 образуются числа: С=00100₂ и D=01101₂. После суммирования на информационных выходах (n+1)-разрядного сумматора 4 (S ₁ …S _n ), а значит и на выходах устройства, формируется число E=0001₂=1₁₀, а на выходе переноса P _o =1. При этом элемент «2И» 5 оказывается закрытым для прохождения сигнала с выхода элемента задержки 7.The inputs A , B and P _i of four full single-digit adders 2.1-2.4 are supplied with codes of numbers A =6 ₁₀ =0110 ₂ , B =4 ₁₀ =0100 ₂ ,

=0110 ₂ . At the input 12 of the installation in the initial state, which is connected to the S input of the RS -flip-flop 3, a unit is supplied, which translates the RS -flip-flop 3 into a single state. The output signal RS -flip-flop 3 is supplied to the control input W n -bit key 1 and the first bit B ₁ of the second information inputs ( n +1)-bit adder 4 . At the outputs of the first full single-digit adder 2.1, we obtain the values S =0, P _o =0. At the outputs of the second full single-digit adder 2.2 we obtain the values of S =0, P _about =1. The outputs of the third full single-bit adder 2.3 obtain the values of S =1, P _about =1. At the outputs of the fourth full single-bit adder 2.4 we obtain the values S =0, P _o =0. The sum signals S and the transfer signals of the number P _about arrive at the first information inputs ( A ₁ ...A _n ) and the second information inputs ( B ₂ ...B _{n + 1} )( n +1)-bit adder 4 . Thus, at the inputs of ( n +1)-bit adder 4 numbers are formed: C =00100 ₂ and D =01101 ₂ . After summation at the information outputs of the ( n +1)-bit adder 4 ( S ₁ ...S _n ) , and hence at the outputs of the device, the number E =0001 ₂ =1 ₁₀ is formed, and at the transfer output P _o = 1. In this case element "2I" 5 is closed for the signal from the output of the delay element 7.

By direct verification we set: 6+4=10, 10≡1 mod 9.

(см. фиг. 1).Consider the operation of the device using an example when

(see Fig. 1).

In the initial state RS -flip-flop 3 is in the zero state, all inputs of the device are affected by logical zeros.

= 0110₂. Устройство для данного примера будет содержать четыре полных одноразрядных сумматора 2.1-2.4.Let A =3 ₁₀ =0011 ₂ , B =4 ₁₀ =0100 ₂ , P =9 ₁₀ =1001 ₂ ,

= 0110 ₂ . The device for this example will contain four full single bit adders 2.1-2.4.

= 0110₂. На вход 12 установки в начальное состояние, который соединён с S-входом RS-триггера 3, подаётся единица, которая переводит RS-триггер 3 в единичное состояние. Сигнал с выхода RS-триггера 3 поступает на управляющий вход Wn-разрядного ключа 1 и первый разряд B ₁ вторых информационных входов (n+1)-разрядного сумматора 4. На выходах первого полного одноразрядного сумматора 2.1 получаем значения S=1, P _o=0. На выходах второго полного одноразрядного сумматора 2.2 получаем значения S=0, P _o=1. На выходах третьего полного одноразрядного сумматора 2.3 получаем значения S=0, P _o=1. На выходах четвёртого полного одноразрядного сумматора 2.4 получаем значения S=0, P _o=0. Сигналы суммы S и сигналы переноса числа P _o поступают на первые информационные входы (A ₁ …A _n )(n+1)-разрядного сумматора 4 и вторые информационные входы (B ₂ …B _{n + 1}). Таким образом, на входах сумматора образуются числа: С=00001₂ и D=01101₂. После суммирования на информационных выходах (n+1)-разрядного сумматора 4 (S ₁ …S _n ), а значит и на выходах устройства, формируется число E=0111₂=7₁₀, а на выходе переноса S _{n + 1} =0. Поскольку значение на выходе переноса P _o оказалось равно нулю, то на выходе элемента «НЕ» 6 окажется сигнал логической единицы, который откроет элемент «2И» 5 и сигнал с выхода элемента задержки 7 переведёт RS-триггер 3 в нулевое состояние. На управляющий вход Wn-разрядного ключа 1 поступит логический ноль, ключ закроется. Инверсный модуль в суммировании при этом не будет участвовать. Тогда, на выходе первого полного одноразрядного сумматора 2.1 получим значения S=1, P _o=0. На выходе второго полного одноразрядного сумматора 2.2 получим значения S=1, P _o=0. На выходе третьего полного одноразрядного сумматора 2.3 получим значения S=1, P _o=0. На выходе четвёртого полного одноразрядного сумматора 2.4 получим значения S=0, P _o=0.The inputs A , B and P _i of four single-bit adders 2.1-2.4 are supplied with codes of numbers A =3 ₁₀ =0011 ₂ , B =4 ₁₀ =0100 ₂ ,

= 0110 ₂ . At the input 12 of the installation in the initial state, which is connected to the S -input of the RS -flip-flop 3, a unit is supplied, which translates the RS -flip-flop 3 into a single state. The output signal RS -flip-flop 3 is supplied to the control input W n -bit key 1 and the first bit B ₁ of the second information inputs ( n +1)-bit adder 4 . The outputs of the first full single-bit adder 2.1 obtain the values of S =1, P _o =0. At the outputs of the second full single-bit adder 2.2 we obtain the values S =0, P _o =1. The outputs of the third full single-digit adder 2.3 obtain the values S =0, P _o =1. At the outputs of the fourth full single-bit adder 2.4 we obtain the values S =0, P _o =0. The sum signals S and carry signals P _o arrive at the first information inputs ( A ₁ ...A _n )( n +1)-bit adder 4 and the second information inputs ( B ₂ ...B _{n + 1} ) . Thus, numbers are formed at the inputs of the adder: С =00001 ₂ and D =01101 ₂ . After summation at the information outputs of the ( n +1)-bit adder 4 ( S ₁ ... S _n ) , and hence at the outputs of the device, the number E = 0111 ₂ = 7 ₁₀ is formed, and at the transfer output S _{n + 1} = 0. Since the value at the transfer output P _o turned out to be zero, then the output of the “NOT” element 6 will be a logical unit signal, which will open the “2I” element 5 and the signal from the output of the delay element 7 will transfer the RS flip-flop 3 to the zero state. The control input W n -bit key 1 will receive a logical zero, the key will close. In this case, the inverse module will not participate in the summation. Then, at the output of the first full single-bit adder 2.1 we obtain the values S =1, P _o =0. At the output of the second full single-digit adder 2.2 we obtain the values S =1, P _o =0. At the output of the third full single-digit adder 2.3 we obtain the values S =1, P _o =0. At the output of the fourth full single-bit adder 2.4 we obtain the values S =0, P _o =0.

Thus, at the inputs of ( n +1)-bit adder 4 numbers are formed: C =00111 ₂ and D =00000 ₂ . After summing at the information outputs of the ( n +1)-bit adder ( S ₁ ... S _n ) , and hence at the outputs of the device, the number E = 0111 ₂ = 7 ₁₀ is formed, and at the transfer output P _o = 0.

By direct verification we set: 3+4=7, 7≡7 mod 9.

Let us evaluate the technical result achieved when using the proposed device in comparison with the prototype device.

Let us estimate the performance T _pr of the prototype device as:

T _pr \u003d 4 nt _refSM1 , where t _refSM1 is the delay time of a full single-bit parallel adder, n is the capacity of the device. Since each one-bit modulo adder contains two series-connected one-bit parallel adders and the total summation time is performed in two cycles, the expression for T _pr includes a factor of 4. The delay time in the logical circuits for generating control signals will not be taken into account, since it will be significantly less than the main summation time and the same as in the proposed device.

The performance T _of the proposed device will be equal to:

T _from \u003d t _set +2 t _setSM1 +2 t _{setSM n} , where t _set is the delay time of the key 1, which can be neglected, t _setSM1 is the delay time of a full single-bit parallel adder 2, t _{setSM n} is the delay time ( n+ 1)- bit parallel adder 4.

If ( n +1)-bit parallel adder 4 is made according to the scheme with serial transfer, then t _{zadSM n} = nt _zadSM1 . If the ( n + 1)-bit parallel adder 4 is made as a prefix adder, then t _{setSM n} = (log n ) t _setSM1 .

Then the gain B in the speed of the proposed device compared to the prototype device when performing the adder 4 in the form of an adder with sequential transfer will be

B = T _pr / T _out = 4 nt _refSM1 /(2 t _refSM1 + 2 nt _refSM1 )=2 n /( n +1).

The gain B in the speed of the proposed device compared to the prototype device when performing the adder 4 in the form of a prefix adder will be

B = T _pr / T _out = 4 nt _refSM1 /(2 t _refSM1 + 2log nt _refSM1 )=2 n /(log n +1).

Information sources

1. Babich N.P., Zhukov I.A. Fundamentals of digital circuitry: Textbook. - M .: Publishing house "Dodeka-XXI", Kyiv: "MK-Press", 2007. - Figure 4.45 p. 176.

2. Pukhalsky G.I., Novoseltseva T.Ya. Designing Discrete Devices on Integrated Circuits: A Handbook. - M .: Radio and communication, 1990. Figure 3.45, p.133.

3. Petrenko V.I., Stepanyan N.E., Nelidin Yu.R. Multi-bit parallel modulo adder with serial transfer // Patent of Russia No. 2724597. Publ. 06/25/2020. Bull. No. 18.

Claims (1)

A multi-bit modulo adder containingn full one-bit adders, wheren - bit depth of the device,RS-trigger, "2I" element, "NOT" element, delay element, inputs of the first summation number, inputs of the second summation number, input of the device module, information outputs of the device, input of setting the device to the initial state, moreover, the inputs of the first summation number are connected to the first information entrancesn full single-digit adders, the inputs of the second summation number are connected to the second information inputsn full single-digit adders, the input of setting the device to the initial state is connected to the input of setting to a single stateRS-trigger, the input of setting to the zero state of which is connected to the output of the "2I" element, the first information input of which is connected to the output of the "NOT" element, and the second information input is connected to the output of the delay element, characterized in that it containsn-bit key And (n+1)-bit adder, the first information inputs of which are connected to information outputsn full single-digit adders, respectively, (2…(n+1))-th digits of the second information inputs (n+1)-bit adder are connected to the transfer outputs (1 ...n)-th single-bit adders, the first bit of the second information inputs is connected to the outputRS-trigger and control inputn-bit key, the transfer output is connected to the input of the "NOT" element, and the information outputs are the information outputs of the device, the information inputsn-bit key connected to the input of the device module, information outputs are connected to the transfer inputsn full single-digit adders, and the input of setting the device to the initial state is connected to the input of the delay element.

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