RU2805939C1 - Device for conveyor summation of numbers according to arbitrary module - Google Patents

Abstract

FIELD: computer technology.

SUBSTANCE: invention can be used in conveyor-type digital computing devices for constructing homogeneous computing environments, as well as in digital signal processing devices and cryptographic applications. The device contains a group of full single-bit adders, a first homogeneous computing environment of bit depth n, where n is the bit depth of the numbers being processed, a second homogeneous computing environment of bit depth (n+1), a multiplexer of bit depth n, the first, second and third information inputs, a clock input and information outputs with relevant connections.

EFFECT: implementation of the summation of numbers using arbitrary modulus.

1 cl, 5 dwg, 8 tbl

Description

Region technology, To which applies invention

The invention relates to computer technology and can be used in conveyor-type digital computing devices for constructing homogeneous computing environments, as well as in digital signal processing devices and cryptographic applications.

Level technology

From the existing level of technology, a technical solution is known for a homogeneous computing structure for performing operations on a given module, which contains N ² full adders, N /2( N -1) ² AND elements, ( N -2)( N -1) OR elements, N /2( N -1) ² control inputs [1], designed to perform arithmetic operations on a given module. A technical problem that cannot be solved using this technical solution is the low performance of arithmetic operations on an arbitrary module, since the main arithmetic operation during device operation is preceded by an additional switching mode, which determines the structure of the device depending on the selected module.

The closest to the claimed technical solution in terms of technical essence and achieved technical result is a device for pipeline arithmetic calculations according to a given module, selected as a prototype, containing a homogeneous computing environment, three substitution tables, information inputs and information outputs, a clock input that allows summation of numbers by arbitrary simple modules [2, Fig. 5]. A technical problem that cannot be solved when using this technical solution for pipeline information processing is the limited functionality of the device, since the device allows you to perform operations of summing numbers only modulo prime numbers. In addition, the use of lookup tables requires changing the contents of the lookup tables every time a module is changed, which does not allow quickly changing a module when organizing pipeline calculations.

The technical result provided by the given set of features is the expansion of the functionality of the device during pipeline processing of information.

Disclosure essence inventions

The specified technical result in the implementation of the invention is achieved by the fact that in a device for conveyor summation of numbers by an arbitrary modulus, containing a first homogeneous computing environment of bit depth n , where n is the bit depth of the numbers being processed, the first, second and third information inputs, information outputs and a clock input, which connected to the synchronization input of the first homogeneous computing environment, a second homogeneous computing environment of capacity ( n +1), a group of full single-bit adders and a multiplexer of capacity n are introduced, and the first information inputs of the device are connected to the first information inputs of the first homogeneous computing environment and to the first information inputs of the group full single-bit adders, the second information inputs of the device are connected to the second information inputs of the first homogeneous computing environment and to the second information inputs of the group of full single-bit adders, the third information inputs of the device are connected to the third information inputs of the group of full single-bit adders, the first information outputs of which are connected to the lowest n bits the first information inputs of the second homogeneous computing environment, the second information outputs are connected to the second information inputs of the second homogeneous computing environment with a shift by one digit towards the higher one, to the ( n +1)th digit of the first information inputs and to the first digit of the second information inputs of the second computing environment, a logical one signal is supplied, the synchronization input of the second homogeneous computing environment is connected to the clock input of the device, the low n bits of the information outputs are connected to the second information inputs of the multiplexer, and the output of the transfer bit is connected to the control input of the multiplexer, the first information inputs of which are connected to the information outputs of the first homogeneous computing environment, and the outputs are connected to the information outputs of the device.

The essence of the invention lies in the implementation of the following method for summing numbers modulo arbitrary. Let S be the sum of two numbers A and B modulo P

S ( A + B ) mod P , (1)

where A and B are positive integers, called the first and second terms, respectively, and

0≤ A , B < P , (2)

P is a positive integer called modulus;

S is a positive integer that is the sum of numbers A and B , modulo P , with 0≤ S < P.

All numbers are represented in positional binary number system.

A = $${\displaystyle \sum _{i=0}^{n-1}{a}_i{2}^i}$$ , (3)

B = $${\displaystyle \sum _{i=0}^{n-1}{b}_i{2}^i}$$ , (4)

P = $${\displaystyle \sum _{i=0}^{n-1}{p}_i{2}^i}$$ , (5)

S = $${\displaystyle \sum _{i=0}^{n-1}{s}_i{2}^i}$$ , (6)

where a _i , - coefficients taking the value 0 or 1 depending on the value of the number A ;

b _i , - coefficients taking the value 0 or 1 depending on the value of the number B ;

p _i , - coefficients taking the value 0 or 1 depending on the value of the module P ;

s _i , - coefficients taking the value 0 or 1 depending on the value of the sum S ;

n is the number of digits in the representation of numbers.

The task is to find the sum S modulo P using known A and B.

Due to the fulfillment of constraint (2), the sum of numbers A and B will always be in the range of values from 0 to 2 P -2. The value range from 0 to 2 P -2 can be divided into a first range from 0 to P -1 and a second range from P to 2 P -2. If the sum of numbers A and B falls into the first range, then it will be the result of the sum of numbers A and B modulo P. If the sum of numbers A and B falls into the second range, then to reduce it modulo P it is enough to subtract modulo P from it. The subtraction operation can be performed by adding the minuend with the subtrahend, represented in two's complement. In this case, an indicator of whether the sum of numbers A and B falls into the first or second range will be the absence or presence of a signal at the transfer output of the adder, which implements the subtraction operation. This signal controls the multiplexer, which selects the desired result.

A homogeneous computing environment can act as an adder in the pipeline summation mode [2, Fig. 3] with the cell structure presented in [2, Fig. 1].

Using one homogeneous computing environment, performing the operation of summing the streams of numbers A _j and B _j , j =1,2,3,..., and using a second homogeneous computing environment the operation ( A _j + B _j - P _j ), using the results of the calculation second homogeneous computing environment, choose the correct value for the sum S _j

Sj _{_} ( A _j + B _j ) mod P _j . (7)

Brief description drawings

The essence of the invention is illustrated by drawings.

In fig. Figure 1 shows a diagram of a device for conveyor summation of numbers modulo arbitrary. A device for conveyor summation of numbers by an arbitrary modulo contains a group of full single-bit adders 1, a first homogeneous computing environment of 2.1 bits n , where n is the bit depth of the numbers being processed, a second homogeneous computing environment of 2.2 bits ( n +1), a multiplexer of 3 bits n , the first 4, the second 5 and third 6 information inputs of the device, clock input 7 and information outputs 8 of the device. The first information inputs 4 of the device are connected to the first information inputs of the first homogeneous computing environment 2.1 and to the first information inputs of the group of full single-bit adders 1. The second information inputs 5 of the device are connected to the second information inputs of the first homogeneous computing environment 2.1 and to the second information inputs of the group of full single-bit adders 1. The third information inputs 6 of the device are connected to the third information inputs of the group of full single-bit adders 1, the first information outputs of which are connected to the low-order n bits of the first information inputs of the second homogeneous computing environment 2.2, the second information outputs are connected to the second information inputs of the second homogeneous computing environment 2.2 with shift by one digit towards the higher one. The clock input of the device is connected to the synchronization inputs of the first 2.1 and second 2.2 homogeneous computing environment. The low-order n bits of the information outputs of the second homogeneous computing environment 2.2 are connected to the second information inputs of the multiplexer 3, and the output of the transfer bit is connected to the control input of the multiplexer 3, the first information inputs of which are connected to the information outputs of the first homogeneous computing environment 2.1, and the outputs are connected to information outputs 8 devices. A logical one signal is supplied to the ( n +1)th bit of the first information inputs and to the first bit of the second information inputs of the second computing environment 2.2. A stream of number codes A _j , j =1,2,3,... is supplied to the first information inputs 4 of the device, a stream of number codes B _j is supplied to the second information inputs 5 of the device, a stream of inverse module codes P _j is supplied to the third information inputs 6 of the device. From the information outputs 8 of the device, the codes of the sum S _j of the numbers A _j and B _j , modulo P _j, are read.

Implementation inventions

A device for conveyor summing of numbers modulo arbitrary operates as follows (see Fig. 1).

In the initial state, all cells of the first 2.1 and second 2.2 of the homogeneous computing environment are reset to zero.

The clock input of device 7 receives clock pulses j =1,2,3,…,. At the first information inputs 4 of the device and the second information inputs 5 of the device, with each clock pulse, numbers A _j and B _j are supplied, respectively, for which it is necessary to calculate the sum S _j modulo P _j . The inverse code of the module P _j is supplied to the third information inputs 6 of the device. The sum S _j modulo P _j of the numbers A _j and B _j is taken from the information outputs 8 of the device.

The length of the pipeline and the latent period of the pipeline depend on the structure of homogeneous computing environments 2.1 and 2.2.

For each pair of numbers A _j and B _j , the first homogeneous computing environment 2.1 calculates the sum ( A _j + B _j ). For each triple of numbers A _j , B _j , and P _j, the second homogeneous computing environment 2.2, together with a group of full one-bit adders 1, calculates the value ( A _j + B _j - P _j ). The sum ( A _j + B _j ) and the value ( A _j + B _j - P _j ) appear synchronously at each clock cycle at the first and second information inputs of multiplexer 3. If the sum ( A _j + B _j )≥ P _j , then at the output of the transfer bit of the second homogeneous computing environment 2.2 a transfer signal will appear, which, arriving at the control input of the multiplexer 3, will connect its second information inputs with its information outputs, as a result, the information outputs of the device will have the value ( A _j + B _j - P _j ). Otherwise, its first information inputs will be connected to the information outputs of multiplexer 1 and the value ( A _j + B _j ) will appear at the information outputs of the device.

Let's consider the implementation of the device for the case when the bit depth of the processed numbers n is 4.

In fig. Figure 2 shows the structure of a group of full single-bit adders 1, consisting of four full single-bit adders 1.1÷1.4. Each full one-bit adder 1.1÷1.4 has two information inputs A and B , a _carry input Pi , a sum output S and a carry output P _o . The first information inputs A of full single-digit adders 1.1÷1.4 receive codes of numbers A _j from the first information inputs 4 of the device, the codes of numbers B j arrive from the second information inputs of the _device 5 from the second information inputs 5 of the device, the codes of numbers B _j are supplied to the transfer inputs Pi from the third information inputs 6 devices inverse codes of modules P _j . Each full one-bit adder 1.1÷1.4 generates at its outputs the sum value and the carry value depending on the values of the input signals that arrive at the first and second information outputs, respectively, of the group of full one-bit adders 1, designated as X _j and Y _j , respectively. In this case, in accordance with the rules for adding numbers, the digits X _j and Y _j will be calculated as

x _{i , j} =a _{i , j} $$\oplus$$ b _{i , j} $$\oplus$$ p _{i , j} , (8)

y _{i , j} =a _{i , j} b _{i , j} $$\vee$$ b _{i , j} p _{i , j} $$\vee$$ a _{i , j} p _{i , j} . (9)

where i = 0, 1, 2, 3 - the number of the digit in the binary representation of numbers;

j =1, 2, 3, …, - number of the device’s operating cycle;

x _{i , j} -i-th rankjon the thX _j ,

y _{i , j} -i-th rankjon the thY _j ;

a _{i , j} -i-th rankjon the thA _j ;

b _{i , j} -i-th rankjon the thB _j ;

p _{i , j} -i-th rankjon the thP _j ;

symbol $$\oplus$$ means summation modulo two;

symbol $$\vee$$ means logical disjunction.

Then the calculation of the value ( A _j + B _j - P _j ), consisting of three operands, can be reduced to the calculation of the value (2 ^{n +1} + X _j +2 Y _j +1), consisting of two operands and two constants, with increasing by one unit the bit capacity of the computer.

The cell shown in FIG. 1 can be used as a cell (CELL) for a homogeneous computing environment. 3 [2, fig. 1] and containing the first 9.1 and second 9.2 triggers, the EXCLUSIVE OR element 10, the AND element 11, two information inputs a and b , a synchronization input and two information outputs Q ₁ and Q ₂ . A cell of a homogeneous structure implements the following system of logical functions:

Q ₁ = a $$\oplus$$ b , (10)

Q ₂ = a⋅b . (eleven)

An example of the implementation of the first homogeneous computing environment 2.1 based on a cell of a homogeneous structure for bit capacity n = 4 in accordance with [2, Fig. 3] is shown in Fig. 4. The first homogeneous computing environment 2.1 for bit depth n = 4 contains 4 rows and 6 columns of cells of a homogeneous structure CELL n , m with the corresponding connections. Clock lines are connected to each cell and in FIG. 4 are not shown. Information inputs a and b of the cells of the first column are inputs for the digits of the summed numbers A _j and B _j . Information outputs Q ₁ of the cells of the sixth column are information outputs of the sum S _j for the case when S _j < P _j .

An example of the implementation of a second homogeneous computing environment 2.2 based on a cell of a homogeneous structure in accordance with [2, Fig. 3] is shown in Fig. 5. The second homogeneous computing environment 2.2 for the bit depth of input numbers n = 4 has an input bit width equal to five and contains 6 rows and 6 columns of cells of a homogeneous structure CELL n , m with appropriate connections, which also allows the formation of a carry signal. Clock lines are connected to each cell and in FIG. 5 are not shown. Information inputs a and b of the cells of the first column are inputs for the digits of the summed numbers X _j and Y _j . The second homogeneous computing environment 2.2 performs the operation (2 ⁵ + X _j +2 Y _j +1). The lower 4 bits of the first information inputs of the homogeneous computing environment 2.2 from the first information outputs of the group of full single-bit adders 1 receive the values X _j calculated in accordance with (8). The value of logical 1 is supplied to the fifth digit. The values of Y _j , calculated in accordance with (9), from the second information outputs of the group of full single-bit adders 1 are supplied to the second information inputs of the homogeneous computing environment 2.2 with a shift of one digit towards the highest ones, and to the most the least significant digit sends a logical 1 signal. The information outputs Q ₁ of the cells of the sixth column are the information outputs of the sum S _j of the homogeneous computing environment 2.2 for the case when S _j ≥P _j . The first four bits of information outputs of the homogeneous computing environment 2.2 are used as bits of the sum S _j , and the information output of the sixth bit is used as a transfer bit. The carry signal from the transfer output of the homogeneous computing environment 2.2 controls the operation of the multiplexer 3. If the carry signal is zero, this means that ( A _j + B _j )< P _j . In this case, the multiplexer 3 switches from the first information inputs to its outputs and then to the information outputs 8 of the device the value of the sum ( A _j + B _j ) from the information outputs of the first homogeneous computing environment 2.1. If the transfer signal is equal to one, this means that ( A _j + B _j )≥ P _j . In this case, the multiplexer 3 switches from the second information inputs to its outputs and then to the information outputs 8 of the device the value ( A _j + B _j ) - P _j from the information outputs of the second homogeneous computing environment 2.2. Thus, the correct value S _j will always be generated at the information outputs 8 of the device in accordance with (7).

Let's consider examples of the device's operation on specific values of the summed numbers and modulus. As a first example, consider the case when the sum of the input numbers does not exceed the modulus value. As input data, for the bit depth n =4 we choose the numbers A =3 ₁₀ (0011 ₂ ), B =7 ₁₀ (0111 ₂ ) and the module P =12 ₁₀ (1100 ₂ , inverse code 0011 ₂ ). The states of the device elements when calculating the sum for the first example are presented in table. 1-4.

Table 1 - State table of the first homogeneous computing environment 2.1 Inputs 1 2 3 4 5 6 Exits 1 a ₀ 1 0 0 0 0 0 s ₀ 0 b ₀ 1 0 0 0 0 0 2 a ₁ 1 1 0 0 0 0 s ₁ 1 b ₁ 1 0 1 1 1 1 3 a ₂ 0 1 0 0 0 0 s ₂ 0 b ₂ 1 1 0 0 0 0 4 a ₃ 0 0 1 0 0 0 s ₃ 1 b ₃ 0 0 0 1 1 1

In the first column of table 1, the numbers 1÷4 indicate the row numbers, and in line 1, the numbers 1÷6 indicate the column numbers of the first homogeneous computing environment 2.1. The intersection of the corresponding row and column indicates the signal at the corresponding input of the corresponding cell. The last column shows the values of the signals at the outputs of the sum of the cells of the sixth column. Signal values are given for one data set for six clock states.

Table 2 - State table of group of full single-bit adders 1 Inputs Exits A B P _i S _P0 1.1 1 1 1 1 1 1.2 1 1 1 1 1 1.3 0 1 0 1 0 1.4 0 0 0 0 0

In the first column of Table 2, designations 1.1÷1.4 indicate the numbers of adders in group of full single-bit adders 1. The signal values are given for one set of data for the first cycle.

Table 3 - State table of the second homogeneous computing environment 2.2 Inputs 1 2 3 4 5 6 Exits 1 x ₀ 1 0 0 0 0 0 s ₀ 0 1 1 0 0 0 0 0 2 x ₁ 1 1 0 0 0 0 s ₁ 1 y ₀ 1 0 1 1 1 1 3 x ₂ 1 1 0 0 0 0 s ₂ 1 y ₁ 1 0 1 1 1 1 4 x ₃ 0 1 0 0 0 0 s ₃ 1 y ₂ 0 0 1 1 1 1 5 1 1 0 0 0 0 0 - 1 y ₃ 0 1 1 1 1 1 6 - 0 0 0 0 0 0 s ₅ 0 - 0 0 0 0 0 0

The structure of Table 3 is similar to the structure of Table 1.

Table 4 - Multiplexer 3 status table Inputs Exits A B S 1st category 0 0 0 2nd category 1 1 1 3rd category 0 1 0 4th category 1 1 1

Table 4 shows the values of the signals at the information inputs and information outputs of multiplexer 3 at the sixth cycle. In accordance with Table 3, the control input of the multiplexer receives the signal s ₅ =0. As a result, the number 1010 ₂ =10 ₁₀ is received at the information outputs 8 of the device in the sixth cycle. By direct check we set 3+7 10 mod 12.

As a second example, consider the case when the sum of the input numbers exceeds the modulus value. As input data, for the bit depth n = 4, we choose the numbers A = 8 (1000) ₂ , B = 9 (1001) ₂ and the module P = 12 ₁₀ (1100 ₂ , inverse code 0011 ₂ ). The states of the device elements when calculating the sum for the second example are presented in table. 5-9.

Table 5 - State table of the first homogeneous computing environment 2.1 Inputs 1 2 3 4 5 6 Exits 1 a ₀ 0 0 0 0 0 0 s ₀ 1 b ₀ 1 1 1 1 1 1 2 a ₁ 0 0 0 0 0 0 s ₁ 0 b ₁ 0 0 0 0 0 0 3 a ₂ 0 0 0 0 0 0 s ₂ 0 b ₂ 0 0 0 0 0 0 4 a ₃ 1 0 0 0 0 0 s ₃ 0 b ₃ 1 0 0 0 0 0

In the first column of table 5, the numbers 1÷4 indicate the row numbers, and in line 1, the numbers 1÷6 indicate the column numbers of the first homogeneous computing environment 2.1. The intersection of the corresponding row and column indicates the signal at the corresponding input of the corresponding cell. The last column shows the values of the signals at the outputs of the sum of the cells of the sixth column. Signal values are given for one data set for six clock states.

Table 6 - State table of group of full single-bit adders 1 Inputs Exits A B P _i S _P0 1.1 0 1 1 0 1 1.2 0 0 1 1 0 1.3 0 0 0 0 0 1.4 1 1 0 0 1

In the first column of Table 6, designations 1.1÷1.4 indicate the numbers of adders in group of full single-bit adders 1. The signal values are given for one set of data for the first cycle.

Table 7 - State table of the second homogeneous computing environment 2.2 Inputs 1 2 3 4 5 6 Exits 1 x ₀ 0 0 0 0 0 0 s ₀ 1 1 1 1 1 1 1 1 2 x ₁ 1 0 0 0 0 0 s ₁ 0 y ₀ 1 0 0 0 0 0 3 x ₂ 0 1 0 0 0 0 s ₂ 1 y ₁ 0 0 1 1 1 1 4 x ₃ 0 0 0 0 0 0 s ₃ 0 y ₂ 0 0 0 0 0 0 5 1 1 0 0 0 0 0 - - y ₃ 1 0 0 0 0 0 6 - 0 1 0 0 0 0 s ₅ 1 - 0 0 1 1 1 1

The structure of table 7 is similar to the structure of table 5.

Table 8 - Multiplexer 3 status table Inputs Exits A B S 1st category 1 1 1 2nd category 0 0 0 3rd category 0 1 1 4th category 0 0 0

Table 8 shows the values of the signals at the information inputs and information outputs of multiplexer 3 at the sixth cycle. In accordance with Table 7, the control input of multiplexer 3 receives the signal s ₅ =1. As a result, the number 0101 ₂ =5 ₁₀ is received at the information outputs 8 of the device in the sixth cycle. By direct verification we establish 8+9 5 mod 12.

The invention makes it possible to perform operations of conveyor summation of numbers in any modules, and not just in modules of prime numbers; in addition, the invention allows you to quickly set its own module for each pair of numbers, without requiring additional preliminary configuration operations, which expands the functionality of the device during conveyor information processing.

Information sources.

1. Patent for invention RU 2310223 C1. IPC G06F 7/72 (2006.01). A homogeneous computing structure for performing operations according to a given module. Published 11/10/2007. Bull. No. 31.

2. Patent for invention RU 2477513 C1. IPC G06F 7/72 (2006.01). A cell of a homogeneous computing environment, a homogeneous computing environment and a device for pipeline arithmetic calculations according to a given module. Published 03/10/2013. Bull. No. 7.

Claims (1)

A device for conveyor summation of numbers by an arbitrary modulus, containing a first homogeneous computing environment of bit depth n , where n is the bit depth of the numbers being processed, first, second and third information inputs, information outputs and a clock input, which is connected to the synchronization input of the first homogeneous computing environment, characterized in that , that it contains a second homogeneous computing environment of capacity ( n +1), a group of full single-bit adders and a multiplexer of capacity n , and the first information inputs of the device are connected to the first information inputs of the first homogeneous computing environment and to the first information inputs of the group of complete single-bit adders, the second the information inputs of the device are connected to the second information inputs of the first homogeneous computing environment and to the second information inputs of the group of full single-bit adders, the third information inputs of the device are connected to the third information inputs of the group of full single-bit adders, the first information outputs of which are connected to the lower n bits of the first information inputs of the second homogeneous computing environment, the second information outputs are connected to the second information inputs of the second homogeneous computing environment with a shift of one bit towards the higher one, a logical one signal is supplied to the ( n +1)th bit of the first information inputs and to the first bit of the second information inputs of the second computing environment , the synchronization input of the second homogeneous computing environment is connected to the clock input of the device, the low n bits of the information outputs are connected to the second information inputs of the multiplexer, and the output of the transfer bit is connected to the control input of the multiplexer, the first information inputs of which are connected to the information outputs of the first homogeneous computing environment, and the outputs connected to the information outputs of the device.