RU1354963C - Device for count loss compensation in spectrometer - Google Patents

Abstract

The invention relates to nuclear instrumentation and can be used to eliminate count loss in precision nuclear radiation spectrometers. The purpose of the invention is to increase accuracy by reducing error and increasing reliability. In the device containing the shaper, two pulse counters. multiplexer, n memory elements, de-multiplexer and analog-to-digital converter, matching pulse separator introduced, reversible The invention relates to nuclear instrumentation and can be used to eliminate count losses in precision nuclear radiation spectrometers, The purpose of the invention is to increase the accuracy of by reducing error and increasing reliability. The drawing shows a functional diagram of a device for eliminating count losses in a spectrometer. The device contains a driver 1. demultiplexer 2. pulse counter 3. n memory elements 4. multiplexer 5. analog-to-digital converter (ADC) 6. pulse counter 7. separator is the same counter and element OR, The output of the last bit of the reverse counter is connected to the control the key input, which blocks the input of the device until the processing of the first pulse is completed and the reverse counter is thrown back one state, as a result of which the inhibit signal at the key input is removed, and then impulses can pass into the device. If there are no more input pulses, then at the end of the processing of the last pulse that was recorded on the memory elements, the reverse counter will be in the zero state, while the output of the OR element will be a signal zero, which will stop the further operation of the ADC until the next input pulse, which makes it possible to almost completely exclude the possibility of writing to the same memory element until the amplitude of the previous pulse is completely processed. 1 ill. pulses 8. reversible counter 9, OR element 10 and key 11. Key 11. the information input of which is the input of the device is connected by the output to the information input of multiplexer 2, and through the former 1 to one input of the separator of matching pulses and the counting input of the pulse counter - sovz. whose bit outputs are connected to the corresponding control inputs of the demultiplexer 2, connected by the outputs through the corresponding memory elements 4 to the information inputs of the multiplexer 5. the output of which is connected to the information input of the ADC 6. digital

Description

the outputs of which are the outputs of the device, and the readiness output of which, which is the output of the end of the conversion of the device, is connected to another input of the splitter of matching pulses

8 and the counting input of the pulse counter 7, connected by the bit outputs to the corresponding control inputs of the multiplexer 5 and the zeroing input, which is the reset input of the device, with the reset inputs of the counter 3 and the reverse counter 9, the bit output of which is connected to the corresponding inputs of the OR element 10, connected by the output to the control input of the ADC 6. The output of the last bit of the reverse counter 9 is connected to the control input of the key 11.

A device for eliminating count losses in a spectrometer operates as follows.

The input of the device is connected to the output of the measuring transducer, and the output is connected to the storage unit of the spectrometer (not shown in the drawing). Before starting work on the reset input of the device, the pulse counters of 3 and 7 m are reset to a reverse counter 9, while the first input pulse at the outputs of all bits of the reverse counter is received at the device’s input e

9 there is a signal zero, which is connected through the multi-input element 1 / 1L1L 10 to the control input of the ADC 6. The input of the device through the key 1 and demultiplexer 2 is connected to the first memory element 4, the output of which through the multiplexer 5 is connected to the input of the ADC 6. When When the first pulse arrives at the input of the device, it passes through a key 11, a demultiplexer 2, and its amplitude is stored in the first memory element 4. The same input pulse passes through a shaper 1, which from pulses of different amplitudes forms pulses with an amplitude equal to unit, and the duration required to operate the pulse counter 3 and the coincident pulse separator 8. When the input pulse changes from one to zero, the pulse counter 3 goes into the first state; through demultiplexer 2, it connects the second memory element 4 to the device input. the pulse from the output of the former 1 passes through a separator of coincident pulses 8 to the summing input of the reverse counter 9, which also goes into the first state. At the same time, at the output of its first bit, a single signal appears, which passes through a multiple input, a new element OR 10 to the control input of the ADC 6. which is triggered and converts the amplitude

first pulse in a digital code. At the end of the conversion cycle, the ADC 6 generates a signal at the ready output, which, simultaneously with a digital code corresponding to the amplitude of the converted pulse, is supplied to the storage unit of the spectrometer, in the memory block of which, at the address corresponding to the digital code of the converted input pulse, one is counted. At the same time, the same signal passes to the counting input of the pulse counter 7, transfers it to the first state, i.e. through the multiplexer 5 connects the input of the ADC 6 to the second memory element 4, and through

the coincident pulse separator 8 takes the reverse counter 9 back one state. If during the conversion of the first pulse to the input of the device receives a second pulse, then it is similar

stored on the second memory element 4, and upon its decline, the counting and pulse 3 goes into the second state, i.e. connects to the input of the device through the demultiplexer 2 the third memory element 4 and through the separator of matching pulses 8 puts the reverse counter 8 in the second state. After the conversion of the amplitude of the first pulse to a digital code is completed, the reverse counter 9 switches from the second

state to the first, and through the element OR 10, the next conversion cycle is started, since the second pulse element already has the amplitude of the second pulse.

After the end of the second cycle, if

this time the third input pulse did not come, the signal from the ADC 6 ready output transfers the pulse counter 7 to the second state, while connecting the ADC 6 input through multiplexer 5 to the third element

memory 4, and the reverse counter 9 goes to the zero state, i.e. in a state in which the pulse counters 3 and 7 are in the same state. The zero state of the reverse counter 9 means.

that all pulses arriving at the input of the device are processed and there is zero at the outputs of all its bits, i.e. at the output of the element OR 1 there is also a signal zero, which prohibits 6 to start a new one

0 conversion cycle until the moment when the third input pulse arrives at the input of the device, which transfers the pulse counter 3 to the third state, and through the separator of matching pulses 8

B will translate the reverse counter 9 into the first state, removing the inhibit signal from the control input of the ADC 6.

If the pulse counters 3 and 7 have a conversion factor of 2, where n is the bit of the demultiplexer .-} 2 and multiplexer 5, TO after the arrival of the input pulse, all 2 memory elements will be filled and pulse counter 3 will again go to the zero state, and after that, the () th input and the pulse will be stored in the first memory element 4.

Thus, if the difference between the number of incoming and processed pulses does not exceed 2. eliminates the loss of pulses during the conversion time of the ADC 6, which eliminates the loss of counting when registering statistical sequences of pulses.

However, if the difference between the pulses arriving at the input of the device and the processed pulses is 2, then after storing the amplitude of the pulses in the memory elements 4, the reverse counter 9 goes into a state in which the signal lasts one (n + 1) bit, which will lock the key 11 until the processing of the next input pulse is completed, thereby eliminating the possibility of re-recording the amplitude of the next input pulse in memory element 4, the amplitude of the previous filled input pulse of which has not yet been processed, which reduces the measurement error of the spectrometer.

Claims (1)

The claims A device for eliminating count losses in a spectrometer containing a demultiplexer, two pulse counters, an analog-to-digital converter, a multiplexer, p memory elements and a driver connected to the information input of the demultiplexer by the input and to the counting input of the first pulse counter, bit the outputs of which are connected to the corresponding control inputs of the demultiplexer, connected by the outputs through the corresponding memory elements to the information inputs of the multiplexer, the output of which is 5 with the information input of an analog-to-digital converter, the digital outputs of which are the outputs of the device, and the readiness output of which, which is the output of the end of the conversion of the device, is connected to the counting input of the second counter, pulses connected by the bit outputs to the corresponding control inputs of the multiplexer and the zeroing input, which is the 5th reset input of the device, with the zeroing input of the first counter, characterized in that, in order to increase accuracy by reducing the error and increasing Reliability, it introduced 0 coincident pulse separator, reversible counter with the number of bits one greater than the bit of both counters, an OR element and a key, the information input of which is the input of the device5, connected by an output to the input of the driver and a control input to the output of the last bit of the reverse counter and one input of the OR element, the output of which is connected to the control 0 to the input of the analog-to-digital converter, the matching pulse separator is connected by the first and second inputs to the counting inputs of the first and second pulse counters, respectively, and the first and 5 by the second outputs, respectively, with the summing and subtracting inputs of the reversible counter, the bit outputs of which are connected to the corresponding inputs of the OR element and whose zeroing input 0 is connected to the device reset input. Editor L. Letters Compiled by Tehred M. Morgenthal Order 544 Mintage VNIIIPI of the State Committee for Inventions and Discover at the USSR State Committee for Science and Technology 113035, Moscow, Zh-35, Rauska nab., 4/5 Production and Publishing House Patent, Uzhhorod, 101 Gagarina St. BymZ Proofreader M. Andrushenko