PH23858A - Graphic display system with display line scan based other than power of 2 refresh memory based on the power of 2 - Google Patents

Graphic display system with display line scan based other than power of 2 refresh memory based on the power of 2

Info

Publication number
PH23858A
PH23858A PH29953A PH29953A PH23858A PH 23858 A PH23858 A PH 23858A PH 29953 A PH29953 A PH 29953A PH 29953 A PH29953 A PH 29953A PH 23858 A PH23858 A PH 23858A
Authority
PH
Philippines
Prior art keywords
power
line scan
refresh memory
display system
graphic display
Prior art date
Application number
PH29953A
Other languages
English (en)
Inventor
Yoshikazu Yoshioka
Original Assignee
Ibm
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Ibm filed Critical Ibm
Publication of PH23858A publication Critical patent/PH23858A/en

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
    • G06F3/14—Digital output to display device ; Cooperation and interconnection of the display device with other functional units
    • G06F3/153—Digital output to display device ; Cooperation and interconnection of the display device with other functional units using cathode-ray tubes
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G5/00—Control arrangements or circuits for visual indicators common to cathode-ray tube indicators and other visual indicators
    • G09G5/36—Control arrangements or circuits for visual indicators common to cathode-ray tube indicators and other visual indicators characterised by the display of a graphic pattern, e.g. using an all-points-addressable [APA] memory
    • G09G5/39—Control of the bit-mapped memory
    • G09G5/395—Arrangements specially adapted for transferring the contents of the bit-mapped memory to the screen
    • B—PERFORMING OPERATIONS; TRANSPORTING
    • B62—LAND VEHICLES FOR TRAVELLING OTHERWISE THAN ON RAILS
    • B62L—BRAKES SPECIALLY ADAPTED FOR CYCLES
    • B62L3/00—Brake-actuating mechanisms; Arrangements thereof
    • B62L3/04—Brake-actuating mechanisms; Arrangements thereof for control by a foot lever
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G5/00—Control arrangements or circuits for visual indicators common to cathode-ray tube indicators and other visual indicators
    • G09G5/34—Control arrangements or circuits for visual indicators common to cathode-ray tube indicators and other visual indicators for rolling or scrolling
    • G09G5/346—Control arrangements or circuits for visual indicators common to cathode-ray tube indicators and other visual indicators for rolling or scrolling for systems having a bit-mapped display memory

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Mechanical Engineering (AREA)
  • Human Computer Interaction (AREA)
  • General Engineering & Computer Science (AREA)
  • Controls And Circuits For Display Device (AREA)
  • Image Generation (AREA)
PH29953A 1983-02-24 1983-12-09 Graphic display system with display line scan based other than power of 2 refresh memory based on the power of 2 PH23858A (en)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP58028635A JPS59159196A (ja) 1983-02-24 1983-02-24 グラフイツク・デイスプレイ・システム

Publications (1)

Publication Number Publication Date
PH23858A true PH23858A (en) 1989-11-23

Family

ID=12253992

Family Applications (1)

Application Number Title Priority Date Filing Date
PH29953A PH23858A (en) 1983-02-24 1983-12-09 Graphic display system with display line scan based other than power of 2 refresh memory based on the power of 2

Country Status (8)

Country Link
US (1) US4617564A (pt)
EP (1) EP0120142B1 (pt)
JP (1) JPS59159196A (pt)
KR (1) KR860001450B1 (pt)
BR (1) BR8400757A (pt)
DE (1) DE3380712D1 (pt)
HK (1) HK20490A (pt)
PH (1) PH23858A (pt)

Families Citing this family (13)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4755810A (en) * 1985-04-05 1988-07-05 Tektronix, Inc. Frame buffer memory
US4769637A (en) * 1985-11-26 1988-09-06 Digital Equipment Corporation Video display control circuit arrangement
US4780709A (en) * 1986-02-10 1988-10-25 Intel Corporation Display processor
JP2829958B2 (ja) * 1988-01-27 1998-12-02 ソニー株式会社 タイトル画像挿入装置
GB9021920D0 (en) * 1990-10-09 1990-11-21 Texas Instruments Ltd Improvements in or relating to raster-scanned displays
US5170251A (en) * 1991-05-16 1992-12-08 Sony Corporation Of America Method and apparatus for storing high definition video data for interlace or progressive access
KR950005650B1 (ko) * 1992-10-29 1995-05-27 대우전자주식회사 어드레스 변환 방법 및 장치
DE69430982T2 (de) * 1993-12-09 2003-03-13 Sun Microsystems Inc Verschachtelung von Bildelementdaten für eine Darstellungspeicherschnittstelle
US5596376A (en) * 1995-02-16 1997-01-21 C-Cube Microsystems, Inc. Structure and method for a multistandard video encoder including an addressing scheme supporting two banks of memory
JP4181645B2 (ja) * 1996-02-29 2008-11-19 富士通株式会社 データ処理装置
WO2004068974A1 (en) * 2003-02-03 2004-08-19 Panchapagesa Muthuswamy Murali A process of preparing a herbal filler composition for bidi cigarette and the like
JP4753873B2 (ja) * 2004-06-23 2011-08-24 パトレネラ キャピタル リミテッド， エルエルシー メモリ
JP4714590B2 (ja) * 2006-01-23 2011-06-29 パトレネラ キャピタル リミテッド， エルエルシー メモリ

Family Cites Families (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3916402A (en) * 1973-12-17 1975-10-28 Ibm Synchronization of display frames with primary power source
JPS5858674B2 (ja) * 1979-12-20 1983-12-26 日本アイ・ビ−・エム株式会社 陰極線管表示装置
JPS5756885A (en) * 1980-09-22 1982-04-05 Nippon Electric Co Video address control device
JPS602669B2 (ja) * 1980-12-24 1985-01-23 松下電器産業株式会社 画面表示装置
US4435703A (en) * 1981-07-06 1984-03-06 Data General Corporation Apparatus and method for simultaneous display of characters of variable size and density

Also Published As

Publication number Publication date
HK20490A (en) 1990-03-23
US4617564A (en) 1986-10-14
EP0120142B1 (en) 1989-10-11
EP0120142A3 (en) 1987-02-25
JPS59159196A (ja) 1984-09-08
EP0120142A2 (en) 1984-10-03
JPS646478B2 (pt) 1989-02-03
KR840008070A (ko) 1984-12-12
DE3380712D1 (en) 1989-11-16
KR860001450B1 (ko) 1986-09-25
BR8400757A (pt) 1984-10-02

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