NO885280D0 - Digital, faselst slfekrets med h opplning. - Google Patents
Digital, faselst slfekrets med h opplning.Info
- Publication number
- NO885280D0 NO885280D0 NO885280A NO885280A NO885280D0 NO 885280 D0 NO885280 D0 NO 885280D0 NO 885280 A NO885280 A NO 885280A NO 885280 A NO885280 A NO 885280A NO 885280 D0 NO885280 D0 NO 885280D0
- Authority
- NO
- Norway
- Prior art keywords
- slfekrets
- opplning
- digital
- phase
- down slfekrets
- Prior art date
Links
Classifications
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
- H03L7/00—Automatic control of frequency or phase; Synchronisation
- H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
- H03L7/08—Details of the phase-locked loop
- H03L7/081—Details of the phase-locked loop provided with an additional controlled phase shifter
- H03L7/0812—Details of the phase-locked loop provided with an additional controlled phase shifter and where no voltage or current controlled oscillator is used
- H03L7/0814—Details of the phase-locked loop provided with an additional controlled phase shifter and where no voltage or current controlled oscillator is used the phase shifting device being digitally controlled
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
- H03L7/00—Automatic control of frequency or phase; Synchronisation
- H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
- H03L7/08—Details of the phase-locked loop
- H03L7/081—Details of the phase-locked loop provided with an additional controlled phase shifter
- H03L7/0812—Details of the phase-locked loop provided with an additional controlled phase shifter and where no voltage or current controlled oscillator is used
- H03L7/0816—Details of the phase-locked loop provided with an additional controlled phase shifter and where no voltage or current controlled oscillator is used the controlled phase shifter and the frequency- or phase-detection arrangement being connected to a common input
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L7/00—Arrangements for synchronising receiver with transmitter
- H04L7/02—Speed or phase control by the received code signals, the signals containing no special synchronisation information
- H04L7/033—Speed or phase control by the received code signals, the signals containing no special synchronisation information using the transitions of the received signal to control the phase of the synchronising-signal-generating means, e.g. using a phase-locked loop
- H04L7/0337—Selecting between two or more discretely delayed clocks or selecting between two or more discretely delayed received code signals
Landscapes
- Engineering & Computer Science (AREA)
- Computer Networks & Wireless Communication (AREA)
- Signal Processing (AREA)
- Stabilization Of Oscillater, Synchronisation, Frequency Synthesizers (AREA)
- Synchronisation In Digital Transmission Systems (AREA)
- Electrical Discharge Machining, Electrochemical Machining, And Combined Machining (AREA)
- Interface Circuits In Exchanges (AREA)
- Control Of El Displays (AREA)
- Manipulation Of Pulses (AREA)
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US07/125,523 US4847870A (en) | 1987-11-25 | 1987-11-25 | High resolution digital phase-lock loop circuit |
Publications (4)
Publication Number | Publication Date |
---|---|
NO885280D0 true NO885280D0 (no) | 1988-11-25 |
NO885280L NO885280L (no) | 1989-05-26 |
NO173719B NO173719B (no) | 1993-10-11 |
NO173719C NO173719C (no) | 1994-01-19 |
Family
ID=22420109
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
NO885280A NO173719C (no) | 1987-11-25 | 1988-11-25 | Digital, faselaast sloeyfekrets med hoey opploesning |
Country Status (3)
Country | Link |
---|---|
US (1) | US4847870A (no) |
EP (1) | EP0317821A3 (no) |
NO (1) | NO173719C (no) |
Families Citing this family (25)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2554705B2 (ja) * | 1988-04-25 | 1996-11-13 | 三菱電機株式会社 | 位相同期回路 |
US5087829A (en) * | 1988-12-07 | 1992-02-11 | Hitachi, Ltd. | High speed clock distribution system |
US5109394A (en) * | 1990-12-24 | 1992-04-28 | Ncr Corporation | All digital phase locked loop |
US5157342A (en) * | 1991-08-30 | 1992-10-20 | The United States Of America As Represented By The Secretary Of The Navy | Precision digital phase lock loop circuit |
US5163067A (en) * | 1991-11-21 | 1992-11-10 | Northern Telecom Limited | Method and apparatus for decoding Manchester encoded data |
DE4209843A1 (de) * | 1992-03-26 | 1993-11-18 | Telefunken Microelectron | Temperaturkompensierte Oszillatoranordnung |
JP3247190B2 (ja) * | 1993-04-13 | 2002-01-15 | 三菱電機株式会社 | 位相同期回路および集積回路装置 |
US5539784A (en) * | 1994-09-30 | 1996-07-23 | At&T Corp. | Refined timing recovery circuit |
US5859881A (en) * | 1996-06-07 | 1999-01-12 | International Business Machines Corporation | Adaptive filtering method and apparatus to compensate for a frequency difference between two clock sources |
JP3487532B2 (ja) * | 1996-07-08 | 2004-01-19 | 株式会社東芝 | データ処理装置、半導体記憶装置、及びデータ処理方法 |
US5903176A (en) * | 1996-09-04 | 1999-05-11 | Litton Systems, Inc. | Clock circuit for generating a high resolution output from a low resolution clock |
US6034558A (en) * | 1997-07-17 | 2000-03-07 | Credence Systems Corporation | Method and apparatus for compensating for thermal drift in a logic circuit |
US6058151A (en) * | 1997-08-19 | 2000-05-02 | Realtek Semiconductor Corp. | Digital phase shift phase-locked loop for data and clock recovery |
US6069506A (en) * | 1998-05-20 | 2000-05-30 | Micron Technology, Inc. | Method and apparatus for improving the performance of digital delay locked loop circuits |
US6137334A (en) * | 1998-07-06 | 2000-10-24 | Micron Technology, Inc. | Logic circuit delay stage and delay line utilizing same |
EP0987853A1 (en) | 1998-09-17 | 2000-03-22 | STMicroelectronics S.r.l. | A fully digital phase aligner |
US6242955B1 (en) * | 1999-09-20 | 2001-06-05 | Silicon Magic Corporation | Delay lock loop circuit, system and method for synchronizing a reference signal with an output signal |
DE69929201D1 (de) * | 1999-10-18 | 2006-02-02 | St Microelectronics Srl | Verbesserte Verzögerungsregelschleife |
US6442697B1 (en) | 2000-03-24 | 2002-08-27 | Intel Corporation | Method and apparatus to control processor power and performance for single phase lock loop (PLL) processor systems |
EP1179900A1 (en) * | 2000-08-11 | 2002-02-13 | Alcatel | Optical receiver with a clock recovery of an input signal and an added phase correction of the clock recovered |
US20030194046A1 (en) * | 2002-04-11 | 2003-10-16 | Shirar Jerry Lester | Method for period counting using a tunable oscillator |
US7106655B2 (en) * | 2004-12-29 | 2006-09-12 | Micron Technology, Inc. | Multi-phase clock signal generator and method having inherently unlimited frequency capability |
JP2009141569A (ja) * | 2007-12-05 | 2009-06-25 | Sony Corp | クロック信号生成回路、表示パネルモジュール、撮像デバイス及び電子機器 |
US8068559B1 (en) | 2008-06-09 | 2011-11-29 | Adtran, Inc. | Pulse width modulation (PWM) clock and data receiver and method for recovering information from received data signals |
US8390352B2 (en) * | 2009-04-06 | 2013-03-05 | Honeywell International Inc. | Apparatus and method for compensating for process, voltage, and temperature variation of the time delay of a digital delay line |
Family Cites Families (15)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US3238459A (en) * | 1961-12-14 | 1966-03-01 | Collins Radio Co | Unambiguous local phase reference for data detection |
US3509471A (en) * | 1966-11-16 | 1970-04-28 | Communications Satellite Corp | Digital phase lock loop for bit timing recovery |
US3585298A (en) * | 1969-12-30 | 1971-06-15 | Ibm | Timing recovery circuit with two speed phase correction |
US3697689A (en) * | 1970-12-23 | 1972-10-10 | North American Rockwell | Fine timing recovery system |
US3646452A (en) * | 1971-02-16 | 1972-02-29 | Ibm | Second order digital phaselock loop |
BE791484A (nl) * | 1971-11-18 | 1973-05-16 | Trt Telecom Radio Electr | Systeem voor synchrone datatransmissie over een synchroon digitaal transmissiekanaal |
US3777272A (en) * | 1972-09-18 | 1973-12-04 | Nasa | Digital second-order phase-locked loop |
JPS54148412A (en) * | 1978-05-15 | 1979-11-20 | Ricoh Co Ltd | Reproduction system for timing information |
US4400817A (en) * | 1980-12-30 | 1983-08-23 | Motorola, Inc. | Method and means of clock recovery in a received stream of digital data |
US4385396A (en) * | 1981-06-05 | 1983-05-24 | Phillips Petroleum Company | NRZ Digital data recovery |
US4617679A (en) * | 1983-09-20 | 1986-10-14 | Nec Electronics U.S.A., Inc. | Digital phase lock loop circuit |
JPS60204121A (ja) * | 1984-03-29 | 1985-10-15 | Fujitsu Ltd | 位相同期回路 |
US4604582A (en) * | 1985-01-04 | 1986-08-05 | Lockheed Electronics Company, Inc. | Digital phase correlator |
CA1297171C (en) * | 1986-04-01 | 1992-03-10 | Samuel Howard Gailbreath Jr. | Digital phase lock loop |
US4680780A (en) * | 1986-05-01 | 1987-07-14 | Tektronix, Inc. | Clock recovery digital phase-locked loop |
-
1987
- 1987-11-25 US US07/125,523 patent/US4847870A/en not_active Expired - Fee Related
-
1988
- 1988-11-08 EP EP19880118590 patent/EP0317821A3/en not_active Ceased
- 1988-11-25 NO NO885280A patent/NO173719C/no unknown
Also Published As
Publication number | Publication date |
---|---|
NO885280L (no) | 1989-05-26 |
NO173719C (no) | 1994-01-19 |
EP0317821A2 (en) | 1989-05-31 |
EP0317821A3 (en) | 1990-10-10 |
NO173719B (no) | 1993-10-11 |
US4847870A (en) | 1989-07-11 |
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