NO20052518L - Ekstra cellearkitektur for handtering av konstruksjonsfeil ved produksjon av integrerte kretser - Google Patents

Ekstra cellearkitektur for handtering av konstruksjonsfeil ved produksjon av integrerte kretser

Info

Publication number
NO20052518L
NO20052518L NO20052518A NO20052518A NO20052518L NO 20052518 L NO20052518 L NO 20052518L NO 20052518 A NO20052518 A NO 20052518A NO 20052518 A NO20052518 A NO 20052518A NO 20052518 L NO20052518 L NO 20052518L
Authority
NO
Norway
Prior art keywords
replacement
input bus
cell
production
integrated circuits
Prior art date
Application number
NO20052518A
Other languages
English (en)
Norwegian (no)
Other versions
NO20052518D0 (no
Inventor
Alain Vergnes
Original Assignee
Atmel Corp A Delaware Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Atmel Corp A Delaware Corp filed Critical Atmel Corp A Delaware Corp
Publication of NO20052518D0 publication Critical patent/NO20052518D0/no
Publication of NO20052518L publication Critical patent/NO20052518L/no

Links

Classifications

    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/02—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components
    • H03K19/173—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components
    • H03K19/177—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components arranged in matrix form
    • H03K19/17748—Structural details of configuration resources
    • H03K19/17764—Structural details of configuration resources for reliability
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/003—Modifications for increasing the reliability for protection
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/02—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components
    • H03K19/173—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components
    • H03K19/177—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components arranged in matrix form
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/02—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components
    • H03K19/173—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components
    • H03K19/177—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components arranged in matrix form
    • H03K19/17736—Structural details of routing resources
    • H03K19/1774—Structural details of routing resources for global signals, e.g. clock, reset
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/02—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components
    • H03K19/173—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components
    • H03K19/177—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components arranged in matrix form
    • H03K19/1778—Structural details for adapting physical parameters
    • H03K19/17796—Structural details for adapting physical parameters for physical disposition of blocks
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations

Landscapes

  • Physics & Mathematics (AREA)
  • Mathematical Physics (AREA)
  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Computing Systems (AREA)
  • General Engineering & Computer Science (AREA)
  • Computer Networks & Wireless Communication (AREA)
  • Design And Manufacture Of Integrated Circuits (AREA)
  • Semiconductor Integrated Circuits (AREA)
  • Logic Circuits (AREA)
NO20052518A 2002-10-25 2005-05-25 Ekstra cellearkitektur for handtering av konstruksjonsfeil ved produksjon av integrerte kretser NO20052518L (no)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
FR0213399A FR2846491B1 (fr) 2002-10-25 2002-10-25 Architecture comprenant des cellules de remplacement pour reparer des erreurs de conception dans des circuits integres apres fabrication
PCT/US2003/029718 WO2004040764A1 (en) 2002-10-25 2003-09-17 Spare cell architecture for fixing design errors in manufactured integrated circuits

Publications (2)

Publication Number Publication Date
NO20052518D0 NO20052518D0 (no) 2005-05-25
NO20052518L true NO20052518L (no) 2005-07-25

Family

ID=32088293

Family Applications (1)

Application Number Title Priority Date Filing Date
NO20052518A NO20052518L (no) 2002-10-25 2005-05-25 Ekstra cellearkitektur for handtering av konstruksjonsfeil ved produksjon av integrerte kretser

Country Status (11)

Country Link
US (1) US6791355B2 (de)
EP (1) EP1568133A4 (de)
JP (1) JP2006518095A (de)
KR (1) KR20050065621A (de)
CN (1) CN1714508A (de)
AU (1) AU2003275085A1 (de)
CA (1) CA2502077A1 (de)
FR (1) FR2846491B1 (de)
NO (1) NO20052518L (de)
TW (1) TW200414680A (de)
WO (1) WO2004040764A1 (de)

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* Cited by examiner, † Cited by third party
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CA2338458A1 (en) * 2001-02-27 2001-08-14 Ioan Dancea Method and vlsi circuits allowing to change dynamically the logical behaviour
JP2006128635A (ja) * 2004-09-30 2006-05-18 Matsushita Electric Ind Co Ltd 半導体集積回路
US20090045836A1 (en) * 2007-08-15 2009-02-19 Herzl Robert D Asic logic library of flexible logic blocks and method to enable engineering change
US20090045839A1 (en) * 2007-08-15 2009-02-19 International Business Machines Corporation Asic logic library of flexible logic blocks and method to enable engineering change
US9122553B2 (en) * 2007-12-01 2015-09-01 Sony Corporation Synchronous bus download of TV software update
US8166439B2 (en) * 2007-12-28 2012-04-24 International Business Machines Corporation Techniques for selecting spares to implement a design change in an integrated circuit
US8181148B2 (en) * 2008-01-15 2012-05-15 International Business Machines Corporation Method for identifying and implementing flexible logic block logic for easy engineering changes
US8141028B2 (en) * 2008-01-15 2012-03-20 International Business Machines Corporation Structure for identifying and implementing flexible logic block logic for easy engineering changes
US7971162B2 (en) * 2008-02-18 2011-06-28 International Business Machines Corporation Verification of spare latch placement in synthesized macros
JPWO2010100830A1 (ja) * 2009-03-05 2012-09-06 日本電気株式会社 半導体装置、回路修正方法、設計支援装置及び設計支援プログラム
KR101677760B1 (ko) * 2009-12-11 2016-11-29 삼성전자주식회사 핀 익스텐션을 이용하여 오류 교정이 가능한 반도체 장치 및 그 설계 방법
US7902855B1 (en) * 2010-03-03 2011-03-08 Altera Corporation Repairable IO in an integrated circuit
US8234612B2 (en) * 2010-08-25 2012-07-31 International Business Machines Corporation Cone-aware spare cell placement using hypergraph connectivity analysis
US8490039B2 (en) * 2011-12-09 2013-07-16 International Business Machines Corporation Distributing spare latch circuits in integrated circuit designs
US9236864B1 (en) 2012-01-17 2016-01-12 Altera Corporation Stacked integrated circuit with redundancy in die-to-die interconnects
US8661391B1 (en) 2013-01-02 2014-02-25 International Business Machines Corporation Spare cell insertion based on reachable state analysis
US9166595B2 (en) 2013-12-27 2015-10-20 Freescale Semiconductor, Inc Configurable flip-flop circuit
US9154135B1 (en) 2014-04-27 2015-10-06 Freescale Semiconductor, Inc. Spare gate cell for integrated circuit
US10082541B2 (en) 2015-06-11 2018-09-25 Altera Corporation Mixed redundancy scheme for inter-die interconnects in a multichip package
US11139217B2 (en) * 2019-09-09 2021-10-05 Bae Systems Information And Electronic Systems Integration Inc. Post-production substrate modification with FIB deposition

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Publication number Priority date Publication date Assignee Title
US3434116A (en) 1966-06-15 1969-03-18 Ibm Scheme for circumventing bad memory cells
US4551814A (en) * 1983-12-12 1985-11-05 Aerojet-General Corporation Functionally redundant logic network architectures
US5161157A (en) 1990-03-12 1992-11-03 Xicor, Inc. Field-programmable redundancy apparatus for memory arrays
DE4038610C1 (en) * 1990-12-04 1992-05-07 Ernst, R., Prof. Dr., 3302 Cremlingen, De Fault-tolerant digital computer circuit - has normal function blocks and redundant function blocks with switching control
JP3365581B2 (ja) * 1994-07-29 2003-01-14 富士通株式会社 自己修復機能付き情報処理装置
US5696943A (en) * 1995-07-27 1997-12-09 Advanced Micro Devices, Inc. Method and apparatus for quick and reliable design modification on silicon
US6091258A (en) 1997-02-05 2000-07-18 Altera Corporation Redundancy circuitry for logic circuits
EP0983549B1 (de) 1997-05-23 2001-12-12 Altera Corporation (a Delaware Corporation) Redundanzschaltung für programmierbare logikanordnung mit verschachtelten eingangsschaltkreisen
US6154851A (en) 1997-08-05 2000-11-28 Micron Technology, Inc. Memory repair
US5959905A (en) * 1997-10-31 1999-09-28 Vlsi Technology, Inc. Cell-based integrated circuit design repair using gate array repair cells
US5920765A (en) 1997-12-12 1999-07-06 Naum; Michael IC wafer-probe testable flip-chip architecture
US6199177B1 (en) 1998-08-28 2001-03-06 Micron Technology, Inc. Device and method for repairing a semiconductor memory
US6404226B1 (en) * 1999-09-21 2002-06-11 Lattice Semiconductor Corporation Integrated circuit with standard cell logic and spare gates
US6181614B1 (en) 1999-11-12 2001-01-30 International Business Machines Corporation Dynamic repair of redundant memory array
US6255845B1 (en) * 1999-11-16 2001-07-03 Advanced Micro Devices, Inc. Efficient use of spare gates for post-silicon debug and enhancements
US6446248B1 (en) * 2000-01-28 2002-09-03 Lsi Logic Corporation Spare cells placement methodology
US6304122B1 (en) * 2000-08-17 2001-10-16 International Business Machines Corporation Low power LSSD flip flops and a flushable single clock splitter for flip flops
US6614263B2 (en) * 2002-02-05 2003-09-02 Logicvision, Inc. Method and circuitry for controlling clocks of embedded blocks during logic bist test mode

Also Published As

Publication number Publication date
EP1568133A4 (de) 2005-11-30
FR2846491B1 (fr) 2005-08-12
US6791355B2 (en) 2004-09-14
AU2003275085A1 (en) 2004-05-25
KR20050065621A (ko) 2005-06-29
TW200414680A (en) 2004-08-01
US20040080334A1 (en) 2004-04-29
CN1714508A (zh) 2005-12-28
NO20052518D0 (no) 2005-05-25
EP1568133A1 (de) 2005-08-31
CA2502077A1 (en) 2004-05-13
FR2846491A1 (fr) 2004-04-30
JP2006518095A (ja) 2006-08-03
WO2004040764A1 (en) 2004-05-13

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