NL9100536A - SEMICONDUCTOR MEMORY DEVICES. - Google Patents

Description

EXTRACT

A semiconductor memory device with bitline contacts, which are provided in pairs of bitlines in a folded bitline structure, includes a zigzag-shaped bitline connecting the bitline contacts.

The pitch between the bit lines is approximately twice that of the semiconductor memory device with the conventional open bit line structure, thereby reducing the coupling capacity produced by the adjacent bit line. As a result, the noise due to the coupling in the high-density memory of 16 mega and more is considerably reduced.

(figure 5)

Title: Semiconductor ^ memory devices

The invention relates to semiconductor memory devices which are applicable in the class of high density memories of 16 mega and more.

Known semiconductor memory devices have a folded bit line structure or an open bit line structure.

Fig. 1 is a layout of conventional semiconductor memory devices with the folded bit line structure, which includes pairs of bit lines BL and BL arranged parallel to each other. The straight line bit line BL comprises bit line contacts 1 with contacts 2a and 2b buried on both sides, respectively. Bit line BL also has bit line contacts 3, which are provided on both sides with buried contacts 4a and 4b, respectively, and are positioned adjacent to bit line BL between buried contacts 2a and 2b.

Fig. 2 is a circuit showing the semiconductor memory device of FIG. When one word line WL of the word lines WL is selected, a selected cell connected to the word line WL is turned on in the cell string 5, and a cell connected to an adjacent corresponding word line WL is turned off. A reference voltage is produced in the bit line BL, thus an electrical potential is changed by an electrical charge from the selected cell, compared to the reference voltage. The pairs of bit lines BL and EL are connected to sense amplifiers SA so that a difference in potential is detected.

Fig. 3 is a layout of conventional open bit line structure semiconductor memory devices containing parallel bit lines EL arranged in parallel. The straight line bit line BL comprises bit line contacts 6 with contacts 7a and 7b buried on both sides, respectively. The adjacent bit lines BL each have the same pattern.

Fig. 4 is a circuit illustrating the semiconductor memory devices of FIG. Detection amplifiers SA are provided between cell arrays 8a and 8b, where bit line BL is in cell array 8a and bit line BL is in cell array 8b.

The semiconductor memory devices with folded bit line structure can tolerate external noise well and make the arrangement of the sense amplifiers simple. However, a pitch between the bit lines narrows and a torque capacity increases more and more with respect to a higher density. In addition, the open bit line structure semiconductor memory devices are applicable to class 4 mega memories, but when applied to high density memories of 16 mega and above, the arrangement of the sense amplifiers becomes difficult with regard to the decrease in pitch of the memory cell. In addition, the load to be coupled increases and a difference in detection potential decreases in accordance with the narrow pitch between the bit lines, thus delaying the detection time.

An object of the invention is to reduce the bit line length by half per cell of integrity.

These and other objects are accomplished in a semiconductor memory device having bit line contacts in a line pair in a folded bit line structure, which includes a bit line connecting the bit line contacts in a zigzag shape.

These and other objects and features of the invention will become apparent from the following detailed description with reference to the drawings.

Fig. 1 is a layout of conventional semiconductor memory devices with a folded bit line structure; FIG. 2 is a circuit illustrating the semiconductor memory devices of FIG. 1; FIG. 3 is a layout of conventional semiconductor memory devices with a single bit line structure; FIG. 4 is a circuit showing the semiconductor memory devices of FIG. 3; FIG. 5 is a layout of semiconductor memory devices according to a first embodiment of the invention; FIG. 6 is a circuit showing the semiconductor memory devices of FIG. 5; FIG. 7 is a layout of semiconductor memory devices according to a second embodiment of the embodiment; FIG. 8 is a circuit showing the semiconductor memory devices of FIG. 7.

Fig. 5 is a layout of semiconductor memory devices with zigzag bit lines according to a first embodiment of the present invention. The pair of bit lines BL and BL used in semiconductor memory devices of FIG. 1 is combined into one bit line BL. The bit line BL in Fig. 5 has a zigzag shape, which ensures that the bit line contacts 11 are connected at right angles from the top and bottom sides.

The pitch of the zigzag shape of the present invention is about twice that of the open bitline semiconductor memory devices of FIG. 3, which makes the arrangement of detection amplifiers SA simple and a coupling capacity is hardly produced. In addition, the length of the bit line per unit cell has been reduced by half compared to semiconductor memory devices having the conventional open bit 1 structure, thus the detection time has been remarkably improved.

In theory, the RC delay of the semiconductor devices of Fig. 3 is equal to Rx (GJ + CB) (R is the resistance of the bit line, CJ is the junction capacitance, and CB is the bit line capacitance), but the RC delay according to the present invention is equivalent to R / 2x (CJ + CB / 2), using one bit line with the same number of cells. This reduces the RC delay and improves the working speed.

Fig. 6 is a circuit showing the semiconductor memory devices of FIG. When a word line WL is selected in the cell string 13a, the cells associated with the selected word line WL are turned on. In the cell string 13a, the bit lines BL are connected to the sense amplifiers SA. The cells connected to an opposite corresponding word line WL in cell string 13b are turned off, the bit lines BL being connected to the sense amplifiers SA. Therefore, data can be detected with respect to a difference in potential between the selected bit line BL and the bit line BL, which has a reference voltage.

Fig. 7 is a layout of semiconductor memory devices according to a second embodiment of the invention. The bit line contacts 11 in Fig. 7 are connected together at an obtuse angle. Fig. 8 is a circuit showing the semiconductor memory devices of FIG.

As described above, the number of cells per unit length of a bit line is twice that of the semiconductor memory devices with the known open bit line structure, the resistance and coupling capacity being reduced by using one bit line with the same number of cells , so that the detection voltage is increased when detecting data, and the character and operating speed are improved.

In addition, the pitch between the bit lines according to the invention is about twice that of the semiconductor memory devices with the conventional open bit line structure, thereby reducing the coupling capacity produced by the adjacent bit line. As a result, the noise by coupling in the high-density memory of 16 mega and more is considerably reduced.

While the invention has been described herein with reference to specific embodiments, it will be understood that these embodiments are preferred embodiments and that modifications may be made without departing from the scope of the invention defined in the accompanying claims.

Claims (3)

1. Semiconductor memory device with bit line contacts provided in a folded bit line structure, characterized in that the bit line connecting the bit line contacts has a zigzag shape. Semiconductor memory device according to claim 1, characterized in that the bit line contacts are connected to each other at right angles. Semiconductor memory device according to claim 1, characterized in that the bit line contacts are connected to each other at an obtuse angle.