JPH0276258A - Semiconductor memory device - Google Patents

Abstract

PURPOSE:To lessen a capacity of a bit line and thereby to reduce power consumption by providing unit cells along one bit line and on the opposite sides thereof, by arranging them regularly in a state of being shifted from each other by a 1/2 pitch so as to form two unit cell arrays, and by connecting all the unit cells of basic units to one bit line. CONSTITUTION:Unit cells MC in adjacent unit cell arrays are disposed in a zigzag state being shifted from each other by a 1/2 pitch, and these two unit cell arrays are connected to one bit line 121-4, so as to form an open bit line. Accordingly, the length of the bit line is 1/2 of that in the form of a folded bit line, though the unit cells are disposed quite in the same way as in this form, and consequently a parasitic capacity turns to be 1/2 as well. Thereby an output signal voltage is improved to be doubled approximately and power consumption is reduced to about 1/2.

Description

[Detailed Description of the Invention] [Summary] This invention relates to a semiconductor memory device with an improved arrangement of bit lines versus memory cells, and reduces power consumption by reducing bit line capacitance without changing the conventional manufacturing process. enable and D
memory without affecting the characteristics and functionality of RAM.
In order to realize a reduction in cell area, one source area, which is a bit line contact area, and a pair of word lines, which are gate electrodes, extending on both sides of the source area in a direction intersecting with the bit line, are provided. A unit cell whose basic unit is a pair of memory cells consisting of a pair of drain regions, which are storage electrode contact regions facing the source region via a channel region, and a charge storage capacitor located on each drain region. , the unit cells are regularly arranged along both sides of one bit line, and one side is shifted by 2 pinches from the other side to form one unit cell row, and The basic unit cells constituting both unit cell rows are all connected to the one focus line.

[Industrial application field]

The present invention relates to a semiconductor memory device with an improved arrangement of bit line pairs and memory cells.

In recent years, dynamic random access memory (
dynamic random accesses
DRAM (DRAM) is becoming more highly integrated, and for example, 16 Mbit devices are about to be put into practical use.

In such a RAM, it is natural that power consumption increases significantly, and therefore, countermeasures are required to avoid many problems caused by this. For example, as mentioned above, the power consumption is large, and the amount of heat generated is large, and the conventional standard package does not last. One way to do this is to improve the circuit to suppress heat generation.

[Conventional technology]

To date, DRAM has made great progress in various aspects. For example, in the case of bit lines, the open bit line format has evolved into the noise-tolerant folded bit line format, and the charge storage capacitors in memory cells have evolved from the conventional three-dimensional stacked type. Starting from capacitors, dendritic multilayer stacked capacitors with a dramatically increased charge storage capacity have appeared, and further improvements to the dendritic multilayer stacked capacitors have been realized.

Figures 15 to 17 show DRAMs with ordinary three-dimensional stacked capacitors (if necessary, "Nikkei Electronics J 1985 6-3, pages 209 to 2
31), a plan view of the main parts, a cutaway side view of the main parts taken along the line X--X shown in FIG. 15, and a circuit diagram of the main parts, respectively, are shown.

In the figure, 1 is a p-type silicon semiconductor substrate, 2 is a field insulating film made of silicon dioxide (SiOz), 3 is a gate insulating film made of 5i02, 41 and 4! 5 is a gate electrode made of polycrystalline silicon which is a word line, 5 is an n+ type source region which is a bit line contact region, 6 is an n+ type drain region which is a storage electrode contact region of a charge storage capacitor, and 7 is made of SiO2. glabellar insulating membrane,
8 is a storage electrode made of polycrystalline silicon of the charge storage capacitor, 9 is a dielectric film made of SiO2 of the charge storage capacitor, 10 is a counter electrode (cell plate) made of polycrystalline silicon of the charge storage capacitor, and 11 is a storage electrode made of polycrystalline silicon of the charge storage capacitor. Phosphosilicate glass
ss:PSG), and numeral 12 indicates a bit line made of aluminum (AI).

In this memory cell, the charge stored in the charge storage capacitor is the stored information, so the larger the capacitance of the charge storage capacitor, the better the S/N.

However, as DRAMs become smaller, charge storage capacitors are also constrained to be smaller in area, and there are concerns about capacity shortages.

Therefore, a dendritic multilayer stacked capacitor, which dramatically increases the amount of charge storage, was introduced.

Figure 18 shows D with a dendritic multilayer stacked capacitor.
It represents a cutaway side view of the essential parts of RAM (see Japanese Patent Application No. 62-22063 if necessary), and the same symbols as those used in FIGS. 15 to 17 indicate the same parts or have the same meanings. shall have.

As is clear from the figure, the storage electrode 8, dielectric film 9, and counter electrode 10 in the charge storage capacitor each have dendritic protruding parts, so the capacitance is the same as the charge storage shown in FIG. It is clear that the increase is compared to the capacitor, and as long as this configuration is adopted,
For example, even in the case of a 16 Mbit DRAM that needs to be further miniaturized, it can be considered that there is no need to worry about the capacity.

By the way, as explained above, D shown in FIG.
Although RAM has sufficient capacity, problems remain in the manufacturing process due to the increased capacity. That is,
As the height of the charge storage capacitor has increased, the step has become larger, making it difficult to form the bit line 12. However, this problem has already been resolved.

FIG. 19 shows a cutaway side view of essential parts to explain the improved DRAM shown in FIG. 18, and symbols used in FIG. 18 indicate the same parts or have the same meanings. shall have it.

In the figure, 13 is an interlayer insulating film made of silicon nitride (Si3N4), 14 is an inter-glabellar insulating film made of SiO2, 15, 17 and 19 are storage electrodes made of polycrystalline silicon, and 20 is made of SiO2. The dielectric film 21 indicates a counter electrode (cell plate) made of polycrystalline silicon. By the way, bit! v112 is constructed by laminating polycrystalline silicon and tungsten silicide (WSiz).

In the DRAM seen here, since the bit line 12 is constructed of a refractory material, it is used early in the manufacturing process, particularly before forming the charge storage capacitor, thus
Since it can be formed without large steps, not only can the problem of DRAM shown in FIG. It is possible to increase the capacity.

[Problem to be solved by the invention]

As mentioned above, when miniaturizing DRAMs, it can be considered that the problem regarding the capacitance of the charge storage capacitor has been almost completely solved by adopting a dendritic multilayer stacked capacitor arranged below the bit line, but there are even more problems. It cannot be said that there are still problems in commercially putting a DRAM with a large capacity, for example, a 16 Mbit DRAM into practical use.

That is, as for the bit line, as mentioned above, the open bit line format is changed to the fallout type, which is advantageous for suppressing noise.
I explained that the technology has evolved into a bit line format, but by adopting the dendritic multilayer stacked capacitor, it is expected that even when miniaturized, it will be possible to secure sufficient capacity and obtain a good S/N ratio. At present, the open bit line format is preferable to the folded bit line format because it can reduce bit line capacitance, increase output signal voltage, and reduce power consumption. It has become.

However, the conventional open bit line format DRAM itself
In this case, we cannot expect much reduction in bit line capacitance, and it is not a good idea to eliminate the established process technology that has been cultivated over many years in the fallen bit line format. Linear DR
AM is considered necessary.

Let us now explain the parasitic capacitance in the bit line.

The capacitance of the charge storage capacitor explained with reference to FIGS. 15 to 19 is Ce, and the capacitance parasitic to the low bit line 12 is C6. , storage capacitor voltage Vl
, word line on voltage ■, when word line 41 is turned on, CILVO+ CCIILL-(Cst”
Cc*tt) V, and the output signal voltage largely depends on the ratio of the bit line capacitance to the charge storage capacitor capacitance. Therefore, it is preferable to make the bit line capacitance as small as possible.

In addition, in DRAM, in order to prevent information from disappearing, refreshing, that is, reading and rewriting operations are performed at regular intervals. During this rewriting, it is necessary to charge the bit line to the power supply voltage and write a high level ("H" level) to the charge storage capacitor, and this charging current occupies about 20% of the total power consumption. Since this charge/discharge current is naturally proportional to the bit line capacitance, it is desirable to reduce it in this respect as well.

For this reason, as the degree of integration of DRAM increases,
Power consumption increases exponentially, pushing the low-cost integrated circuit encapsulant plastic packaging to its thermal limits.

Now, how can we reduce the bit line capacitance? The simplest and surest way to do this is to shorten the length of the bit line.

Figure 20 shows the conventional fallen bit line format DR.
It shows a plan view of the main parts for explaining AM.

In the figure, 4. and 42 is a word line, 7A.

and 7Az+ are bit line contact windows, 7B1. and 7
B21 is a storage electrode contact window, 811 and 8□ are storage electrodes, 12. and 12z are bit lines, 23. .

and 23° indicate the active region, respectively. In the scale shown at the right end of the figure, a indicates the minimum line width, and b and C indicate alignment margins, which will be explained later.

It goes without saying that in the active region, the side where the bit line contact window is provided is the source region, and the side where the storage electrode contact window is provided is the drain region.

FIG. 21 is an explanatory diagram of the main parts to explain the correspondence between the sense amplifier (S/A), bit line, and memory cell in the DRAM shown in FIG. 20. The same symbols as those used indicate the same parts or have the same meaning.・In the figure, 12. and 12. 241 and 24□ are sense amplifiers, and MC is a memory cell. Note that two memory cells MC are combined to form a unit cell.

In this fallen bit line type DRAM, bit lines 12. ．． It goes without saying that 12□... is long and has a large parasitic capacitance.

By the way, the conventional folded bit line type DRAM described above has a problem not only in the large bit line capacitance but also in the area of the memory cell.

Let us now consider the DRAM sense amplifier pinch shown in FIGS. 20 and 21.

Figure 22 (A) and (B) and Figure 23 (A) and (
B) shows a cutaway side view of the main part of the DRAM for explaining the alignment margin.

In the figure, 31 is a silicon semiconductor substrate, 32 is 5i0
2, 33 is a first layer polycrystalline silicon electrode, and 34 is a second layer polycrystalline silicon electrode.

FIG. 22 explains the meaning of providing a positioning margin. In other words, as shown in (A), unless the polycrystalline silicon electrode 34 is formed large enough to allow for alignment, it will be misaligned with the electrode contact window during patterning, as shown in (B). If this occurs, the underlying silicon semiconductor substrate 31 will be etched.

FIG. 23 explains the meaning of providing a positioning margin C. That is, as shown in (A), the insulating film 32 is placed so that there is a positioning margin C between the electrode contact window for contacting the polycrystalline silicon electrode 34 with the silicon semiconductor substrate 31 and the polycrystalline silicon pole 33. If selective etching is not performed, a short circuit will occur between polycrystalline silicon electrode 33 and polycrystalline silicon electrode 34, as seen in (B).

From this, regarding the alignment margin, b<
It will be understood that c.

Now, the sense amplifier pitch for the DRAM shown in FIG. 20 is calculated by taking the alignment margin and the C1 minimum line width a.

In this case, it is sufficient to add all the scales shown at the right end of the figure, and the sense amplifier pitch=4a+4c.

If the sense amplifier pitch can be further reduced without affecting the function and characteristics of the DRAM, the area of the memory cell will naturally become smaller, which will lead to better results in terms of higher integration.

The present invention makes it possible to reduce power consumption by reducing the bit line capacitance without changing the conventional manufacturing process, and to reduce the memory cell area without affecting the characteristics and functions of DRAM. try to make it happen.

[Means to solve the problem]

FIG. 1 shows a sense amplifier (S) for explaining the present invention in detail.
/A) represents a main part explanatory diagram for explaining the correspondence between bit lines and memory cells, and the same symbols as those used in Fig. 21 indicate the same parts or have the same meaning. shall be.

As is clear from the figure, in the DRAM of the present invention,
The arrangement of unit cells is no different from that of the conventional fallen bit line type DRAM described with reference to FIG. That is, each unit cell in adjacent unit cell rows is arranged in a staggered manner with a two-pinch offset from each other.

Fig. 2 is an explanatory diagram of the main part, showing only the unit cell with bit lines and sense amplifiers omitted; symbols used in Fig. 1 indicate the same parts or have the same meanings. shall have it.

According to this figure, the arrangement relationship of units and cells can be clearly understood.

Now, the difference between the DRAM of the present invention and the conventional fallen bit line type DRAM is that, as mentioned above, one unit cell row shifted by two pinches is connected to one bit line. They are connected in an open bit line format.

In this way, the length of the bit line is A
It is clear that the parasitic capacitance is reduced accordingly.

Further, as will be explained in detail later based on an embodiment, the sense amplifier pitch can be made smaller compared to the fallen bit line type explained with reference to FIG. can do. In this case, of course, the functions and characteristics of the DRAM are not impaired.

In the present invention, the ability to reduce the sense amplifier pinch is largely due to the arrangement of the unit cells described above.

Incidentally, in the conventional open bit line format, unit cells are arranged in a straight line on one side of a single bit line, and the unit cells connected to each bit line are The pinch is the same, for example, there is no shift by % pitch.

As described above, in the semiconductor memory device of the present invention, one source region (for example, an n1 type source region) is a bit line contact region, and both sides of the source region intersect with a bit line (for example, bit line 12, etc.). A pair of gate electrodes (for example, gate electrodes 4., 4., etc.) are a pair of word lines extending in the direction, and a pair of drain regions (for example, n1 type drain regions 6) and charge storage capacitors (storage electrodes made of polycrystalline silicon films 15, 17, 19, for example) on the respective drain regions;
A pair of memory cells (for example, two memory cells MC
) as a basic unit, and the unit cells are arranged regularly along both sides of one bit line and with one side shifted by 2 pinches from the other side. Book unit/cell row and none/both units/
All of the basic unit cells constituting the cell string are connected to the one bit line.

[Effect]

By adopting the above method, although the unit cell arrangement is exactly the same as the conventional fallen bit line format, the bit line length is 2, so the parasitic capacitance is also A, and the output signal voltage is therefore The power consumption is improved by about 2 times, and the power consumption is reduced to about 2 times. Also, since one bit line corresponds to the unit cell column on the second side, the number of focus lines in the memory cell array is two, and therefore the bit line spacing is increased. There is no need to provide a convex part for bit line contact in the active region, and it is possible to increase the device isolation width to prevent short circuits between active regions, and to reduce the area of the active region to prevent Soft error resistance can be improved by reducing the probability of radiation incidence.

Here, the bit line contact convex portion provided in the active region will be explained in more detail. This is, for example, bit line contact window 7A1. shown in FIG. It is easy to understand by referring to the vicinity of the bit line contact window 7A.
This refers to the part of the active region that extends in the horizontal direction to correspond to bits 11 and 11.The reason for this configuration is that the bit line contact window? This is necessary because Az is arranged to be shifted upward in the plane of the paper compared to the storage electrode contact window 7B11.

〔Example〕

FIG. 3 shows a plan view of essential parts of an embodiment of the present invention, and the same symbols as those used in FIG. 20 indicate the same parts or have the same meanings.

In the figure, 7A, □ and 7Az□ are bit line contact windows, 7B+z and 7B2□ are storage electrode contact windows, 81□ and 8□2 are storage electrodes, 2331 and 2
341 indicates active regions, respectively.

Calculate the sense amplifier pitch in the DRAM shown in FIGS. 1 and 3.

This can be done in the same way as in the conventional example shown in FIGS. 20 and 21, which is to add all the scales shown at the right end of FIG. 3, and the sense amplifier pitch =
It becomes 43+2b+20. Therefore, Figures 20 and 21
It is clearly smaller than the conventional example shown in the figure, which has 4a+4c. Here, when calculated assuming that a=0.7 (μm) b=0.3 Cμm] c=0.45 Cμm], in the case of the present invention, 6.5
It will be about [%] smaller.

4 to 14 show cutaway side views of essential parts of a semiconductor memory device at key points in the process for explaining the case of manufacturing an embodiment of the present invention, and the following will refer to these figures. explain. Note that the same symbols as those used in FIGS. 1 to 3 and FIGS. 15 to 23 indicate the same parts or have the same meanings. Furthermore, in FIGS. 4 to 14, approximately one memory cell in FIG. 3 is cut in the X direction.

Referring to FIG. 4, a field insulating film 2 of 5 Ioz is formed on a p-type silicon semiconductor substrate 1 by applying a selective thermal oxidation method using an oxidation-resistant mask such as a 11S i 3 N4 film.

Next, the oxidation-resistant mask is removed to expose the active region in the p-type silicon semiconductor substrate 1.

Next, by applying the same thermal oxidation method, S i
A gate insulating film 3 made of O2 is formed.

Next, chemical vapor deposition (chemical vapor deposition) is performed.
A polycrystalline silicon film is formed by applying a deposition (CVD) method.

Next, resist processing and reactive ion etching (rea
By applying the active ion etching (RIE) method, the polycrystalline silicon film is patterned to form gate electrodes 41 and 4□, which are word lines.
etc. to form.

Next, by applying an ion implantation method, the gate electrode 4. and 4□ as a mask, n-type impurities are introduced, and heat treatment for activation is performed to form an n++ source region 5, which is a bit line contact region, and an n+ type drain region 6, which is a storage electrode contact region.

Refer to FIG. 5 (by applying the 21CVD method, a glabellar insulating film 7 made of S i 02 is formed. Note that this interlayer insulating film 7
It is also possible to adopt S i 3 N 4.

Next, by applying a resist process in a normal photolithography technique and an RIE method, the glabellar insulating film 7 is selectively etched to form a bit line contact window 7A.

Referring to FIG. 6, a polycrystalline silicon film is formed by applying the +31CVD method.

Next, a tungsten (W) film is formed by applying the CVD method.

Next, the polycrystalline silicon film and W film are patterned to form the bit line 12 by applying a resist process and RIB method in a normal photolithography technique.

Next, heat treatment is performed to cause the polycrystalline silicon in the bit vA12 to react with W to form tungsten silicide (WSi2).

Refer to FIG. 7 (by applying the 41CVD method, an interlayer insulating film 13 made of 5i3N4 is formed.

Refer to FIG. 8<51By applying the CVD method, the 5io2 film 14
, impurity-containing polycrystalline silicon film 15.5i02 film 16,
An impurity-containing polycrystalline silicon film 17.5i02 film 18 is grown in order.

See Figure 9 (6) By applying the resist process and RIE method in normal photolithography technology, 5i
Selective etching of the O2 film 18, etc. is performed to remove n from the surface.
A storage electrode contact window 7B reaching the surface of the + type drain region 6 is formed.

Refer to FIG. 10 (71) By applying the CVD method, an impurity-containing polycrystalline silicon film 19 is grown.

See Figure 11 (8) By applying the resist process and RIE method in normal photolithography technology, the impurity-containing polycrystalline silicon film 19.5i021111
B, impurity-containing polycrystalline silicon film 17, Si02 film 1
6. Patterning the impurity-containing polycrystalline silicon film 15 to form a storage electrode pattern.

See FIG. 12 (9) The Si02 films 18 and 16 are removed by applying a dipping method using hydronic acid as an enchantment.

Through this process, the dendritic multilayer storage electrode was completed.

See FIG. 13 αω By applying a thermal oxidation method, SiO2 is deposited on each surface of the impurity-containing polycrystalline silicon film 19, 17, and 15.
A dielectric film 20 is formed.

Referring to FIG. 14, by applying the αω CVD method, a counter electrode (cell plate) 21 made of impurity-containing polycrystalline silicon is formed.

(2) Thereafter, by applying ordinary techniques, a passivation film, bonding pads, etc. are formed and completed.

〔Effect of the invention〕

In the semiconductor memory device according to the present invention, the unit cells are arranged along both sides of one bit line and are regularly arranged with one side shifted by two bits from the other side. The configuration is such that each of the unit cells constituting one unit cell column and one unit cell column and both unit cell columns are all connected to the one bit line.

By adopting the above configuration, although the unit cell arrangement is exactly the same as the conventional folde soto bit bi format, the length of the bi node line is 2, so the parasitic capacitance is also reduced to A.
Therefore, the output signal voltage is improved to about twice, and the power consumption is reduced to about 2 times. Also, since one bit line corresponds to the unit cell column on the second side, the number of bit lines in the memory cell array is two, and therefore the bit line spacing is increased. There is no need to provide a convex part for bit line contact in the active region, and it is possible to increase the device isolation width to prevent short circuits between active regions, and to reduce the area of the active region to prevent By reducing the probability of radiation incidence, many effects can be achieved, such as improving soft error resistance.

[Brief explanation of the drawing]

FIG. 1 is an explanatory diagram of the main parts of a semiconductor memory device to explain the present invention in detail, FIG. 2 is an explanatory diagram of the main parts to explain the arrangement of unit cells shown in FIG. 1, and FIG. 1 is a plan view of a main part of an embodiment of the present invention, and FIGS. 4 to 14 are cutaway side views of a main part of a semiconductor memory device at important points in the process for explaining the case of manufacturing an embodiment of the present invention. 15 is a plan view of the main part for explaining a conventional semiconductor memory device, FIG. 16 is a cutaway side view of the main part taken along line XX seen in FIG. 15, and FIG. Main part circuit diagram of a semiconductor memory device, Part 1
FIG. 8 is a cutaway side view of essential parts of a semiconductor memory device having a dendritic multilayer stacked capacitor, FIG. 19 is a cutaway side view of essential parts of an improved semiconductor memory device, and FIG. 20 is a collapsed bit line type semiconductor memory. 21 is a plan view of the main parts for explaining the device, and FIG. 22 is an explanatory diagram of the main parts for explaining the arrangement of various parts in the semiconductor memory device shown in FIG. ) and Figure 23 (A) and (B
) respectively show cutaway side views of essential parts of the semiconductor memory device for explaining the alignment margin. In the figure, numeral 1 is a p-type silicon semiconductor substrate, 2 is Si
A field insulating film made of O2, 3 a gate insulating film made of SiO2, 4I and 4□ gate electrodes made of polycrystalline silicon which are word lines, 5 an n++ source region which is a bit line contact region, 6 a charge storage capacitor. The n+ type drain region 7, which is the storage electrode contact MB region, is a glabella insulating film made of S i Q 2, 8 is a storage electrode made of polycrystalline silicon of a charge storage capacitor, 9
1o is a counter electrode (cell plate) made of polycrystalline silicon of the charge storage capacitor, 11 is an insulating film between the eyebrows made of PSG, and 12 is AI! Alternatively, bit lines each consisting of W S i 2 are shown. C M O-00-00-0 0-OM 0-0 M M O-0 Fig. 5 Fig. 6 Fig. 7 Fig. 8 Fig. 11 Fig. 12 Fig. 15 Fig. 16 Fig. 16 ) (B) 22nd
Figure (A)' (B) Figure 23

Claims (1)

[Scope of Claims] One source region that is a bit line contact region, and a pair of word lines that extend on both sides of the source region in a direction intersecting the bit lines, and a channel region that connects the source region. A unit cell whose basic unit is a pair of memory cells each consisting of a pair of drain regions, which are storage electrode contact regions facing each other, and a charge storage capacitor disposed on each drain region. They are arranged regularly along both sides of the bit line of the book and are shifted by 1/2 bit from one side to the other to form one unit cell row and both unit cell rows. A semiconductor memory device characterized in that all of the unit cells of the basic unit are connected to the one bit line.