KR910017640A - Highly Integrated Memory Cell and Core Array Structures - Google Patents

Highly Integrated Memory Cell and Core Array Structures Download PDF

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Publication number
KR910017640A
KR910017640A KR1019900004190A KR900004190A KR910017640A KR 910017640 A KR910017640 A KR 910017640A KR 1019900004190 A KR1019900004190 A KR 1019900004190A KR 900004190 A KR900004190 A KR 900004190A KR 910017640 A KR910017640 A KR 910017640A
Authority
KR
South Korea
Prior art keywords
memory cell
highly integrated
integrated memory
core array
array structures
Prior art date
Application number
KR1019900004190A
Other languages
Korean (ko)
Other versions
KR920007358B1 (en
Inventor
안승한
이영종
정원화
Original Assignee
문정환
금성일렉트론 주식회사
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 문정환, 금성일렉트론 주식회사 filed Critical 문정환
Priority to KR1019900004190A priority Critical patent/KR920007358B1/en
Priority to FR9103522A priority patent/FR2660475A1/en
Priority to NL9100536A priority patent/NL9100536A/en
Priority to DE4110155A priority patent/DE4110155A1/en
Priority to GB9106576A priority patent/GB2242568A/en
Priority to JP3063190A priority patent/JPH0774266A/en
Publication of KR910017640A publication Critical patent/KR910017640A/en
Application granted granted Critical
Publication of KR920007358B1 publication Critical patent/KR920007358B1/en

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Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/18—Bit line organisation; Bit line lay-out
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G11C11/4063—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
    • G11C11/407—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing for memory cells of the field-effect type
    • G11C11/409—Read-write [R-W] circuits 
    • G11C11/4097—Bit-line organisation, e.g. bit-line layout, folded bit lines
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C5/00—Details of stores covered by group G11C11/00
    • G11C5/06—Arrangements for interconnecting storage elements electrically, e.g. by wiring
    • G11C5/063—Voltage and signal distribution in integrated semi-conductor memory access lines, e.g. word-line, bit-line, cross-over resistance, propagation delay
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H01L23/5222—Capacitive arrangements or effects of, or between wiring layers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H01L23/528—Geometry or layout of the interconnection structure
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Power Engineering (AREA)
  • Geometry (AREA)
  • Semiconductor Memories (AREA)
  • Dram (AREA)
  • Static Random-Access Memory (AREA)

Abstract

내용 없음No content

Description

고집적 메모리 셀 및 코어 어레이 구조Highly Integrated Memory Cell and Core Array Structures

본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음Since this is an open matter, no full text was included.

제 3도는 본 발명에 따른 셀의 구조, 제 5도는 본 발명에 따른 셀구조의 다른예.3 is a structure of a cell according to the present invention, Figure 5 is another example of a cell structure according to the present invention.

Claims (1)

2개의 인접된 셀사이에 비트선을 두는 수정된 오픈 비트선으로 어레이하여, 하나의 비트선을 중심으로 상하 또는 좌우로 셀이 대칭을 이루고 비트선에 어레이되고, 웨이블 구조로 구성하여서 이루어진 것을 특징으로 하는 고집적 메모리 셀 및 메모리 어레이 구조.Arrayed by a modified open bit line having a bit line between two adjacent cells, the cells being symmetrically arranged up and down or left and right around one bit line, arrayed in the bit line, and configured in a wave structure A highly integrated memory cell and memory array structure. ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.※ Note: The disclosure is based on the initial application.
KR1019900004190A 1990-03-28 1990-03-28 Vlsi cell and core array KR920007358B1 (en)

Priority Applications (6)

Application Number Priority Date Filing Date Title
KR1019900004190A KR920007358B1 (en) 1990-03-28 1990-03-28 Vlsi cell and core array
FR9103522A FR2660475A1 (en) 1990-03-28 1991-03-22 Semiconductor memory device
NL9100536A NL9100536A (en) 1990-03-28 1991-03-26 SEMICONDUCTOR MEMORY DEVICES.
DE4110155A DE4110155A1 (en) 1990-03-28 1991-03-27 SEMICONDUCTOR MEMORY COMPONENT
GB9106576A GB2242568A (en) 1990-03-28 1991-03-27 Semiconductor memory devices
JP3063190A JPH0774266A (en) 1990-03-28 1991-03-27 Semiconductor memory device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
KR1019900004190A KR920007358B1 (en) 1990-03-28 1990-03-28 Vlsi cell and core array

Publications (2)

Publication Number Publication Date
KR910017640A true KR910017640A (en) 1991-11-05
KR920007358B1 KR920007358B1 (en) 1992-08-31

Family

ID=19297455

Family Applications (1)

Application Number Title Priority Date Filing Date
KR1019900004190A KR920007358B1 (en) 1990-03-28 1990-03-28 Vlsi cell and core array

Country Status (6)

Country Link
JP (1) JPH0774266A (en)
KR (1) KR920007358B1 (en)
DE (1) DE4110155A1 (en)
FR (1) FR2660475A1 (en)
GB (1) GB2242568A (en)
NL (1) NL9100536A (en)

Families Citing this family (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2007013011A (en) * 2005-07-01 2007-01-18 Seiko Epson Corp Ferroelectric memory device and driving ic (integrated circuit) for indication
US11877441B2 (en) 2021-03-04 2024-01-16 Changxin Memory Technologies, Inc. Memory and fabricating method thereof
CN113053897B (en) * 2021-03-04 2022-06-17 长鑫存储技术有限公司 Memory and preparation method thereof

Family Cites Families (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE2743619A1 (en) * 1977-09-28 1979-03-29 Siemens Ag SEMICONDUCTOR STORAGE ELEMENT AND METHOD FOR MANUFACTURING IT
US4319342A (en) * 1979-12-26 1982-03-09 International Business Machines Corporation One device field effect transistor (FET) AC stable random access memory (RAM) array
JPS57208691A (en) * 1981-06-15 1982-12-21 Mitsubishi Electric Corp Semiconductor memory
JP2682021B2 (en) * 1988-06-29 1997-11-26 富士通株式会社 Semiconductor memory device
JPH0276258A (en) * 1988-09-13 1990-03-15 Fujitsu Ltd Semiconductor memory device
JP2681285B2 (en) * 1988-09-19 1997-11-26 富士通株式会社 Semiconductor memory device
JP2974252B2 (en) * 1989-08-19 1999-11-10 富士通株式会社 Semiconductor storage device

Also Published As

Publication number Publication date
DE4110155A1 (en) 1991-10-02
GB2242568A (en) 1991-10-02
GB9106576D0 (en) 1991-05-15
NL9100536A (en) 1991-10-16
JPH0774266A (en) 1995-03-17
KR920007358B1 (en) 1992-08-31
FR2660475A1 (en) 1991-10-04

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