KR940022555A - Low Power Consumption Bit Line Configuration Circuit - Google Patents

Low Power Consumption Bit Line Configuration Circuit Download PDF

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Publication number
KR940022555A
KR940022555A KR1019930003522A KR930003522A KR940022555A KR 940022555 A KR940022555 A KR 940022555A KR 1019930003522 A KR1019930003522 A KR 1019930003522A KR 930003522 A KR930003522 A KR 930003522A KR 940022555 A KR940022555 A KR 940022555A
Authority
KR
South Korea
Prior art keywords
bit line
configuration circuit
line configuration
power consumption
low power
Prior art date
Application number
KR1019930003522A
Other languages
Korean (ko)
Other versions
KR950009078B1 (en
Inventor
김태형
곽덕영
안진홍
Original Assignee
문정환
금성일렉트론 주식회사
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 문정환, 금성일렉트론 주식회사 filed Critical 문정환
Priority to KR1019930003522A priority Critical patent/KR950009078B1/en
Publication of KR940022555A publication Critical patent/KR940022555A/en
Application granted granted Critical
Publication of KR950009078B1 publication Critical patent/KR950009078B1/en

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    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/18—Bit line organisation; Bit line lay-out
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C5/00—Details of stores covered by group G11C11/00
    • G11C5/06—Arrangements for interconnecting storage elements electrically, e.g. by wiring

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  • Dram (AREA)

Abstract

본 발명은 메모리의 비트선 구성에 관한 것으로,종래 기술은 비트선 구성시 제1물질로만 구성하여 한정된 면적안에 레이아웃하였을 때 비트선당 연결된 메모리 셀이 많아서 비트선 캐피시터가 증가하게 되며 따라서 칩이 동작할 때 전류가 많이 흐르게 된다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a bit line configuration of a memory. In the related art, when a bit line is configured with only a first material and laid out in a limited area, the number of connected memory cells per bit line increases, thereby increasing the bit line capacitor. When the current flows a lot.

이에 따라 본 발명은 상기와 같은 종래의 비트선 구성회로에 따르는 결함을 해결하기 위하여, 비트선의 물질 구성을 두가지로 사용하여 비트선당 연결된 메모리셀의 숫자를 비트선 한 물질로만 구성한 것에 비하여 반으로 줄이고 두 물질을 입체적으로 배선하여 레이아웃 면적에 손실이 없도록 하는 비트선 구성회로를 제공하는데 있다.Accordingly, in order to solve the defect caused by the conventional bit line configuration circuit, the present invention reduces the number of memory cells connected per bit line by half using only one bit line material by using two material configurations of the bit line. The present invention provides a bit line configuration circuit in which two materials are interconnected in three dimensions so that there is no loss in the layout area.

Description

저전력 소모형 비트선 구성회로Low Power Consumption Bit Line Configuration Circuit

본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음Since this is an open matter, no full text was included.

제 2도는 본 발명의 저전력 소모형 비트선 구성회로도.2 is a low power consumption bit line configuration circuit diagram of the present invention.

Claims (1)

메모리 셀 어레이는 워드선과 워드선의 수직방향의 형태로 교차되는 비트선이 있고 상기 비트선은 제1비트선 물질에 의해서만 형성된 제1비트선이 있고 그 비트선의 연장선에 제1비트선 물질에 의해 형성된 제2비트선이 형성되고 그 제1비트선 또는 제2비트선중 하나는 제2비트선 물질과 연결되어 제1비트선 선택 스위치와 연결되며, 제1비트선 물질에 의해서만 구성된 비트선도 제2비트선 선택 스위치와 연결되고 제1비트선 선택 스위치의 비트선과 연결되지 않은 노드와 제2비트선 선택 스위치의 비트선과 연결되지 않은 노드는 서로 같이 연결되어 센스 증폭기(10,10′,11,11′,12,12′)의 입출력에 연결되며, 제2비트선 물질로 구성된 비트선은 제1비트선 물질로 구성된 비트선 4개당 2개씩 형성되는 것을 특징으로 하는 저전력 소모형 비트선 구성회로.The memory cell array has a bit line intersecting in the form of a word line and a word line in a vertical direction, the bit line having a first bit line formed only by a first bit line material and formed by a first bit line material on an extension line of the bit line. A second bit line is formed and one of the first bit line or one of the second bit lines is connected to the second bit line material and connected to the first bit line selection switch, and the bit line formed only by the first bit line material is also second. A node connected to the bit line selection switch and not connected to the bit line of the first bit line selection switch and a node not connected to the bit line of the second bit line selection switch are connected together to sense amplifiers (10, 10 ', 11, 11). And a bit line formed of a second bit line material is formed in each of four bit lines made of a first bit line material. ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.※ Note: The disclosure is based on the initial application.
KR1019930003522A 1993-03-09 1993-03-09 Low power consumption type bit line driving circuit KR950009078B1 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
KR1019930003522A KR950009078B1 (en) 1993-03-09 1993-03-09 Low power consumption type bit line driving circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
KR1019930003522A KR950009078B1 (en) 1993-03-09 1993-03-09 Low power consumption type bit line driving circuit

Publications (2)

Publication Number Publication Date
KR940022555A true KR940022555A (en) 1994-10-21
KR950009078B1 KR950009078B1 (en) 1995-08-14

Family

ID=19351865

Family Applications (1)

Application Number Title Priority Date Filing Date
KR1019930003522A KR950009078B1 (en) 1993-03-09 1993-03-09 Low power consumption type bit line driving circuit

Country Status (1)

Country Link
KR (1) KR950009078B1 (en)

Also Published As

Publication number Publication date
KR950009078B1 (en) 1995-08-14

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