KR920022301A - Semiconductor memory - Google Patents

Semiconductor memory Download PDF

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Publication number
KR920022301A
KR920022301A KR1019910008735A KR910008735A KR920022301A KR 920022301 A KR920022301 A KR 920022301A KR 1019910008735 A KR1019910008735 A KR 1019910008735A KR 910008735 A KR910008735 A KR 910008735A KR 920022301 A KR920022301 A KR 920022301A
Authority
KR
South Korea
Prior art keywords
semiconductor memory
memory device
switching means
bit line
semiconductor
Prior art date
Application number
KR1019910008735A
Other languages
Korean (ko)
Inventor
김창래
Original Assignee
김광호
삼성전자 주식회사
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 김광호, 삼성전자 주식회사 filed Critical 김광호
Priority to KR1019910008735A priority Critical patent/KR920022301A/en
Priority to GB9121767A priority patent/GB2256297A/en
Priority to ITMI912808A priority patent/IT1251623B/en
Priority to NL9101772A priority patent/NL9101772A/en
Priority to FR9113207A priority patent/FR2677162A1/en
Priority to DE4135686A priority patent/DE4135686A1/en
Priority to CN92100194A priority patent/CN1067325A/en
Publication of KR920022301A publication Critical patent/KR920022301A/en

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Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/41—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming static cells with positive feedback, i.e. cells not needing refreshing or charge regeneration, e.g. bistable multivibrator or Schmitt trigger
    • G11C11/413—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing, timing or power reduction
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/12—Bit line control circuits, e.g. drivers, boosters, pull-up circuits, pull-down circuits, precharging circuits, equalising circuits, for bit lines
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/41—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming static cells with positive feedback, i.e. cells not needing refreshing or charge regeneration, e.g. bistable multivibrator or Schmitt trigger
    • G11C11/413—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing, timing or power reduction
    • G11C11/417—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing, timing or power reduction for memory cells of the field-effect type
    • G11C11/419—Read-write [R-W] circuits

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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Computer Hardware Design (AREA)
  • Static Random-Access Memory (AREA)
  • Semiconductor Memories (AREA)
  • Dram (AREA)

Abstract

내용 없음.No content.

Description

반도체 기억장치Semiconductor memory

본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음Since this is an open matter, no full text was included.

제1도는 이 발명의 회로가 포함된 반도체 기억장치의 메모리 블록에 대한 회로 구성도,1 is a circuit configuration diagram of a memory block of a semiconductor memory device including the circuit of the present invention;

제2도는 제2실시예로서의 제1도의 관련된 회로 구성도.2 is a related circuit diagram of FIG. 1 as a second embodiment.

Claims (12)

메모리 셀, 워드라인 및 제1 및 제2의 한쌍의 비트라인을 갖고 비트라인의 프리챠징 수단이 구비된 반도체 장치에 있어서, 제1비트라인측의 프리챠지 수단 신호를 받고 소오스가 전원에 연결되고 드레인이 제2비트라인축에 연결된 누설전류 보상 또는 오프 전류 차단을 위한 제1스위칭 수단과, 제2비트라인측의 프리챠지 수단 신호를 받고 소오스가 저원에 연결되고 드레인이 제1비트라인측에 연결된 상기 기능의 제2스위칭 수단을 구비하여 구성된 것을 특징으로 하는 반도체 기억장치.A semiconductor device having a memory cell, a word line, and a pair of first and second bit lines and provided with precharging means for the bit lines, wherein the source is connected to a power source in response to a precharge means signal on the first bit line side; A first switching means for leakage current compensation or an off current blocking in which the drain is connected to the second bit line shaft, a precharge means signal on the second bit line side, a source is connected to the source, and the drain is connected to the first bit line side. And a second switching means of said function connected to said semiconductor memory device. 제1항에 있어서, 상기 제1 및 제2스위칭 수단을 위한 트랜지스터 타입은 프리챠지용 트랜지스터와 동일 타입이며 워드라인과 메모리 셀 간 연결된 트랜지스터와는 상기 타입과 다른 타입의 트랜지스터인 것을 특징으로 하는 반도체 기억장치.2. The semiconductor device according to claim 1, wherein the transistor type for the first and second switching means is of the same type as the precharge transistor and is of a different type from the transistor connected between the word line and the memory cell. Memory. 제1항에 있어서, 상기 회로 적용된 반도체 기억장치는 한쌍의 비트라인간에 이퀄라이징 수단이 포함되어 있는 반도체 기억장치인 것을 특징으로 하는 반도체 기억장치.2. The semiconductor memory device according to claim 1, wherein the circuit-applied semiconductor memory device is a semiconductor memory device including equalizing means between a pair of bit lines. 제1항에 있어서, 상기 회로 적용된 반도체 기억장치의 프리챠징 수단에 공급되는 제어신호는 ATD회로로부터 공급됨을 특징으로 하는 반도체 기억장치.The semiconductor memory device according to claim 1, wherein a control signal supplied to the precharging means of the circuit-applied semiconductor memory device is supplied from an ATD circuit. 제1항에 있어서, 상기 제1 및 제2스위칭 수단은 IGFET인 것을 특징으로 하는 반도체 기억장치.The semiconductor memory device according to claim 1, wherein said first and second switching means are IGFETs. 메모리 셀, 워드라인 및 제1 및 제2의 한쌍의 비트라인을 갖고 비트라인의 프리챠징 수단이 구비된 반도체 장치에 있어서, 제1비트라인측의 프리챠지 수단신호를 받고 드레인이 제2비트라인측에 연결된 누설전류 보상 또는 오프 전류 차단을 위한 제1스위칭 수단과, 제2비트라인측의 프리챠지 수단신호를 받고 드레인이 제1비트 라인측에 연결된 상기 기능의 제2스위칭 수단과, 상기 제1 및 제2스위칭수단의 소오스에 공히 연결되어 전원공급을 행하는 제3의 스위칭수단으로 연결 구성됨을 특징으로 하는 반도체 기억장치.A semiconductor device having a memory cell, a word line, and a pair of first and second bit lines and having precharging means for bit lines, the semiconductor device comprising: receiving a precharge means signal on the first bit line side, and draining the second bit line; A first switching means for leakage current compensation or an off current blocking connected to the side; a second switching means of the function receiving a precharge means signal on the second bit line side and a drain connected to the first bit line side; And a third switching means connected to the source of the first and second switching means to supply power. 제6항에 있어서, 상기 제1 및 제2의 스위칭 수단을 위한 트랜지스터 타입은 프리챠지용 트랜지스터와 제3의 트랜지스터 타입과 서로 다른 타입이도록 구성됨을 특징으로 하는 반도체 기억장치.7. The semiconductor memory device according to claim 6, wherein the transistor type for the first and second switching means is configured to be different from the precharge transistor and the third transistor type. 제6항에 있어서, 상기 회로 적용된 반도체 기억장치는 한쌍의 비트라인간에 데이타 이퀄라이징 수단이 또한 포함되어 있는 반도체 기억장치인 것을 특징으로 하는 반도체 기억장치.7. The semiconductor memory device according to claim 6, wherein the circuit-applied semiconductor memory device is a semiconductor memory device further including data equalizing means between a pair of bit lines. 제6항에 있어서, 상기 회로 적용된 반도체 기억장치는 프리챠징 수단에 공급되는 제어신호는 ATD회로로부터 공급됨을 특징으로 하는 반도체 기억장치.7. The semiconductor memory device according to claim 6, wherein the circuit-applied semiconductor memory device is supplied with a control signal supplied to a precharging means from an ATD circuit. 제6항에 있어서, 상기 제1 및 제3스위칭 수단은 IGFET인 것을 특징으로 하는 반도체 기억장치.7. The semiconductor memory device according to claim 6, wherein said first and third switching means are IGFETs. 제6항에 있어서, 상기 프래챠징 수단의 전압레벨은 전원전압과 사용된 트랜지스터의 문턱전압과의 차인 것을 특징으로 하는 반도체 기억장치.7. The semiconductor memory device according to claim 6, wherein the voltage level of the framing means is a difference between a power supply voltage and a threshold voltage of a transistor used. 제1항 또는 제6항중 어느 1항에 있어서, 상기 메모리 셀을 포함하는 메모리 블록은 단일 워드라인상에 다수 연결되도록 배치됨을 특징으로 하는 반도체 기억장치.7. The semiconductor memory device according to any one of claims 1 to 6, wherein a plurality of memory blocks including the memory cells are arranged to be connected on a single word line. ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.※ Note: The disclosure is based on the initial application.
KR1019910008735A 1991-05-28 1991-05-28 Semiconductor memory KR920022301A (en)

Priority Applications (7)

Application Number Priority Date Filing Date Title
KR1019910008735A KR920022301A (en) 1991-05-28 1991-05-28 Semiconductor memory
GB9121767A GB2256297A (en) 1991-05-28 1991-10-14 Semi-conductor memory device
ITMI912808A IT1251623B (en) 1991-05-28 1991-10-23 SEMICONDUCTOR MEMORY DEVICE
NL9101772A NL9101772A (en) 1991-05-28 1991-10-23 SEMI-CONDUCTIVE MEMORY DEVICE.
FR9113207A FR2677162A1 (en) 1991-05-28 1991-10-25 Semiconductor memory device
DE4135686A DE4135686A1 (en) 1991-05-28 1991-10-25 SEMICONDUCTOR MEMORY ARRANGEMENT
CN92100194A CN1067325A (en) 1991-05-28 1992-01-10 Semiconductor memory

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
KR1019910008735A KR920022301A (en) 1991-05-28 1991-05-28 Semiconductor memory

Publications (1)

Publication Number Publication Date
KR920022301A true KR920022301A (en) 1992-12-19

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Application Number Title Priority Date Filing Date
KR1019910008735A KR920022301A (en) 1991-05-28 1991-05-28 Semiconductor memory

Country Status (7)

Country Link
KR (1) KR920022301A (en)
CN (1) CN1067325A (en)
DE (1) DE4135686A1 (en)
FR (1) FR2677162A1 (en)
GB (1) GB2256297A (en)
IT (1) IT1251623B (en)
NL (1) NL9101772A (en)

Cited By (2)

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KR100445353B1 (en) * 2000-10-05 2004-08-25 엔이씨 일렉트로닉스 가부시키가이샤 Semiconductor integrated circuit
KR100732390B1 (en) * 2001-12-29 2007-06-27 매그나칩 반도체 유한회사 current mirror type circuit for compensating leakage current

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US5828610A (en) * 1997-03-31 1998-10-27 Seiko Epson Corporation Low power memory including selective precharge circuit
US6608786B2 (en) * 2001-03-30 2003-08-19 Intel Corporation Apparatus and method for a memory storage cell leakage cancellation scheme
JP4251815B2 (en) * 2002-04-04 2009-04-08 株式会社ルネサステクノロジ Semiconductor memory device
JP3904499B2 (en) * 2002-09-25 2007-04-11 松下電器産業株式会社 Semiconductor memory device
JP2004152092A (en) * 2002-10-31 2004-05-27 Matsushita Electric Ind Co Ltd Voltage source circuit
DE10255102B3 (en) * 2002-11-26 2004-04-29 Infineon Technologies Ag Semiconducting memory cell, especially SRAM cell, has arrangement for adapting leakage current that causes total leakage current independent of memory state, especially in the non-selected state
US6967875B2 (en) * 2003-04-21 2005-11-22 United Microelectronics Corp. Static random access memory system with compensating-circuit for bitline leakage
CN106558329A (en) * 2015-09-30 2017-04-05 展讯通信（上海）有限公司 A kind of difference reading circuit of single-ended memory and method
CN106875963B (en) * 2017-02-21 2019-05-14 中国科学院上海微系统与信息技术研究所 A kind of three-dimensional storage reading circuit and reading method

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Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100445353B1 (en) * 2000-10-05 2004-08-25 엔이씨 일렉트로닉스 가부시키가이샤 Semiconductor integrated circuit
KR100732390B1 (en) * 2001-12-29 2007-06-27 매그나칩 반도체 유한회사 current mirror type circuit for compensating leakage current

Also Published As

Publication number Publication date
IT1251623B (en) 1995-05-17
CN1067325A (en) 1992-12-23
ITMI912808A0 (en) 1991-10-23
ITMI912808A1 (en) 1993-04-23
DE4135686A1 (en) 1992-12-03
GB9121767D0 (en) 1991-11-27
NL9101772A (en) 1992-12-16
GB2256297A (en) 1992-12-02
FR2677162A1 (en) 1992-12-04

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