GB2242568A - Semiconductor memory devices - Google Patents
Semiconductor memory devices Download PDFInfo
- Publication number
- GB2242568A GB2242568A GB9106576A GB9106576A GB2242568A GB 2242568 A GB2242568 A GB 2242568A GB 9106576 A GB9106576 A GB 9106576A GB 9106576 A GB9106576 A GB 9106576A GB 2242568 A GB2242568 A GB 2242568A
- Authority
- GB
- United Kingdom
- Prior art keywords
- bit line
- semiconductor memory
- memory devices
- contacts
- memory device
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Withdrawn
Links
Classifications
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
- G11C7/18—Bit line organisation; Bit line lay-out
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
- G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
- G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
- G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
- G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
- G11C11/4063—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
- G11C11/407—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing for memory cells of the field-effect type
- G11C11/409—Read-write [R-W] circuits
- G11C11/4097—Bit-line organisation, e.g. bit-line layout, folded bit lines
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C5/00—Details of stores covered by group G11C11/00
- G11C5/06—Arrangements for interconnecting storage elements electrically, e.g. by wiring
- G11C5/063—Voltage and signal distribution in integrated semi-conductor memory access lines, e.g. word-line, bit-line, cross-over resistance, propagation delay
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
- H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
- H01L23/5222—Capacitive arrangements or effects of, or between wiring layers
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
- H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
- H01L23/528—Geometry or layout of the interconnection structure
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/0001—Technical content checked by a classifier
- H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Computer Hardware Design (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Power Engineering (AREA)
- Geometry (AREA)
- Semiconductor Memories (AREA)
- Dram (AREA)
- Static Random-Access Memory (AREA)
Abstract
A semiconductor memory device having bit line contacts (11) provided in a pair of bit lines in a folded bit line structure, comprises a zigzag shaped bit line (BL) linking the bit line contacts of an adjacent pair of rows. The pitch between the bit lines is about twice as compared with the semiconductor memory devices having the conventional open bit line structure, thus the coupling capacitance produced by adjacent bit line is reduced. Therefore, the coupling noise in a high density memory of 16 mega class and over is reduced remarkably. <IMAGE>
Description
SEMICONDUCTOR MEMORY DEVICES
This invention relates to semiconductor memory devices applicable to high density memory of 16 mega class and over.
Semiconductor memory devices have a folded bit line structure or an open bit line structure in the prior art.
Fig. 1 is a layout of conventional semiconductor memory devices having the folded bit line structure, including adjacent pairs of bit lines BL and BL running parallel to each other. The bit line BL having the shape of a straight line includes bit line contacts 1 having buried contacts 2a and 2b respectively on either side.
Also, the bit line BL has bit line contacts 3 provided with buried contact 4a and 4b respectively on either side and positioned adjacent to the bit line BL between the buried contacts 2a and 2b.
Fig. 2 is a circuit representing the semiconductor memory devices of Fig. 1. Among wbrd lines
WL, if one word line WL is selected, a selected cell in cell array 5 connected to the word line WL is turned on and a cell connected to an adjacent corresponding word line WL is turned off. A reference voltage is applied to the bit line BL, and the electric potential is changed compared with the reference voltage, due to an electric charge flowing from the selected cell. The pairs of bit lines BL and BL are connected to sense amplifiers SA so that a difference in potential is sensed.
Fig. 3 is a layout of conventional semiconductor memory devices having open bit line structure, including adjacent bit lines BL running parallel to each other. The bit line BL having a shape of a straight line includes bit line contacts 6 having buried contacts 7a and 7b respectively on either side. The adjacent bit lines BL have the same pattern to each other.
Fig. 4 is a circuit representing the semiconductor memory devices of Fig. 3. Sense amplifiers
SA are provided between cell arrays 8a and 8b and sensed in accordance with bit line BL in the cell array 8a and bit line BL in the cell array 8b.
Semiconductor memory devices having folded bit line structure endure external noise well and make arrangement of the sense amplifiers easy. However, the pitch between bit lines narrows and the coupling capacitance increases more and more with higher density.
Also, semiconductor memory devices having open bit line structure are applicable to memory of 4 mega class, but when applied to high density memory of 16 mega class and over the arrangement of the sense amplifiers becomes hard with decrease in the pitch between memory cells. Moreover, the load to be coupled increases and the difference in potential for sensing decreases with narrower pitch between the bit lines, so that sensing time becomes longer.
The invention provides a semiconductor memory device having bit line contacts in a pair of lines in a folded bit line structure, which includes bit line linking the bit line contacts in a shape of zigzag.
In accordance with the present invention, there is provided a semiconductor memory device having bit line contacts arranged as in a folded bit line structure and including a bit line linking the bit line contacts in an adjacent pair of rows. The bit line may be arranged as a straight line between the rows of the pair and have links extending at right angles to the bit line contacts.
Instead, the bit line may form a zigzag path linking the bit line contacts.
In the accompanying drawings;
Fig. 1 shows the layout of conventional semiconductor memory devices having a folded bit line structure;
Fig 2 shows the circuit representing the semiconductor memory devices of Fig. 1;
Fig. 3 shows the layout of conventional semiconductor memory devices having open bit line structure;
Fig. 4 shows the circuit representing the semiconductor memory devices of Fig 3;
Fig. 5 shows the layout of semiconductor memory devices according to a first embodiment of the present invention;
Fig. 6 shows the circuit representing the semiconductor memory devices of Fig. 5;
Fig. 7 shows the layout of semiconductor memory devices according to a second embodiment of the present invention;
Fig. 8 shows the circuit representing the semiconductor memory devices of Fig. 7.
Fig. 5 is a layout of semiconductor memory devices having bit lines according to a first embodiment of the present invention. The pair of bit lines BL and BL used in the prior art semiconductor memory devices of
Fig. 1 is formed into one bit line BL. As shown Fig. 5, the bit line BL links the bit line contacts of a pair of adjacent rows of the device. In this embodiment, the bit line is arranged as a straight line between the rows of the pair and has links extending at right angles to the bit line contacts of both the upper and lower rows.
The pitch of the bit lines according to the present invention is about twice as compared with the semiconductor memory devices having open bit line structure of Fig. 3, thus it makes arrangement of sense amplifiers
SA easy and coupling capacitance is negligible. ,Moreover, the length of bit line per unit cell is reduced by half as compared with semiconductor memory devices having conventional open bit line structure, so that sensing time is improved remarkably.
In theory, the RC delay of the semiconductor devices of Fig. 3 is R x (CJ + CB) (R is the resistance of bit line, CJ is the junction capacitance, and CB is the bit line capacitance), but the RC delay according to the present invention is R/2 x (CJ + CB/2), for a bit line having the same number of cells. Therefore, the RC delay is reduced and thus speed of operation is improved.
Fig. 6 is a circuit representing the semiconductor memory devices of Fig. 5. When a word line
WL is selected in cell array 13a, cells connected to the selected word line WL are turned on. In the cell array 13a, bit lines BL are connected to the sense amplifiers
SA. On the other hand, cells connected to an opposite corresponding word line WL in cell array 13b are turned off, and bit lines BL are also connected to the sense amplifiers SA. Therefore, data can be sensed in accordance with a difference in potential between the selected bit line BL and bit line BL having a reference voltage.
Fig. 7 is a layout of semiconductor memory devices according to a second embodiment of the present invention. As shown Fig. 7, bit line contacts 11 are linked by a bit line forming a zigzag path. Fig. 8 is a circuit representing the semiconductor memory devices of
Fig. 7.
As described above, according to the present invention, the number of cell per length of unit bit line is twice as compared with semiconductor memory devices having the open bit line structure of the prior art, so that when using a bit line having the same number of cells the resistance and the coupling capacitance are reduced, and the available voltage is increased for sensing of data, and the character and speed of operation are improved.
Moreover, the pitch between the bit lines according to the present invention is about twice as compared with semiconductor memory devices having the conventional open bit line structure, so that coupling capacitance between adjacent bit line is reduced.
Therefore, coupling noise in the high density memory of 16 mega class and over is reduced remarkably.
Claims (7)
1. A semiconductor memory device having bit line contacts arranged as in a folded bit line structure and including a bit line linking the bit line contacts in an adjacent pair of rows.
2. A semiconductor memory device as claimed in
Claim 1 wherein the bit line is arranged as a straight line between the rows of the pair and has links extending at right angles to the bit line contacts.
3. A semiconductor memory device as claimed in
Claim 1 wherein the bit line forms a zigzag path linking the bit line contacts.
4. A semiconductor memory device substantially as hereinbefore described with reference to and as illustrated in Figures 5 to 8 of the accompanying drawings.
5. A semiconductor memory device having bit line contacts provide in a folded bit line structure, comprising: bit line linking said bit line contacts in a shape of zigzag.
6. A semiconductor memory device according to
Claim 5, wherein said bit line contacts are linked at a right angle to each other.
7. A semiconductor memory device according to
Claim 5, wherein said bit line contacts are linked at abtuse angle to each other.
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR1019900004190A KR920007358B1 (en) | 1990-03-28 | 1990-03-28 | Vlsi cell and core array |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| GB9106576D0 GB9106576D0 (en) | 1991-05-15 |
| GB2242568A true GB2242568A (en) | 1991-10-02 |
Family
ID=19297455
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| GB9106576A Withdrawn GB2242568A (en) | 1990-03-28 | 1991-03-27 | Semiconductor memory devices |
Country Status (6)
| Country | Link |
|---|---|
| JP (1) | JPH0774266A (en) |
| KR (1) | KR920007358B1 (en) |
| DE (1) | DE4110155A1 (en) |
| FR (1) | FR2660475A1 (en) |
| GB (1) | GB2242568A (en) |
| NL (1) | NL9100536A (en) |
Families Citing this family (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2007013011A (en) * | 2005-07-01 | 2007-01-18 | Seiko Epson Corp | Ferroelectric memory device and driving ic (integrated circuit) for indication |
| US11877441B2 (en) | 2021-03-04 | 2024-01-16 | Changxin Memory Technologies, Inc. | Memory and fabricating method thereof |
| CN113053897B (en) * | 2021-03-04 | 2022-06-17 | 长鑫存储技术有限公司 | Memory and preparation method thereof |
Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| GB2005077A (en) * | 1977-09-28 | 1979-04-11 | Siemens Ag | Semiconductor storage elements |
| EP0031490A2 (en) * | 1979-12-26 | 1981-07-08 | International Business Machines Corporation | One device field effect transistor AC stable random access memory array |
| GB2114811A (en) * | 1981-06-15 | 1983-08-24 | Mitsubishi Electric Corp | Semiconductor memory |
Family Cites Families (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2682021B2 (en) * | 1988-06-29 | 1997-11-26 | 富士通株式会社 | Semiconductor memory device |
| JPH0276258A (en) * | 1988-09-13 | 1990-03-15 | Fujitsu Ltd | Semiconductor memory device |
| JP2681285B2 (en) * | 1988-09-19 | 1997-11-26 | 富士通株式会社 | Semiconductor memory device |
| JP2974252B2 (en) * | 1989-08-19 | 1999-11-10 | 富士通株式会社 | Semiconductor storage device |
-
1990
- 1990-03-28 KR KR1019900004190A patent/KR920007358B1/en not_active IP Right Cessation
-
1991
- 1991-03-22 FR FR9103522A patent/FR2660475A1/en active Pending
- 1991-03-26 NL NL9100536A patent/NL9100536A/en not_active Application Discontinuation
- 1991-03-27 GB GB9106576A patent/GB2242568A/en not_active Withdrawn
- 1991-03-27 DE DE4110155A patent/DE4110155A1/en not_active Ceased
- 1991-03-27 JP JP3063190A patent/JPH0774266A/en active Pending
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| GB2005077A (en) * | 1977-09-28 | 1979-04-11 | Siemens Ag | Semiconductor storage elements |
| EP0031490A2 (en) * | 1979-12-26 | 1981-07-08 | International Business Machines Corporation | One device field effect transistor AC stable random access memory array |
| GB2114811A (en) * | 1981-06-15 | 1983-08-24 | Mitsubishi Electric Corp | Semiconductor memory |
Also Published As
| Publication number | Publication date |
|---|---|
| JPH0774266A (en) | 1995-03-17 |
| KR910017640A (en) | 1991-11-05 |
| FR2660475A1 (en) | 1991-10-04 |
| KR920007358B1 (en) | 1992-08-31 |
| GB9106576D0 (en) | 1991-05-15 |
| DE4110155A1 (en) | 1991-10-02 |
| NL9100536A (en) | 1991-10-16 |
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Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| WAP | Application withdrawn, taken to be withdrawn or refused ** after publication under section 16(1) |