NL7904292A - Werkwijze voor het vormen van geintegreerde schakelin- gen op zeer grote schaal op een mono-kristallijn silicium-halfgeleidersubstraat, werkwijze voor het ver- vaardigen van een veldeffect-halfgeleiderinrichting en werkwijze voor het vormen van precies aansluitende contacten. - Google Patents

Werkwijze voor het vormen van geintegreerde schakelin- gen op zeer grote schaal op een mono-kristallijn silicium-halfgeleidersubstraat, werkwijze voor het ver- vaardigen van een veldeffect-halfgeleiderinrichting en werkwijze voor het vormen van precies aansluitende contacten.

Info

Publication number
NL7904292A
NL7904292A NL7904292A NL7904292A NL7904292A NL 7904292 A NL7904292 A NL 7904292A NL 7904292 A NL7904292 A NL 7904292A NL 7904292 A NL7904292 A NL 7904292A NL 7904292 A NL7904292 A NL 7904292A
Authority
NL
Netherlands
Prior art keywords
procedure
mono
manufacturing
forming
integrated circuits
Prior art date
Application number
NL7904292A
Other languages
English (en)
Dutch (nl)
Original Assignee
Rockwell International Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Rockwell International Corp filed Critical Rockwell International Corp
Publication of NL7904292A publication Critical patent/NL7904292A/xx

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Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76897—Formation of self-aligned vias or contact plugs, i.e. involving a lithographically uncritical step
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
    • H01L21/283—Deposition of conductive or insulating materials for electrodes conducting electric current
    • H01L21/285—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation
    • H01L21/28506—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers
    • H01L21/28512—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers on semiconductor bodies comprising elements of Group IV of the Periodic Table
    • H01L21/28525—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers on semiconductor bodies comprising elements of Group IV of the Periodic Table the conductive layers comprising semiconducting material
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B20/00—Read-only memory [ROM] devices
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S148/00—Metal treatment
    • Y10S148/043—Dual dielectric
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S148/00—Metal treatment
    • Y10S148/116—Oxidation, differential
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S148/00—Metal treatment
    • Y10S148/133—Reflow oxides and glasses
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S148/00—Metal treatment
    • Y10S148/141—Self-alignment coat gate
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S148/00—Metal treatment
    • Y10S148/173—Washed emitter

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Physics & Mathematics (AREA)
  • Power Engineering (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Electrodes Of Semiconductors (AREA)
  • Insulated Gate Type Field-Effect Transistor (AREA)
  • Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
  • Non-Volatile Memory (AREA)
NL7904292A 1978-06-06 1979-05-31 Werkwijze voor het vormen van geintegreerde schakelin- gen op zeer grote schaal op een mono-kristallijn silicium-halfgeleidersubstraat, werkwijze voor het ver- vaardigen van een veldeffect-halfgeleiderinrichting en werkwijze voor het vormen van precies aansluitende contacten. NL7904292A (nl)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US05/913,257 US4192059A (en) 1978-06-06 1978-06-06 Process for and structure of high density VLSI circuits, having inherently self-aligned gates and contacts for FET devices and conducting lines

Publications (1)

Publication Number Publication Date
NL7904292A true NL7904292A (nl) 1979-12-10

Family

ID=25433096

Family Applications (1)

Application Number Title Priority Date Filing Date
NL7904292A NL7904292A (nl) 1978-06-06 1979-05-31 Werkwijze voor het vormen van geintegreerde schakelin- gen op zeer grote schaal op een mono-kristallijn silicium-halfgeleidersubstraat, werkwijze voor het ver- vaardigen van een veldeffect-halfgeleiderinrichting en werkwijze voor het vormen van precies aansluitende contacten.

Country Status (6)

Country Link
US (1) US4192059A (ja)
JP (1) JPS5940297B2 (ja)
DE (1) DE2922018A1 (ja)
FR (1) FR2428358A1 (ja)
IT (1) IT1206967B (ja)
NL (1) NL7904292A (ja)

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US4506437A (en) * 1978-05-26 1985-03-26 Rockwell International Corporation Process for and structure of high density VLSI circuits, having self-aligned gates and contacts for FET devices and conducting lines
US4455737A (en) * 1978-05-26 1984-06-26 Rockwell International Corporation Process for and structure of high density VLSI circuits, having self-aligned gates and contacts for FET devices and conducting lines
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US4391650A (en) * 1980-12-22 1983-07-05 Ncr Corporation Method for fabricating improved complementary metal oxide semiconductor devices
US4517729A (en) * 1981-07-27 1985-05-21 American Microsystems, Incorporated Method for fabricating MOS device with self-aligned contacts
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US4397076A (en) * 1981-09-14 1983-08-09 Ncr Corporation Method for making low leakage polycrystalline silicon-to-substrate contacts
US4464824A (en) * 1982-08-18 1984-08-14 Ncr Corporation Epitaxial contact fabrication process
US4517731A (en) * 1983-09-29 1985-05-21 Fairchild Camera & Instrument Corporation Double polysilicon process for fabricating CMOS integrated circuits
US4584761A (en) * 1984-05-15 1986-04-29 Digital Equipment Corporation Integrated circuit chip processing techniques and integrated chip produced thereby
US4733291A (en) * 1985-11-15 1988-03-22 American Telephone And Telegraph Company, At&T Bell Laboratories Contact vias in semiconductor devices
US4825277A (en) * 1987-11-17 1989-04-25 Motorola Inc. Trench isolation process and structure
US4960727A (en) * 1987-11-17 1990-10-02 Motorola, Inc. Method for forming a dielectric filled trench
US4988643A (en) * 1989-10-10 1991-01-29 Vlsi Technology, Inc. Self-aligning metal interconnect fabrication
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US9496033B2 (en) 2010-08-20 2016-11-15 Attopsemi Technology Co., Ltd Method and system of programmable resistive devices with read capability using a low supply voltage
US9824768B2 (en) 2015-03-22 2017-11-21 Attopsemi Technology Co., Ltd Integrated OTP memory for providing MTP memory
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US9460807B2 (en) 2010-08-20 2016-10-04 Shine C. Chung One-time programmable memory devices using FinFET technology
US9251893B2 (en) 2010-08-20 2016-02-02 Shine C. Chung Multiple-bit programmable resistive memory using diode as program selector
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US9431127B2 (en) 2010-08-20 2016-08-30 Shine C. Chung Circuit and system of using junction diode as program selector for metal fuses for one-time programmable devices
US8804398B2 (en) 2010-08-20 2014-08-12 Shine C. Chung Reversible resistive memory using diodes formed in CMOS processes as program selectors
US9711237B2 (en) 2010-08-20 2017-07-18 Attopsemi Technology Co., Ltd. Method and structure for reliable electrical fuse programming
US10229746B2 (en) 2010-08-20 2019-03-12 Attopsemi Technology Co., Ltd OTP memory with high data security
US9070437B2 (en) 2010-08-20 2015-06-30 Shine C. Chung Circuit and system of using junction diode as program selector for one-time programmable devices with heat sink
US9236141B2 (en) 2010-08-20 2016-01-12 Shine C. Chung Circuit and system of using junction diode of MOS as program selector for programmable resistive devices
US10249379B2 (en) 2010-08-20 2019-04-02 Attopsemi Technology Co., Ltd One-time programmable devices having program selector for electrical fuses with extended area
US8830720B2 (en) 2010-08-20 2014-09-09 Shine C. Chung Circuit and system of using junction diode as program selector and MOS as read selector for one-time programmable devices
US9025357B2 (en) 2010-08-20 2015-05-05 Shine C. Chung Programmable resistive memory unit with data and reference cells
US9019742B2 (en) 2010-08-20 2015-04-28 Shine C. Chung Multiple-state one-time programmable (OTP) memory to function as multi-time programmable (MTP) memory
US10916317B2 (en) 2010-08-20 2021-02-09 Attopsemi Technology Co., Ltd Programmable resistance memory on thin film transistor technology
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Also Published As

Publication number Publication date
FR2428358A1 (fr) 1980-01-04
FR2428358B1 (ja) 1983-12-09
JPS54160183A (en) 1979-12-18
IT7949318A0 (it) 1979-06-05
IT1206967B (it) 1989-05-17
DE2922018A1 (de) 1979-12-13
US4192059A (en) 1980-03-11
JPS5940297B2 (ja) 1984-09-29

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