NL7614299A - Werkwijze ter vervaardiging van een half-gelei- derinrichting door isolatie met een oxydelaag, alsmede aldus verkregen half-geleiderinrichting. - Google Patents

Werkwijze ter vervaardiging van een half-gelei- derinrichting door isolatie met een oxydelaag, alsmede aldus verkregen half-geleiderinrichting.

Info

Publication number
NL7614299A
NL7614299A NL7614299A NL7614299A NL7614299A NL 7614299 A NL7614299 A NL 7614299A NL 7614299 A NL7614299 A NL 7614299A NL 7614299 A NL7614299 A NL 7614299A NL 7614299 A NL7614299 A NL 7614299A
Authority
NL
Netherlands
Prior art keywords
semi
conductor device
insulation
manufacture
well
Prior art date
Application number
NL7614299A
Other languages
English (en)
Original Assignee
Hitachi Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hitachi Ltd filed Critical Hitachi Ltd
Publication of NL7614299A publication Critical patent/NL7614299A/nl

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/482—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of lead-in layers inseparably applied to the semiconductor body
    • H01L23/485—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of lead-in layers inseparably applied to the semiconductor body consisting of layered constructions comprising conductive layers and insulating layers, e.g. planar contacts
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/74—Making of localized buried regions, e.g. buried collector layers, internal connections substrate contacts
    • H01L21/743—Making of internal connections, substrate contacts
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H01L21/76202—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using a local oxidation of silicon, e.g. LOCOS, SWAMI, SILO
    • H01L21/76205—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using a local oxidation of silicon, e.g. LOCOS, SWAMI, SILO in a region being recessed from the surface, e.g. in a recess, groove, tub or trench region
    • H01L21/76208—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using a local oxidation of silicon, e.g. LOCOS, SWAMI, SILO in a region being recessed from the surface, e.g. in a recess, groove, tub or trench region using auxiliary pillars in the recessed region, e.g. to form LOCOS over extended areas
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H01L21/76202—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using a local oxidation of silicon, e.g. LOCOS, SWAMI, SILO
    • H01L21/76205—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using a local oxidation of silicon, e.g. LOCOS, SWAMI, SILO in a region being recessed from the surface, e.g. in a recess, groove, tub or trench region
    • H01L21/7621—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using a local oxidation of silicon, e.g. LOCOS, SWAMI, SILO in a region being recessed from the surface, e.g. in a recess, groove, tub or trench region the recessed region having a shape other than rectangular, e.g. rounded or oblique shape
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
NL7614299A 1975-12-22 1976-12-22 Werkwijze ter vervaardiging van een half-gelei- derinrichting door isolatie met een oxydelaag, alsmede aldus verkregen half-geleiderinrichting. NL7614299A (nl)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP50151828A JPS5275989A (en) 1975-12-22 1975-12-22 Production of semiconductor device

Publications (1)

Publication Number Publication Date
NL7614299A true NL7614299A (nl) 1977-06-24

Family

ID=15527189

Family Applications (1)

Application Number Title Priority Date Filing Date
NL7614299A NL7614299A (nl) 1975-12-22 1976-12-22 Werkwijze ter vervaardiging van een half-gelei- derinrichting door isolatie met een oxydelaag, alsmede aldus verkregen half-geleiderinrichting.

Country Status (3)

Country Link
US (2) US4111724A (nl)
JP (1) JPS5275989A (nl)
NL (1) NL7614299A (nl)

Families Citing this family (27)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4198649A (en) * 1976-09-03 1980-04-15 Fairchild Camera And Instrument Corporation Memory cell structure utilizing conductive buried regions
NL7706802A (nl) * 1977-06-21 1978-12-27 Philips Nv Werkwijze voor het vervaardigen van een half- geleiderinrichting en halfgeleiderinrichting vervaardigd met behulp van de werkwijze.
US4219369A (en) * 1977-09-30 1980-08-26 Hitachi, Ltd. Method of making semiconductor integrated circuit device
US4228450A (en) * 1977-10-25 1980-10-14 International Business Machines Corporation Buried high sheet resistance structure for high density integrated circuits with reach through contacts
US4168999A (en) * 1978-12-26 1979-09-25 Fairchild Camera And Instrument Corporation Method for forming oxide isolated integrated injection logic semiconductor structures having minimal encroachment utilizing special masking techniques
US4261763A (en) * 1979-10-01 1981-04-14 Burroughs Corporation Fabrication of integrated circuits employing only ion implantation for all dopant layers
JPS5737849A (en) * 1980-08-20 1982-03-02 Toshiba Corp Manufacture of semiconductor device
US4395438A (en) * 1980-09-08 1983-07-26 Amdahl Corporation Low pressure chemical vapor deposition of silicon nitride films
US4624046A (en) * 1982-01-04 1986-11-25 Fairchild Camera & Instrument Corp. Oxide isolation process for standard RAM/PROM and lateral PNP cell RAM
JPS58127374A (ja) * 1982-01-25 1983-07-29 Hitachi Ltd 半導体装置の製造方法
JPS60103642A (ja) * 1983-11-11 1985-06-07 Hitachi Ltd 半導体装置およびその製造方法
FR2547954B1 (fr) * 1983-06-21 1985-10-25 Efcis Procede de fabrication de composants semi-conducteurs isoles dans une plaquette semi-conductrice
US4498227A (en) * 1983-07-05 1985-02-12 Fairchild Camera & Instrument Corporation Wafer fabrication by implanting through protective layer
US4519128A (en) * 1983-10-05 1985-05-28 International Business Machines Corporation Method of making a trench isolated device
US4671851A (en) * 1985-10-28 1987-06-09 International Business Machines Corporation Method for removing protuberances at the surface of a semiconductor wafer using a chem-mech polishing technique
US4729816A (en) * 1987-01-02 1988-03-08 Motorola, Inc. Isolation formation process with active area protection
JPH0682750B2 (ja) * 1989-08-30 1994-10-19 日東電工株式会社 ウエハ保護シートの剥離方法
US4987099A (en) * 1989-12-29 1991-01-22 North American Philips Corp. Method for selectively filling contacts or vias or various depths with CVD tungsten
KR0131723B1 (ko) * 1994-06-08 1998-04-14 김주용 반도체소자 및 그 제조방법
JPH08316223A (ja) * 1995-05-16 1996-11-29 Mitsubishi Electric Corp 半導体装置およびその製造方法
KR100384560B1 (ko) * 1995-06-30 2003-08-06 주식회사 하이닉스반도체 반도체소자및그제조방법
US5876879A (en) * 1997-05-29 1999-03-02 International Business Machines Corporation Oxide layer patterned by vapor phase etching
US5838055A (en) * 1997-05-29 1998-11-17 International Business Machines Corporation Trench sidewall patterned by vapor phase etching
US6074951A (en) * 1997-05-29 2000-06-13 International Business Machines Corporation Vapor phase etching of oxide masked by resist or masking material
US6326281B1 (en) * 1998-09-23 2001-12-04 Texas Instruments Incorporated Integrated circuit isolation
JP3751469B2 (ja) * 1999-04-26 2006-03-01 沖電気工業株式会社 Ｓｏｉ構造の半導体装置の製造方法
CN105609544B (zh) 2015-12-22 2019-05-03 杭州士兰微电子股份有限公司 绝缘隔离半导体器件及其制造方法

Family Cites Families (12)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3759761A (en) * 1968-10-23 1973-09-18 Hitachi Ltd Washed emitter method for improving passivation of a transistor
US3648125A (en) 1971-02-02 1972-03-07 Fairchild Camera Instr Co Method of fabricating integrated circuits with oxidized isolation and the resulting structure
US4005453A (en) * 1971-04-14 1977-01-25 U.S. Philips Corporation Semiconductor device with isolated circuit elements and method of making
GB1388926A (en) * 1972-03-04 1975-03-26 Ferranti Ltd Manufacture of silicon semiconductor devices
JPS5038836B2 (nl) * 1972-09-13 1975-12-12
GB1457139A (en) * 1973-09-27 1976-12-01 Hitachi Ltd Method of manufacturing semiconductor device
JPS5214594B2 (nl) * 1973-10-17 1977-04-22
US3962779A (en) * 1974-01-14 1976-06-15 Bell Telephone Laboratories, Incorporated Method for fabricating oxide isolated integrated circuits
US4038110A (en) * 1974-06-17 1977-07-26 Ibm Corporation Planarization of integrated circuit surfaces through selective photoresist masking
US4023195A (en) * 1974-10-23 1977-05-10 Smc Microsystems Corporation MOS field-effect transistor structure with mesa-like contact and gate areas and selectively deeper junctions
US4044454A (en) * 1975-04-16 1977-08-30 Ibm Corporation Method for forming integrated circuit regions defined by recessed dielectric isolation
US4002511A (en) * 1975-04-16 1977-01-11 Ibm Corporation Method for forming masks comprising silicon nitride and novel mask structures produced thereby

Also Published As

Publication number Publication date
US4111724A (en) 1978-09-05
JPS5275989A (en) 1977-06-25
USRE31506E (en) 1984-01-24
JPS5541531B2 (nl) 1980-10-24

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