NL7512713A - METHOD OF PROVIDING A SUBSTITUTE MEMORY MODULE IN A DATA PROCESSING SYSTEM. - Google Patents

METHOD OF PROVIDING A SUBSTITUTE MEMORY MODULE IN A DATA PROCESSING SYSTEM.

Info

Publication number
NL7512713A
NL7512713A NL7512713A NL7512713A NL7512713A NL 7512713 A NL7512713 A NL 7512713A NL 7512713 A NL7512713 A NL 7512713A NL 7512713 A NL7512713 A NL 7512713A NL 7512713 A NL7512713 A NL 7512713A
Authority
NL
Netherlands
Prior art keywords
memory module
address
marked
store
data processing
Prior art date
Application number
NL7512713A
Other languages
Dutch (nl)
Original Assignee
Northern Electric Co
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Northern Electric Co filed Critical Northern Electric Co
Publication of NL7512713A publication Critical patent/NL7512713A/en

Links

Classifications

    • GPHYSICS
    • G11INFORMATION STORAGE
    • G11CSTATIC STORES
    • G11C29/00Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/70Masking faults in memories by using spares or by reconfiguring
    • G11C29/78Masking faults in memories by using spares or by reconfiguring using programmable devices
    • GPHYSICS
    • G05CONTROLLING; REGULATING
    • G05DSYSTEMS FOR CONTROLLING OR REGULATING NON-ELECTRIC VARIABLES
    • G05D13/00Control of linear speed; Control of angular speed; Control of acceleration or deceleration, e.g. of a prime mover
    • G05D13/08Control of linear speed; Control of angular speed; Control of acceleration or deceleration, e.g. of a prime mover without auxiliary power
    • G05D13/10Centrifugal governors with fly-weights
    • HELECTRICITY
    • H04ELECTRIC COMMUNICATION TECHNIQUE
    • H04QSELECTING
    • H04Q3/00Selecting arrangements
    • H04Q3/42Circuit arrangements for indirect selecting controlled by common circuits, e.g. register controller, marker
    • H04Q3/54Circuit arrangements for indirect selecting controlled by common circuits, e.g. register controller, marker in which the logic circuitry controlling the exchange is centralised
    • H04Q3/545Circuit arrangements for indirect selecting controlled by common circuits, e.g. register controller, marker in which the logic circuitry controlling the exchange is centralised using a stored programme
    • H04Q3/54541Circuit arrangements for indirect selecting controlled by common circuits, e.g. register controller, marker in which the logic circuitry controlling the exchange is centralised using a stored programme using multi-processor systems
    • H04Q3/54558Redundancy, stand-by

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Automation & Control Theory (AREA)
  • Computer Networks & Wireless Communication (AREA)
  • Techniques For Improving Reliability Of Storages (AREA)
  • Exchange Systems With Centralized Control (AREA)
  • Hardware Redundancy (AREA)

Abstract

1512220 Data processing NORTHERN TELECOM Ltd 29 Oct 1975 [12 Nov 1974] 44698/75 Heading G4A A low priority memory module M1 is marked, by setting a spare marker 107 to 1, to be used as a substitute for a higher priority memory module M2 or M3 which develops a fault. In normal operation each called address is fed to a comparator 102, coincidence of the called address with the memory module address in a store 101 enabling store 21 via gates 103 and 111. If a fault develops in a memory module the address of the faulty memory module is entered in an address register 400 and a 1 is output on a bus 300 which disables AND gate 103 in the marked memory module M1 to prevent it responding to its own address. Data identical to that in the faulty memory module is then loaded, for example from a standby magnetic tape unit, into the store 21 of the marked memory module M1. Each called address is fed to a comparator 500 and on coincidence with the faulty memory module address in address register 400a 1 is output on line 200 to enable store 21 in the marked memory module M1 via gates 110 and 111. The memory modules M1-M3 may form part of the control unit of a multi-line, multistation telephone exchange system.
NL7512713A 1974-11-12 1975-10-30 METHOD OF PROVIDING A SUBSTITUTE MEMORY MODULE IN A DATA PROCESSING SYSTEM. NL7512713A (en)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
CA213,526A CA1053352A (en) 1974-11-12 1974-11-12 Method for providing a substitute memory module in a data processing system

Publications (1)

Publication Number Publication Date
NL7512713A true NL7512713A (en) 1976-05-14

Family

ID=4101603

Family Applications (1)

Application Number Title Priority Date Filing Date
NL7512713A NL7512713A (en) 1974-11-12 1975-10-30 METHOD OF PROVIDING A SUBSTITUTE MEMORY MODULE IN A DATA PROCESSING SYSTEM.

Country Status (7)

Country Link
JP (1) JPS5412373B2 (en)
CA (1) CA1053352A (en)
DE (1) DE2550805A1 (en)
FR (1) FR2291544A1 (en)
GB (1) GB1512220A (en)
NL (1) NL7512713A (en)
SE (2) SE413949B (en)

Families Citing this family (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE2741379A1 (en) * 1977-09-14 1979-03-15 Siemens Ag COMPUTER SYSTEM
JPS5580164A (en) * 1978-12-13 1980-06-17 Fujitsu Ltd Main memory constitution control system
JPS6272138A (en) * 1985-09-26 1987-04-02 Hitachi Electronics Eng Co Ltd Wafer positioning retainer
FR2643993B1 (en) * 1989-03-03 1991-05-17 Bull Sa METHOD FOR REPLACING MEMORY MODULES IN A COMPUTER SYSTEM AND COMPUTER SYSTEM FOR IMPLEMENTING THE METHOD
US7139942B2 (en) * 2003-07-21 2006-11-21 Sun Microsystems, Inc. Method and apparatus for memory redundancy and recovery from uncorrectable errors

Also Published As

Publication number Publication date
FR2291544A1 (en) 1976-06-11
GB1512220A (en) 1978-05-24
DE2550805A1 (en) 1976-05-13
SE7512711L (en) 1976-05-13
JPS5412373B2 (en) 1979-05-22
SE413949B (en) 1980-06-30
SE413948B (en) 1980-06-30
SE7710060L (en) 1979-03-08
JPS5171641A (en) 1976-06-21
CA1053352A (en) 1979-04-24

Similar Documents

Publication Publication Date Title
US4150428A (en) Method for providing a substitute memory in a data processing system
GB1504602A (en) Word organized random access memory systems
GB1378224A (en) Data processing apparatus
GB1412051A (en) Method and apparatus for regulating input/output traffic of a data processing system
EP0094042A3 (en) Data processing apparatus wherein a system bus is shared by two or more circuits
GB1411882A (en) Methods and apparatus for control of data processing systems
NL7512713A (en) METHOD OF PROVIDING A SUBSTITUTE MEMORY MODULE IN A DATA PROCESSING SYSTEM.
GB1056511A (en) Interrupt logic system for computers
GB1092520A (en) Data processing systems
GB1166647A (en) Improvements in Electronic Data Processing Systems
ES416400A1 (en) Data processing systems
GB1043642A (en) Method of checking clock-pulse controlled electronic storage members during operation
GB1536436A (en) Memory reconfiguration device
GB1164000A (en) Data Processing System with Controls to Deal with Requests from Subsystem for Prohibited Operations
GB1520484A (en) Data processing system
GB1497738A (en) Information transfer
JPS58159292A (en) Memory refreshing method
JPS5229131A (en) Storage protection unit for counter-channel input & output device
JPS59154698A (en) Protecting system of control storage
JPS5537680A (en) Decentralized control system
GB1092660A (en) Computing system
JPS6448152A (en) Memory write protection system
GB1482659A (en) Device for selective exchange of information
JPS5769460A (en) Data saving control system
JPH05347096A (en) Multi-port ram

Legal Events

Date Code Title Description
BV The patent application has lapsed