GB1512220A - Method of providing a substitute memory module - Google Patents
Method of providing a substitute memory moduleInfo
- Publication number
- GB1512220A GB1512220A GB44698/75A GB4469875A GB1512220A GB 1512220 A GB1512220 A GB 1512220A GB 44698/75 A GB44698/75 A GB 44698/75A GB 4469875 A GB4469875 A GB 4469875A GB 1512220 A GB1512220 A GB 1512220A
- Authority
- GB
- United Kingdom
- Prior art keywords
- memory module
- address
- marked
- store
- faulty
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired
Links
- 239000003550 marker Substances 0.000 abstract 1
Classifications
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
- G11C29/70—Masking faults in memories by using spares or by reconfiguring
- G11C29/78—Masking faults in memories by using spares or by reconfiguring using programmable devices
-
- G—PHYSICS
- G05—CONTROLLING; REGULATING
- G05D—SYSTEMS FOR CONTROLLING OR REGULATING NON-ELECTRIC VARIABLES
- G05D13/00—Control of linear speed; Control of angular speed; Control of acceleration or deceleration, e.g. of a prime mover
- G05D13/08—Control of linear speed; Control of angular speed; Control of acceleration or deceleration, e.g. of a prime mover without auxiliary power
- G05D13/10—Centrifugal governors with fly-weights
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04Q—SELECTING
- H04Q3/00—Selecting arrangements
- H04Q3/42—Circuit arrangements for indirect selecting controlled by common circuits, e.g. register controller, marker
- H04Q3/54—Circuit arrangements for indirect selecting controlled by common circuits, e.g. register controller, marker in which the logic circuitry controlling the exchange is centralised
- H04Q3/545—Circuit arrangements for indirect selecting controlled by common circuits, e.g. register controller, marker in which the logic circuitry controlling the exchange is centralised using a stored programme
- H04Q3/54541—Circuit arrangements for indirect selecting controlled by common circuits, e.g. register controller, marker in which the logic circuitry controlling the exchange is centralised using a stored programme using multi-processor systems
- H04Q3/54558—Redundancy, stand-by
Landscapes
- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- General Physics & Mathematics (AREA)
- Automation & Control Theory (AREA)
- Computer Networks & Wireless Communication (AREA)
- Techniques For Improving Reliability Of Storages (AREA)
- Exchange Systems With Centralized Control (AREA)
- Hardware Redundancy (AREA)
Abstract
1512220 Data processing NORTHERN TELECOM Ltd 29 Oct 1975 [12 Nov 1974] 44698/75 Heading G4A A low priority memory module M1 is marked, by setting a spare marker 107 to 1, to be used as a substitute for a higher priority memory module M2 or M3 which develops a fault. In normal operation each called address is fed to a comparator 102, coincidence of the called address with the memory module address in a store 101 enabling store 21 via gates 103 and 111. If a fault develops in a memory module the address of the faulty memory module is entered in an address register 400 and a 1 is output on a bus 300 which disables AND gate 103 in the marked memory module M1 to prevent it responding to its own address. Data identical to that in the faulty memory module is then loaded, for example from a standby magnetic tape unit, into the store 21 of the marked memory module M1. Each called address is fed to a comparator 500 and on coincidence with the faulty memory module address in address register 400a 1 is output on line 200 to enable store 21 in the marked memory module M1 via gates 110 and 111. The memory modules M1-M3 may form part of the control unit of a multi-line, multistation telephone exchange system.
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
CA213,526A CA1053352A (en) | 1974-11-12 | 1974-11-12 | Method for providing a substitute memory module in a data processing system |
Publications (1)
Publication Number | Publication Date |
---|---|
GB1512220A true GB1512220A (en) | 1978-05-24 |
Family
ID=4101603
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
GB44698/75A Expired GB1512220A (en) | 1974-11-12 | 1975-10-29 | Method of providing a substitute memory module |
Country Status (7)
Country | Link |
---|---|
JP (1) | JPS5412373B2 (en) |
CA (1) | CA1053352A (en) |
DE (1) | DE2550805A1 (en) |
FR (1) | FR2291544A1 (en) |
GB (1) | GB1512220A (en) |
NL (1) | NL7512713A (en) |
SE (2) | SE413949B (en) |
Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
DE2949768A1 (en) * | 1978-12-13 | 1980-06-19 | Fujitsu Ltd | MAIN STORAGE CONFIGURATION CONTROL SYSTEM |
GB2404261A (en) * | 2003-07-21 | 2005-01-26 | Sun Microsystems Inc | Memory redundancy and recovery from uncorrectable errors |
Families Citing this family (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
DE2741379A1 (en) * | 1977-09-14 | 1979-03-15 | Siemens Ag | COMPUTER SYSTEM |
JPS6272138A (en) * | 1985-09-26 | 1987-04-02 | Hitachi Electronics Eng Co Ltd | Wafer positioning retainer |
FR2643993B1 (en) * | 1989-03-03 | 1991-05-17 | Bull Sa | METHOD FOR REPLACING MEMORY MODULES IN A COMPUTER SYSTEM AND COMPUTER SYSTEM FOR IMPLEMENTING THE METHOD |
-
1974
- 1974-11-12 CA CA213,526A patent/CA1053352A/en not_active Expired
-
1975
- 1975-10-29 GB GB44698/75A patent/GB1512220A/en not_active Expired
- 1975-10-30 NL NL7512713A patent/NL7512713A/en not_active Application Discontinuation
- 1975-11-10 JP JP13421075A patent/JPS5412373B2/ja not_active Expired
- 1975-11-12 DE DE19752550805 patent/DE2550805A1/en not_active Withdrawn
- 1975-11-12 FR FR7534509A patent/FR2291544A1/en not_active Withdrawn
- 1975-11-12 SE SE7512711-8A patent/SE413949B/en not_active IP Right Cessation
-
1977
- 1977-09-07 SE SE7512711A patent/SE413948B/en unknown
Cited By (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
DE2949768A1 (en) * | 1978-12-13 | 1980-06-19 | Fujitsu Ltd | MAIN STORAGE CONFIGURATION CONTROL SYSTEM |
GB2404261A (en) * | 2003-07-21 | 2005-01-26 | Sun Microsystems Inc | Memory redundancy and recovery from uncorrectable errors |
GB2404261B (en) * | 2003-07-21 | 2005-12-07 | Sun Microsystems Inc | Method and apparatus for memory redundancy and recovery from uncorrectable errors |
US7139942B2 (en) | 2003-07-21 | 2006-11-21 | Sun Microsystems, Inc. | Method and apparatus for memory redundancy and recovery from uncorrectable errors |
Also Published As
Publication number | Publication date |
---|---|
FR2291544A1 (en) | 1976-06-11 |
DE2550805A1 (en) | 1976-05-13 |
NL7512713A (en) | 1976-05-14 |
SE7512711L (en) | 1976-05-13 |
JPS5412373B2 (en) | 1979-05-22 |
SE413949B (en) | 1980-06-30 |
SE413948B (en) | 1980-06-30 |
SE7710060L (en) | 1979-03-08 |
JPS5171641A (en) | 1976-06-21 |
CA1053352A (en) | 1979-04-24 |
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Legal Events
Date | Code | Title | Description |
---|---|---|---|
PS | Patent sealed [section 19, patents act 1949] | ||
PCNP | Patent ceased through non-payment of renewal fee |