CA1053352A - Method for providing a substitute memory module in a data processing system - Google Patents
Method for providing a substitute memory module in a data processing systemInfo
- Publication number
- CA1053352A CA1053352A CA213,526A CA213526A CA1053352A CA 1053352 A CA1053352 A CA 1053352A CA 213526 A CA213526 A CA 213526A CA 1053352 A CA1053352 A CA 1053352A
- Authority
- CA
- Canada
- Prior art keywords
- memory module
- address
- spare
- module
- data
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired
Links
- 238000000034 method Methods 0.000 title claims abstract description 14
- 238000001514 detection method Methods 0.000 claims abstract description 4
- 239000003550 marker Substances 0.000 description 4
- 230000006870 function Effects 0.000 description 2
- 239000000470 constituent Substances 0.000 description 1
- 230000002401 inhibitory effect Effects 0.000 description 1
- 150000002500 ions Chemical class 0.000 description 1
- 230000007257 malfunction Effects 0.000 description 1
- 230000002093 peripheral effect Effects 0.000 description 1
- 238000006467 substitution reaction Methods 0.000 description 1
Classifications
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
- G11C29/70—Masking faults in memories by using spares or by reconfiguring
- G11C29/78—Masking faults in memories by using spares or by reconfiguring using programmable devices
-
- G—PHYSICS
- G05—CONTROLLING; REGULATING
- G05D—SYSTEMS FOR CONTROLLING OR REGULATING NON-ELECTRIC VARIABLES
- G05D13/00—Control of linear speed; Control of angular speed; Control of acceleration or deceleration, e.g. of a prime mover
- G05D13/08—Control of linear speed; Control of angular speed; Control of acceleration or deceleration, e.g. of a prime mover without auxiliary power
- G05D13/10—Centrifugal governors with fly-weights
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04Q—SELECTING
- H04Q3/00—Selecting arrangements
- H04Q3/42—Circuit arrangements for indirect selecting controlled by common circuits, e.g. register controller, marker
- H04Q3/54—Circuit arrangements for indirect selecting controlled by common circuits, e.g. register controller, marker in which the logic circuitry controlling the exchange is centralised
- H04Q3/545—Circuit arrangements for indirect selecting controlled by common circuits, e.g. register controller, marker in which the logic circuitry controlling the exchange is centralised using a stored programme
- H04Q3/54541—Circuit arrangements for indirect selecting controlled by common circuits, e.g. register controller, marker in which the logic circuitry controlling the exchange is centralised using a stored programme using multi-processor systems
- H04Q3/54558—Redundancy, stand-by
Landscapes
- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- General Physics & Mathematics (AREA)
- Automation & Control Theory (AREA)
- Computer Networks & Wireless Communication (AREA)
- Techniques For Improving Reliability Of Storages (AREA)
- Exchange Systems With Centralized Control (AREA)
- Hardware Redundancy (AREA)
Abstract
Abstract of the Disclosure A method for substituting one memory module for another.
faulty, memory module comprises designating and marking a memory module as the substitute module, which, upon detection of a fault in the other memory module, is inhibited from responding to its own address when called.
and responds to the address of the faulty module whenever the latter is called.
- i -
faulty, memory module comprises designating and marking a memory module as the substitute module, which, upon detection of a fault in the other memory module, is inhibited from responding to its own address when called.
and responds to the address of the faulty module whenever the latter is called.
- i -
Description
~LO S~33~2 Field of the Invention The present invention relates to data processing systems in general and in particular to the utilization of memory modules therein.
Background of the Invention In recent years the trend in the ~elephone apparatus and systems has been toward increased computerization. As a result many such systems of modern design contain data processing sub-systems to perform supervision and control func~ions in lieu of the hitherto extensively used electromechanical devices.
1~ The requirements placed on telephone systems are in certain aspects sometimes in conflict with the performance specifications of ~ -conventional data processing systems. Certainly the most prominent example o~ such conflict arises due to ~he extreme reliability requirements placed on telephone systems and apparatus. In contrast~ occasional failure of a computer, be it because of hard or software malfunction, is not uncommon.
While often higher reliability on telephone systems is attained by duplicating critical units of the system, such approach is in conflict with yet another important requirement, that of cost.
The present invention discloses a method for inexpensively providing spare memory capability in a data processing system at the cost of slightly reducing its normal functional capability. The present invention is particularly suitable for use in certain types of telephone systems. It is, however, not restricted to such use, as will be apparent to those skilled in related arts.
Summary of the Invention The method of the present invention is applicable in a data processing system having a plurality of separately callable memory modules each having an address. The method permits substitution of one ~ e,/ecfror~c~l//y 3~ memory module for another and comprises the steps of:~ marking one memory module as a spare or substitute module; storing into an address register ~05~3~2 the address of another memory module upon fault detection thereini inhibiting the substitu~e memory m~dule from responding to its address, Gontinuously comparing called addresses of memory modules with the address stored in the address register; and, upon occurrence of a match between a called address and the address in the register, selecting the substitute memory module instead of the called memory module.
Usually the memory module marked as a substitute module would be one o~ low priority and/or low utilization probability (for example due to it having a high address in a read/wri~e or scratch-pad memory) compared with the remaining modules. The substitute memory module is loaded with data substantially identical to that of the faulty module after the fault has been detected. In a preferred embodiment, this is accomplished by reading the appropriate portion of an auxiliary standby storage tape containing the data vital to the system. This, of course, occurs under the control of the CPU (Central Processing Unit) in the system in a well known manner. Clearly, all other control functions such as fault location among memory modules, the calling of memory module -addresses and the loading of the address of the faulty memory module into the address register are initiated by the CPU.
Any interruption of service due to the process of loading the substitute module will depend on the type and capacity of the module and should be in the order of minutes which is still better than total failure.
BrieF Description of the ~rawings An example embodiment will now be described in conjunction with the drawings in which:
Figure 1 is a block schematic of a multi-line, multi-station telephone exchange system capable of increased reliability according to the present invention; and 3~ Figure 2 is a block schematic of a circuit embodying the method of the present invention as utilized in the system of F~gure 1.
-
Background of the Invention In recent years the trend in the ~elephone apparatus and systems has been toward increased computerization. As a result many such systems of modern design contain data processing sub-systems to perform supervision and control func~ions in lieu of the hitherto extensively used electromechanical devices.
1~ The requirements placed on telephone systems are in certain aspects sometimes in conflict with the performance specifications of ~ -conventional data processing systems. Certainly the most prominent example o~ such conflict arises due to ~he extreme reliability requirements placed on telephone systems and apparatus. In contrast~ occasional failure of a computer, be it because of hard or software malfunction, is not uncommon.
While often higher reliability on telephone systems is attained by duplicating critical units of the system, such approach is in conflict with yet another important requirement, that of cost.
The present invention discloses a method for inexpensively providing spare memory capability in a data processing system at the cost of slightly reducing its normal functional capability. The present invention is particularly suitable for use in certain types of telephone systems. It is, however, not restricted to such use, as will be apparent to those skilled in related arts.
Summary of the Invention The method of the present invention is applicable in a data processing system having a plurality of separately callable memory modules each having an address. The method permits substitution of one ~ e,/ecfror~c~l//y 3~ memory module for another and comprises the steps of:~ marking one memory module as a spare or substitute module; storing into an address register ~05~3~2 the address of another memory module upon fault detection thereini inhibiting the substitu~e memory m~dule from responding to its address, Gontinuously comparing called addresses of memory modules with the address stored in the address register; and, upon occurrence of a match between a called address and the address in the register, selecting the substitute memory module instead of the called memory module.
Usually the memory module marked as a substitute module would be one o~ low priority and/or low utilization probability (for example due to it having a high address in a read/wri~e or scratch-pad memory) compared with the remaining modules. The substitute memory module is loaded with data substantially identical to that of the faulty module after the fault has been detected. In a preferred embodiment, this is accomplished by reading the appropriate portion of an auxiliary standby storage tape containing the data vital to the system. This, of course, occurs under the control of the CPU (Central Processing Unit) in the system in a well known manner. Clearly, all other control functions such as fault location among memory modules, the calling of memory module -addresses and the loading of the address of the faulty memory module into the address register are initiated by the CPU.
Any interruption of service due to the process of loading the substitute module will depend on the type and capacity of the module and should be in the order of minutes which is still better than total failure.
BrieF Description of the ~rawings An example embodiment will now be described in conjunction with the drawings in which:
Figure 1 is a block schematic of a multi-line, multi-station telephone exchange system capable of increased reliability according to the present invention; and 3~ Figure 2 is a block schematic of a circuit embodying the method of the present invention as utilized in the system of F~gure 1.
-
- 2 - : ~
1~533SZ
Description of the Preferred ~mbodiment The method of the present invention is utilized in a multi-line, multi-station telephone exchange system which performs internal switching functions as well as connects local station sets with an exchange office of the telephone network. The outline of a typical system is shown schematically in Figure 1 o~ the drawings. It comprises a plurality of station sets Sl to Sn which are centrally connected to a peripheral equipment unit Pl. The un;~ Pl is in turn connected to a control unit CU
which contains a central processing unit CPU that (among o~her tasks) controls acoess to a standby magnetic tape storage unit MT and a system memory SM. For clarity of description, Figure 1 shows only essential elements of the system that are necessary for understanding the present nvention.
The sub-system of the control unit subject of the present invention is the system memory SM shown in Figure 2 of the drawings in more detail. Again for reasons of clarity and ease of understanding, the system memory is shown with only three constituent memory modules Ml, M2 and M3. Each memory module is callable via an address bus 100 by a unique individual address, the individual addresses being decoded in address decoder logic units 10, 11 and 12 which in turn enable the associated data store upon the occurrence of a match between the stored memory module address and the called address. The data from or into data stores 21, 22 and 23 is usually written and read from and on a common data bus. The address decoder logic unit 10 is shown in block schematic and comprises a module address store 101 supplying the module address to a comparator 102 which compares the same with the called address on address bus 100. The result of the comparison is fed to an AND-gate 103, which is also driven by an OR-gate 104. One input of the OR-gate 104 is driven from a spare-in-use bus 200 via an inverter 105.
The other input of the OR-ga~e 104 is driven from an AND-gate 106, one input of which is driven from spare marker 107 via an inverter 108.
~ 05335Z
The ~ther input of the AND-gate 106 is driven from a select-spare bus 300 via an inverter 109. The spare marker 107 also drives an AND-gate llO, also driven by the select-spare bus 300. The output of the AND-gate 110 as well as that of the AND-gate 103 drives an OR-gate 111 which enables (and disables) the data store 21. -An address register 400 is controlled from the CPU of the system and is adapted to receive the address of a faulty memory module.
One bit in the address register 400 is set to logical "1" when the register is being loaded with an address, it is termed spare-in-use lQ bit and driyes the spare-in-use bus 200. The contents of the address register 400 are input to a comparator 500 which continuously compares the address in the register 400 (iF any) with the called address on the address bus lOO. The result is output on the select-spare bus 300.
The address bus 1009 the spare-in-use bus 200 and the select-spare bus 300 all are inputs to each of the memory modules l, 2 and 3.
Now the method of operation of the system will be described step by step. Assuming the memory module 1 is a low priority module and has been selected to be the substitute module, the first step is . ~.
to set spare marker 107 to a logical ''l''g thus marking that module as 2~ the substitute module. As long as no fault in any of the other memory modules ~ and 3 is detected, no address is stored in the address register 400 and the output of the comparator 500 connected to the select-spare bus ~ is low (at logical "O"). As a result, and unless enabled via its other input, the output of the OR-gate 111 which enables the data store 21 remains low and hence the data store 111 inaccessible.
When a fault in one of the memory modules (say 3) is detected, the CPU enters the address of the memory module 3 into the address register 400 and simultaneously sets the spare-in-use bit in that 20~
register to "l" (or high). Thus the spare-in-use bus ~ now is at a
1~533SZ
Description of the Preferred ~mbodiment The method of the present invention is utilized in a multi-line, multi-station telephone exchange system which performs internal switching functions as well as connects local station sets with an exchange office of the telephone network. The outline of a typical system is shown schematically in Figure 1 o~ the drawings. It comprises a plurality of station sets Sl to Sn which are centrally connected to a peripheral equipment unit Pl. The un;~ Pl is in turn connected to a control unit CU
which contains a central processing unit CPU that (among o~her tasks) controls acoess to a standby magnetic tape storage unit MT and a system memory SM. For clarity of description, Figure 1 shows only essential elements of the system that are necessary for understanding the present nvention.
The sub-system of the control unit subject of the present invention is the system memory SM shown in Figure 2 of the drawings in more detail. Again for reasons of clarity and ease of understanding, the system memory is shown with only three constituent memory modules Ml, M2 and M3. Each memory module is callable via an address bus 100 by a unique individual address, the individual addresses being decoded in address decoder logic units 10, 11 and 12 which in turn enable the associated data store upon the occurrence of a match between the stored memory module address and the called address. The data from or into data stores 21, 22 and 23 is usually written and read from and on a common data bus. The address decoder logic unit 10 is shown in block schematic and comprises a module address store 101 supplying the module address to a comparator 102 which compares the same with the called address on address bus 100. The result of the comparison is fed to an AND-gate 103, which is also driven by an OR-gate 104. One input of the OR-gate 104 is driven from a spare-in-use bus 200 via an inverter 105.
The other input of the OR-ga~e 104 is driven from an AND-gate 106, one input of which is driven from spare marker 107 via an inverter 108.
~ 05335Z
The ~ther input of the AND-gate 106 is driven from a select-spare bus 300 via an inverter 109. The spare marker 107 also drives an AND-gate llO, also driven by the select-spare bus 300. The output of the AND-gate 110 as well as that of the AND-gate 103 drives an OR-gate 111 which enables (and disables) the data store 21. -An address register 400 is controlled from the CPU of the system and is adapted to receive the address of a faulty memory module.
One bit in the address register 400 is set to logical "1" when the register is being loaded with an address, it is termed spare-in-use lQ bit and driyes the spare-in-use bus 200. The contents of the address register 400 are input to a comparator 500 which continuously compares the address in the register 400 (iF any) with the called address on the address bus lOO. The result is output on the select-spare bus 300.
The address bus 1009 the spare-in-use bus 200 and the select-spare bus 300 all are inputs to each of the memory modules l, 2 and 3.
Now the method of operation of the system will be described step by step. Assuming the memory module 1 is a low priority module and has been selected to be the substitute module, the first step is . ~.
to set spare marker 107 to a logical ''l''g thus marking that module as 2~ the substitute module. As long as no fault in any of the other memory modules ~ and 3 is detected, no address is stored in the address register 400 and the output of the comparator 500 connected to the select-spare bus ~ is low (at logical "O"). As a result, and unless enabled via its other input, the output of the OR-gate 111 which enables the data store 21 remains low and hence the data store 111 inaccessible.
When a fault in one of the memory modules (say 3) is detected, the CPU enters the address of the memory module 3 into the address register 400 and simultaneously sets the spare-in-use bit in that 20~
register to "l" (or high). Thus the spare-in-use bus ~ now is at a
3~ logical high.
The inYerter 105 in the address decoder logic unit lO
The inYerter 105 in the address decoder logic unit lO
- 4 -~ L6~5;33 ~
inverts the logical high of the spare-in-use bus 30~ to a logical low, and hence, the output of the OR-gate 104, unless otherw;se driven by the AND-gate 106, remains at a logical low. The A~D-gate 103 is thus disabled even when the comparator 102 indicates a match in addresses. The data store 20 could not, ~herefore, be enabled when ~he address of the memory module 1 is called. Memory module 1 (marked as substitute or spare module) has thus been inhibited from responding to its address.
In the present system, the (substitute) memory module 1 is ~-loaded at this point with data identical to that in the faulty memory module 3. Such data is obtained from a standby magnetic tape unit MT
in Figure 1 containing the ~ital system data. The tape unit itself could not be used instead of the faulty memory module 3 because data retrieval from tape is usually slow. 0f course, other means may be used in this process of loading the memory module 1 with the necessary data. For example, the present system being a telephone system, it could request that the data be transmitted over the telephone lines from a remote storage location.
As various memory module addresses appear on the address bus 100, the comparator 500 continuously compares them with the contents of the address register 400. When the address of the now faulty memory module 3 appears on the bus 100 the comparator indicates a match on the select-spare bus ~, thereby enabling the AND-gate 110 (the other input of which is at ~llU through the setting of spare marker 107), which in turn enables the OR-gate 111 and hence the data store 21 The memory module 1, marked as a spare, is thus selected to respond instead of the faulty memory module 3.
_ 5 _
inverts the logical high of the spare-in-use bus 30~ to a logical low, and hence, the output of the OR-gate 104, unless otherw;se driven by the AND-gate 106, remains at a logical low. The A~D-gate 103 is thus disabled even when the comparator 102 indicates a match in addresses. The data store 20 could not, ~herefore, be enabled when ~he address of the memory module 1 is called. Memory module 1 (marked as substitute or spare module) has thus been inhibited from responding to its address.
In the present system, the (substitute) memory module 1 is ~-loaded at this point with data identical to that in the faulty memory module 3. Such data is obtained from a standby magnetic tape unit MT
in Figure 1 containing the ~ital system data. The tape unit itself could not be used instead of the faulty memory module 3 because data retrieval from tape is usually slow. 0f course, other means may be used in this process of loading the memory module 1 with the necessary data. For example, the present system being a telephone system, it could request that the data be transmitted over the telephone lines from a remote storage location.
As various memory module addresses appear on the address bus 100, the comparator 500 continuously compares them with the contents of the address register 400. When the address of the now faulty memory module 3 appears on the bus 100 the comparator indicates a match on the select-spare bus ~, thereby enabling the AND-gate 110 (the other input of which is at ~llU through the setting of spare marker 107), which in turn enables the OR-gate 111 and hence the data store 21 The memory module 1, marked as a spare, is thus selected to respond instead of the faulty memory module 3.
_ 5 _
Claims (4)
PROPERTY OR PRIVILEGE IS CLAIMED ARE DEFINED AS FOLLOWS:
1. In a data processing system having a plurality of separately callable memory modules each having an address, a method for substituting one memory module of low priority for another memory module of higher priority, should the latter become faulty while said system is in operation, comprising the steps of:
(a) electronically marking one memory module as a substitute module;
(b) storing into a register the address of another memory module upon detection of a fault therein, and transmitting a permanent spare-in-use signal to each of said memory modules;
(c) transmitting a match signal to all memory modules upon occurrence of a match between a called memory module address and the address in said register; and (d) through logic circuits in each of said memory modules:
(i) preventing access to said another memory module when called in the presence of a spare-in-use signal;
(ii) preventing access to said one memory module when called and the spare-in-use signal is present; and (iii) permitting access to said one memory module only in the presence of both the spare-in-use signal and said match signal.
(a) electronically marking one memory module as a substitute module;
(b) storing into a register the address of another memory module upon detection of a fault therein, and transmitting a permanent spare-in-use signal to each of said memory modules;
(c) transmitting a match signal to all memory modules upon occurrence of a match between a called memory module address and the address in said register; and (d) through logic circuits in each of said memory modules:
(i) preventing access to said another memory module when called in the presence of a spare-in-use signal;
(ii) preventing access to said one memory module when called and the spare-in-use signal is present; and (iii) permitting access to said one memory module only in the presence of both the spare-in-use signal and said match signal.
2. The method of claim 1 further comprising after step (b) the step of loading said one memory module from a standby data store with data substantially identical to that originally stored in said another memory module.
3. The method of claim 1 further comprising the step of loading said one memory module from a data source after fault detection in said another memory module with data substantially identical to that originally stored in the latter.
4. The method of claims 2 or 3 wherein any data stored in said one memory module is not preserved after said loading step.
Priority Applications (8)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CA213,526A CA1053352A (en) | 1974-11-12 | 1974-11-12 | Method for providing a substitute memory module in a data processing system |
| GB44698/75A GB1512220A (en) | 1974-11-12 | 1975-10-29 | Method of providing a substitute memory module |
| NL7512713A NL7512713A (en) | 1974-11-12 | 1975-10-30 | METHOD OF PROVIDING A SUBSTITUTE MEMORY MODULE IN A DATA PROCESSING SYSTEM. |
| JP13421075A JPS5412373B2 (en) | 1974-11-12 | 1975-11-10 | |
| FR7534509A FR2291544A1 (en) | 1974-11-12 | 1975-11-12 | METHOD FOR PROVIDING A RESERVE MEMORY MODULE IN A DATA PROCESSING DEVICE |
| SE7512711-8A SE413949B (en) | 1974-11-12 | 1975-11-12 | PLACE IN A DATA PROCESSING SYSTEM WITH A MULTIPLE MEMORY MODULE TO REPLACE A WRONG MODULE TO ANOTHER |
| DE19752550805 DE2550805A1 (en) | 1974-11-12 | 1975-11-12 | PROCEDURE FOR REPLACING A MEMORY MODULE |
| SE7512711A SE413948B (en) | 1974-11-12 | 1977-09-07 | SET IN A DATA PROCESSING SYSTEM WITH A MULTIPLE MEMORY MODULE REPLACING A WRONG MODULE TO ANOTHER |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CA213,526A CA1053352A (en) | 1974-11-12 | 1974-11-12 | Method for providing a substitute memory module in a data processing system |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CA1053352A true CA1053352A (en) | 1979-04-24 |
Family
ID=4101603
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CA213,526A Expired CA1053352A (en) | 1974-11-12 | 1974-11-12 | Method for providing a substitute memory module in a data processing system |
Country Status (7)
| Country | Link |
|---|---|
| JP (1) | JPS5412373B2 (en) |
| CA (1) | CA1053352A (en) |
| DE (1) | DE2550805A1 (en) |
| FR (1) | FR2291544A1 (en) |
| GB (1) | GB1512220A (en) |
| NL (1) | NL7512713A (en) |
| SE (2) | SE413949B (en) |
Families Citing this family (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| DE2741379A1 (en) * | 1977-09-14 | 1979-03-15 | Siemens Ag | COMPUTER SYSTEM |
| JPS5580164A (en) * | 1978-12-13 | 1980-06-17 | Fujitsu Ltd | Main memory constitution control system |
| JPS6272138A (en) * | 1985-09-26 | 1987-04-02 | Hitachi Electronics Eng Co Ltd | Wafer positioning retainer |
| FR2643993B1 (en) * | 1989-03-03 | 1991-05-17 | Bull Sa | METHOD FOR REPLACING MEMORY MODULES IN A COMPUTER SYSTEM AND COMPUTER SYSTEM FOR IMPLEMENTING THE METHOD |
| US7139942B2 (en) * | 2003-07-21 | 2006-11-21 | Sun Microsystems, Inc. | Method and apparatus for memory redundancy and recovery from uncorrectable errors |
-
1974
- 1974-11-12 CA CA213,526A patent/CA1053352A/en not_active Expired
-
1975
- 1975-10-29 GB GB44698/75A patent/GB1512220A/en not_active Expired
- 1975-10-30 NL NL7512713A patent/NL7512713A/en not_active Application Discontinuation
- 1975-11-10 JP JP13421075A patent/JPS5412373B2/ja not_active Expired
- 1975-11-12 DE DE19752550805 patent/DE2550805A1/en not_active Withdrawn
- 1975-11-12 SE SE7512711-8A patent/SE413949B/en not_active IP Right Cessation
- 1975-11-12 FR FR7534509A patent/FR2291544A1/en not_active Withdrawn
-
1977
- 1977-09-07 SE SE7512711A patent/SE413948B/en unknown
Also Published As
| Publication number | Publication date |
|---|---|
| JPS5171641A (en) | 1976-06-21 |
| FR2291544A1 (en) | 1976-06-11 |
| GB1512220A (en) | 1978-05-24 |
| SE7512711L (en) | 1976-05-13 |
| DE2550805A1 (en) | 1976-05-13 |
| SE7710060L (en) | 1979-03-08 |
| SE413949B (en) | 1980-06-30 |
| NL7512713A (en) | 1976-05-14 |
| SE413948B (en) | 1980-06-30 |
| JPS5412373B2 (en) | 1979-05-22 |
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