NL193012C - Three-state output circuit. - Google Patents

Description

1 193012

Three-state output circuit

The invention relates to a three-state output circuit comprising a data input terminal for receiving a data signal, which may have either a first state or a second state; a release input terminal for receiving either a release signal or a lock signal; an output terminal; a first output switching means having a first current treatment terminal connected to the output terminal, a second current treatment terminal connected to a first voltage potential, and a control terminal; a first supply means for supplying a selected voltage to the control terminal of the first output switching means in response to the data signal; a second output switching means having a first current treatment terminal connected to the output terminal, a second current treatment terminal connected to a second voltage potential, and a control terminal; a second supply means for supplying a selected voltage to the control terminal of the second output switching means in response to the data signal; a controller which responds to the blocking signal, wherein in response to the blocking signal the controller supplies a selected voltage to the control terminal of the first output switching member and to the control terminal of the second output switching member, as a result of which the first and second output switching members switch off irrespective of the state of the data signal and the voltage applied by the first supply to the control terminal of the first output switching means, and regardless of the voltage applied by the second supplying means to the control terminal of the second output switching element, the control unit comprising a first blocking means, which a first current treatment terminal, which is connected to the control terminal of the first output switching means, a second current treatment terminal, which is connected to the second voltage potential, and a control terminal, which is connected to the release input terminal, a second blocking means, which first current treatment terminal connected directly to the control terminal of the second output switching means, a second current treatment terminal connected to the second voltage potential, and a control terminal connected to the release input terminal; and wherein the output circuit has a first output state, wherein in response to the enable signal and a data signal having the first state, the circuit is capable of supplying current to external circuits connected to the output terminal, having a second output state, in response to the enable signal and a data signal having the second state, the circuit can receive current from external circuits connected to the output terminal, and has a third output state, the circuit providing a high impedance to the external circuits connected to the output terminal in response to the blocking signal .

Such a circuit is known from European patent application 0,011,961.

In the known circuit, the second output switching device switches off immediately when it is actuated by the second blocking switch for this purpose, but the first output switching device does not switch off immediately when it is actuated for this purpose by the first blocking device and the first output switching device includes a transistor circuit comprising an NPN transistor and an emitter resistor, wherein, when driven by the first blocking switch, the first output switching device can only turn off after the transistor of the transistor circuit has been turned off, with the load on the control terminal of the first output circuit is removed by the emitter resistor from the transistor circuit.

This produces a propagation delay in the controller due to the fact that with respect to the first output switch, the data path is not independent of the turn-off control path.

The object of the invention is to improve the known circuit such that the said propagation delay (switching time) is substantially shortened, such that, when actuated for this purpose, the first and second output switching members both switch off immediately.

The invention provides for this purpose a circuit of the type mentioned in the preamble, characterized in that the first current treatment terminal of the first blocking switch is connected directly to the control terminal of the first output switching device.

For a better understanding of problems underlying the invention, first, referring to Figures 1 through 4 of the drawing, is a discussion of undocumented prior art 55.

Output circuits for use in integrated circuits are well known. Such output circuits receive low current input signals and buffer these input signals to 1193012 2 relatively high current output signals. Such circuits can absorb or deliver a fairly large amount of current. The output circuits receive input signals ranging from about 0 V (a logic zero or low signal) to about 3 V (logic one or "high" signal). The current, which is the input signal of an output stage, when a logic one input signal is received, is of the order of 0.5 mA. The output circuit buffers these input signals and provides output signals corresponding to about 0 V (logic zero) and about 5 V (logic one). The output circuits can receive about 100 mA (logic zero output signal) from external circuits and output about 50 mA (logic one output signal) to external circuits. Of course, output circuits can be made which can receive input signals with higher or lower currents and output or record higher or lower output currents.

In addition to these output circuits being able to supply and receive current, many output circuits are designed as three-state output circuits in which the output circuit can either supply current, or draw current, or provide a high impedance to its output terminal. Such three-state circuits are very useful because a large number of output circuits can be connected in parallel to a common bus and a single output circuit can be released from the number of output circuits at any given time. The blocked output stages provide high impedance and therefore have essentially no effect on the common bus.

A known three-state output circuit is shown in the circuit diagram of Figure 1. With 20 a logic one input signal applied to the ENABLE OUTPUT terminal 24, inverter 25 provides a logic zero output signal, which is applied to emitter 13b of NPN transistor 12 and to the cathode of diode 21. With a logic zero applied to emitter 13b of transistor 12, transistor 12 is turned on, providing a logic zero at the base of NPN transistor 20, which results in transistor 20 is blocked. With transistor 20 in the blocking, the base of NPN transistor 26 is raised to a logic zero level by resistor 23 connected between the base of transistor 26 and ground, so NPN transistor 26 enters the blocking, making output terminal 27 of ground disconnected. At the same time, diode 21 comes with a logic zero applied to its cathode, in forward setting and current flows from the positive power supply terminal 16 through resistor 15 and diode 21. Thus, the base of NPN transistor 18 is pulled up to a logic zero level, resulting in causes NPN-30 transistor 18 to turn off and therefore provides a logic zero signal to the base of NPN transistor 19, resulting in transistor 19 turning off.

With transistors 18 and 19 in the blocking, the output terminal 27 is effectively disconnected from the positive supply voltage VCC, which is connected to terminal 16. Thus, with a logic one MAKE OUTPUT FREE signal, the output terminal is disconnected from ground and the positive supply voltage VCC and the output buffer 10 of Figure 1 provides a high impedance to output terminal 27.

Conversely, with a logic zero CREATE OUTPUT FREE signal applied to terminal 24, inverter 25 supplies a logic one signal to its output line, causing the base-emitter junction 13b of transistor 12 to reverse. Similarly, the logic one output of inverter 25 causes diode 21 to be set in reverse device. At that time, the output 40 circuit 10 is inhibited and an output is provided on output terminal 27 which is the logical inverse of the input applied to terminal 11. For example, with a logic one input signal applied to terminal 11, transistor 12 locks out and the base-collector junction of transistor 12 is set forward, providing a logic one at the base of transistor 20. Thus, transistor 20 the conductor, thereby providing a base current to transistor 26, which results in transistor 26 entering the conductor. With transistor 20 in the conductor, the voltage of the base of transistor 18 is insufficient to cause transistor 18 to conduct and, with transistor 18 in the blocking, transistor 19 does not receive enough base current to conduct. come. Thus, transistors 18 and 19 are in the block. With transistor 26 in the conductor and transistors 18 and 19 in the blocking, output terminal 27 is effectively grounded and 50 is effectively disconnected from the positive supply voltage VCC connected to terminal 16. thus, in response to a logic zero CREATE OUTPUT FREE signal and a logic one data input signal, the output signal is logic zero.

Inversely, with a logic zero input signal applied to terminal 11, NPN transistor 12 is turned on, providing a logic zero at the base of transistor 20, causing transistor 20 to trip. With transistor 20 in the blocking, transistor 26 does not receive a basic drive and thus transistor 26 remains in the blocking. With further transistor 20 in the blocking, the base of NPN transistor 18 is high and thus transistor 18 conducts. With transistor 18 in the 193012 conductor, base current is applied to transistor 19, and transistor 19 enters the conductor. With transistor 19 in the conductor and transistor 26 in the blocking, output terminal 27 is effectively connected to the positive supply voltage VCC, which is connected to terminal 16 and is effectively disconnected from ground. The truth table, which illustrates the operation of the output circuit 10 of Figure 1, is provided in Table 1, 5 where É represents the MAKE OUTPUT FREE signal.

TABLES 1, 2, 3

OE D Z

10 - 0 0 1 0 1 o 1 0 High impedance 1 1 High impedance 15 -

It is very important that output circuit 10 is constructed so that the propagation delay between receiving a CREATE OUTPUT FREE signal at terminal 24 and a data input signal at terminal 11 and the generation of an output signal at terminal 27 in response to the CREATE OUTPUT FREE and 20 data input signal is as small as possible. For this reason, transistors 12, 20, 18 and 26 in the circuit of Figure 1 include Schottky transistors, and diode 21 is a Schottky diode, because Schottky transistors and diodes have an extremely short turn-off time. Transistor 19 is not a Schottky transistor because the voltage on the collector of transistor 19 is always about 0.3 volts (i.e. the voltage between the collector and the emitter of saturated Schottky transistor 18), which is higher than the voltage 25 from the base of transistor 19, thereby preventing saturation of transistor 19. Since transistor 19 does not saturate, transistor 19 can be a non-Schottky transistor since the switching speed of an unsaturated bipolar transistor is sufficiently high. Importantly, when the CLEAR OUTPUT signal applied to terminal 24 switches from a logic zero to a logic one, the output of inverter 25 switches from a logic one to a logic zero and Schottky diode 21 conducts 30 , preventing transistors 18 and 19 from entering the conduction. At the same time, the logic zero output signal provided by inverter 25 causes transistor 12 to turn on, causing transistor 26 to turn off. However, before transistor 26 is turned on, transistor 12 should be on and transistor 20 should be on and resistor 23 should keep the base of transistor 26 low enough to cause transistor 26 to turn on. blockage is coming. Although transistors 18 and 19 are quickly stalled in response to a high MAKE OUTPUT FREE signal, transistor 26 is not so likely to stall. Accordingly, the overall propagation delay between the reception of a logic one MAKE OUTPUT FREE signal on terminal 24 and the generation of a high impedance state on output terminal 26 is quite long, typically of the order of 20 nanoseconds for a three-state output circuit 40 , which dissipates about 25 mW and is manufactured using bipolar junction separation technology (whereby electrical separation between elements within the integrated circuit is provided by reverse bi-polar junctions).

Another known three-state output buffer is shown in the circuit diagram of Figure 2. The operation of output buffer 20 is similar to output buffer 10 of Figure 1 and therefore will not be described in detail. In response to a logic ONE CREATE OUTPUT signal at input terminal 23, however, inverter 24 provides logic zero output to the cathodes of Schottky diodes 22 and 29. Schottky diode 29 keeps the base of transistor 31 low in an identical manner to Schottky diode 21 keeps the base of transistor 18 low in the circuit of Figure 1. Furthermore, just like in the circuit of Figure 1, the logic zero output of inverter 24 results in transistor 25 and 50 transistor 28 becoming blocked and therefore no basic control to conduct transistor 35, which results in transistor 35 becoming blocked. However, as in output buffer 10 of Figure 1, there is a relatively long propagation delay between the reception of a logic one MAKE OUTPUT FREE signal at terminal 23 and the blocking of transistor 35, because this signal is passed through inverter 24, Schottky diode 22 and transistors 25 and 28 propagate before resistor 30 begins to pull down the base of transistor 35 55. Accordingly, the propagation delay between the reception of a logic one MAKE OUTPUT FREE signal and the generation of a high impedance state on output terminal 36 is approximately the same as for the output circuit 10 of Figure 1 for a comparable power consumption and a similar manufacturing technology. The truth table showing the operation of output buffer 20 is given in Table 2.

Yet another known output buffer is shown in Figure 3. The operation of output buffer 30 is similar to the operation of output buffers 10 and 20 of Figures 1 and 2, respectively, and will not be described in detail. As in the case of output buffers 10 and 20, however, the propagation delay between the reception of a logic one MAKE OUTPUT signal and the blocking of transistor 46 is quite long, because transistors 33, 41 and 42 must switch before transistor 46 is pulled down by resistor 47. The truth table showing the operation of output buffer 30 of Figure 3 is shown in Table 3.

Another known type of output buffer is the so-called open collector output buffer, such as the open collector output buffer 40 shown in figure 4. Unlike the three-state circuitry of FIGS. 1, 2 and 3, the open collector output buffer is not capable of delivering current, but is merely capable of drawing current or providing a high impedance at output terminal 54. Open collector output buffer 40 is blocked by a logic one MAKE OUTPUT 15 FREE signal, which is applied to input terminal 50. The logic high MAKE OUTPUT FREE signal on terminal 50 is buffered by buffer 51, causing NPN transistor 53 conducts, grounding the base of output transistor 49. With the base of transistor 49 grounded, transistor 49 locks and the high impedance is provided at output terminal 54 regardless of the value of the data input signal applied to input terminals 41. The truth table 20 for the open collector output buffer of Figure 4 is given in Table 4, TABLE 4

OE D Z

25 - 0 0 Open collector 0 1 0 1 0 Open collector 1 1 Open collector 30 - where OE represents the MAKE OUTPUT FREE signal.

A drawback of known circuits described above is the rather long propagation delay.

The invention will now be described in more detail with reference to the drawing, in which: Figure 1 is a circuit diagram of a three-state buffer circuit according to the prior art; Figure 2 is a circuit diagram of another prior art three-state buffer circuit; Fig. 3 is a circuit diagram of yet another prior art three-state buffer circuit; Figure 4 is a circuit diagram of a prior art open collector buffer circuit; and Figure 5 is a circuit diagram of a present three-state buffer circuit.

45

As shown in Figure 5, output buffer 50 includes an NPN transistor 60, the emitter of which is connected to output terminal 58 and the collector is connected through resistor 56 to a positive supply voltage VCC connected to terminal 55. The base of transistor 60 is connected through resistor 61 and Schottky diode 62 to the emitter of transistor 60 to provide a current path for discharging the 50 base of transistor 60 when transistor 59 locks, causing basic driving of transistor 60 will be removed. NPN transistor 59 has its collector connected to the collector of transistor 60 and its emitter connected to the base of transistor 60, and thus transistors 59 and 60 form a Darlington pair. The base of transistor 59 receives a signal that controls the operation of transistors 59 and 60 and thus controls whether or not current will be delivered through resistor 56 and 55 transistor 60 at output terminal 58. Output buffer 50 also includes transistor 63, the collector of which is connected to the output terminal 58, the emitter is grounded and the base is connected to receive an input signal, which controls the operation of transistor 63 and thus controls whether or not current will be drawn from output terminal 58 via transistor 63. When output terminal 58 is to be in the high impedance state, the base of transistor 59 is pulled down by the operation of transistor 65. When output terminal 58 is to be in the high impedance state, similarly, the base of transistor 63 is pulled down by the operation of transistor 67. This is in direct contrast to the known three-state buffer circuits, in which the base of tr ansistor 63 is not pulled down by a specific blocking transistor 67, but instead is pulled down by the operation of other elements, which also serve to propagate the data input signal. For example, when a logic one CREATE OUTPUT signal is applied to terminal 150, buffer 151 provides a logic one signal to resistors 64 and 66. With 10 resistors 64 and 66 connected to a logic one or high signal, the base emitter is switched gene of transistors 65 and 67 are biased forward and thus transistors 65 and 67 are turned on. With transistors 65 and 67 in the conductor, the bases of transistors 59 and 63 are pulled down, and thus transistors 59, 60 and 63 become blocked, providing a high impedance at output terminal 58. It is important that the propagation delay between the reception of a logic one make output free signal at input terminal 150 and the bases of transistors 59 and 63 is equivalent to one gate delay, the gate delay being provided by the single gate formed by buffer 51 and transistors 65 and 67. In response to a logic one MAKE OUTPUT FREE signal, the output terminal 58 is set to the high impedance state after a very short propagation delay, a propagation delay much smaller than the propagation delay 20 between receiving a high MAKE OUTPUT FREE signal and the generation of a high impedance state at the output terminal of the known three-state buffer circuits.

In order to complete the description of the operation of the output buffer 50, when a low MAKE OUTPUT FREE signal is applied to terminal 150 buffer 151, a low signal is provided to the bases of transistors 65 and 67 through resistors 64 and 66, respectively, resulting in that 25 transistors 65 and 67 become blocked. Thus, the bases of transistors 59 and 63 are not pulled down, and their operation is determined by the state of the input data signal applied to terminal 51. For example, with a logic zero input data signal applied to input terminal 51, transistors 52 and 53 become blocked. , which results in transistor 63 becoming blocked. Similarly, with transistor 53 in the blocking, the base of transistor 59 is connected to a high voltage through resistor 54 and transistor 59 is turned on. With transistor 59 in the conductor, transistor 59 supplies base current to transistor 60, which results in transistor 60 entering the conductor. With transistor 60 in the conductor, output terminal 58 is effectively connected to the positive supply voltage VCC, which is connected to terminal 55, and output terminal 58 is effectively disconnected from ground, which allows output terminal 58 to supply current through resistor 56 and transistor 60 to external circuits (not shown) connected to output terminal 58.

Conversely, with a logic one data input signal applied to input terminal 51, transistors 52 and 53 are turned on, thereby applying base current to transistor 63, causing transistor 63 to turn on and output terminal 58 has effective ground potential. With transistor 53 in the conductor, the base of transistor 59 is simultaneously kept low to prevent transistor 59 from entering the conductor. With transistor 59 in the blocking, no base current is supplied to transistor 60 and therefore transistor 60 remains in the blocking, thereby disconnecting output terminal 58 from the positive supply voltage VCC connected to terminal 55. Thus, output terminal 58 can draw current from external circuits (not shown) through transistor 63.

Thus, the present output circuit provides a three-state output buffer 45 with an extremely short propagation delay between the receipt of a blocking output signal (i.e., a high ENABLE OUTPUT signal) and the generation of a high impedance state on the output terminal of the three-state buffer. For a typical output circuit, constructed in accordance with the present measures using bipolar transition separation technology and dissipating approximately 25 mW of power, the propagation 50 delay between receipt of a logic ONE CLEAR OUTPUT (OE) signal on terminal 150 and the generation of a high impedance state on output terminal 58 is about 10 nanoseconds, about half the propagation delay of known output circuits. Of course, the actual propagation delay between the reception of a logic one ÖË signal and the generation of a high impedance state on output terminal 58 depends on the power dissipation of the circuit and 55 on the specific manufacturing technology used to fabricate a present output circuit.

Claims (1)

1193012 6 Three-state output circuit comprising a data input terminal for receiving a data signal, which may have either a first state or a second state; a release input terminal for receiving either a release signal or a lock signal; an output terminal; a first output switching means having a first current treatment terminal connected to the output terminal, a second current treatment terminal connected to a first voltage potential, and a second current treatment terminal connected to a first voltage potential, and a control terminal; a first supply means for supplying a selected voltage 10 to the control terminal of the first output switching means in response to the data signal; a second output switching means having a first current treatment terminal connected to the output terminal, a second current treatment terminal connected to a second voltage potential, and a control terminal; a second supply means for supplying a selected voltage to the control terminal of the second output switching means in response to the data signal; a controller which responds to the blocking signal, wherein in response to the blocking signal the controller supplies a selected voltage to the control terminal of the first output switching member and to the control terminal of the second output switching member, as a result of which the first and second output switching members switch off irrespective of the state of the data signal and the voltage applied by the first supply to the control terminal of the first output switching means and regardless of the voltage applied by the second supply means to the control terminal of the second output switching means, the control unit comprising a first blocking means, which has a first current treatment terminal connected to the control terminal of the first output switching means, a second current treatment terminal connected to the second voltage potential, and a control terminal connected to the release input terminal, a second blocking means which having a first current treatment terminal connected directly to the control terminal of the second output switching means, a second current treatment terminal connected to the second voltage potential, and a control terminal connected to the release input terminal; and wherein the output circuit has a first output state, wherein in response to the enable signal and a data signal having the first state, the circuit can supply current to external circuits connected to the output terminal, having a second output state, in response to the enable 30 signal and a data signal having the second state, the circuit can draw current from external circuits connected to the output terminal, and has a third output state, in response to the blocking signal the circuit provides a high impedance to external circuits connected to the output terminal characterized in that the first current treatment terminal of the first interlock switch is connected directly to the control terminal of the first output switch. Hereby 3 sheets drawing