GB2128432A

GB2128432A - Improvements in or relating to a tri-state output circuit

Info

Publication number: GB2128432A
Application number: GB08321748A
Authority: GB
Inventors: Sing Y Wong
Original assignee: Monolithic Memories Inc
Current assignee: Monolithic Memories Inc
Priority date: 1982-09-28
Filing date: 1983-08-12
Publication date: 1984-04-26
Also published as: GB2128432B; FR2533780A1; DE3335133A1; FR2533780B1; GB8321748D0; JPS5980022A; NL8302933A; NL193012C; NL193012B; DE3335133C2

Abstract

A tri-state output buffer circuit (50) includes means for quickly turning off both the sourcing and the sinking output transistors (60, 63) of the buffer in response to an output disable signal. The circuit causes the sinking output transistor to be disabled after a minimum of gate delays after the receipt of an output disable signal, thereby providing a high impedance on the output terminal (58) after an extremely short time delay after the receipt of an output disable signal. <IMAGE>

Description

SPECIFICATION Improvements in or relating to an output circuit This invention relates to electronic circuits, and more particularly to output circuits which are particularly useful in integrated circuit devices.

Output circuits for use in integrated circuits are well known in the prior art. Such output circuits typically receive low current input signals and buffer these input signals to relatively high current output signals. Such circuits are capable of sinking or sourcing a rather large amount of current. Typically, such output circuits receive input signals which vary from approximately zero volts (a logical 0 or low signal) to approximately three volts (logical 1 or "high" signal). The current which is the input to an output stage when a logical 1 input signal is received is typically on the order of 0.5 milliamps. The output circuit buffers these input signals and provides output signals corresponding to approximately zero volts (logical zero) and approximately 5 volts (logical one).

Such output circuits are capable of sinking approximately 100 milliamps (logical zero output) from external circuitry and sourcing approximately 50 milliamps (logical one output signal) to external circuitry. Of course, such output circuits can be made which are capable of receiving higher or lower input signal currents and capable of sourcing or sinking higher or lower output currents.

In addition to being able to source and sink current, many output circuits are designed to be the so-called "tri-state" output circuits wherein the output circuit is either capable of sourcing current, sinking current, or providing a high impedance on its output terminal. Such tri-state circuits are very useful in that a large number of output circuits can be connected in parallel to a common bus, and a single one of the plurality of output circuits enabled at any given time. The disabled output stages provide a high impedance and thus have essentially no effect on the common bus.

One such tri-state output circuit is shown on the schematic diagram of Figure 1. With a logical one input signal applied to the OUTPUT ENABLE terminal 24, inverter 25 provides a logical zero output signal, which is applied to emitter 1 3b of NPN transistor 12 and to the cathode of diode 21.

With a logical zero applied to emitter 1 3b of transistor 12, transistor 12 turns on, thus providing a logical zero to the base of NPN transistor 20, thus causing transistor 20 to turn off. With transistor 20 turned off, the base of NPN transistor 26 is pulled to a logical zero level by resistor 23 connected between the base of transistor 26 and ground. Thus, NPN transistor 26 turns off, disconnecting output terminal 27 from ground. Simultaneously, with a logical zero applied to the cathode of diode 21, diode 21 is forward biased and current flows from the positive supply terminal 1 6 through resistor 1 5 and diode 21.Thus, the base of NPN transistor 18 is pulled to a logical zero level, causing NPN transistor 1 8 to turn off and thus providing a logical zero signal to the base of NPN transistor 19, causing transistor 1 9 to turn off. With transistors 18 and a 9 turned off, the output terminal 27 is effectively disconnected from the positive supply voltage VCC connected to terminal 1 6. Thus, with a logical one OUTPUT ENABLE signal, the output terminal is disconnected from ground and the positive supply voltage VCC and the output buffer 10 of Figure 1 provides a high impedance on output terminal 27.

Conversely, with a logical zero OUTPUT ENABLE signal applied to terminal 24, inverter 25 provides logical one signal on its output lead, thus causing the base-emitter 1 3b junction of transistor 12 to be reverse biased. Similarly, the logical one output signal from inverter 25 causes diode 21 to be reverse biased. In this event, the output circuit 10 is enabled and will provide an output signal on output terminal 27 which is the logical inverse of the input signal applied to terminal 11. For example, with logical one input signal applied to terminal 11. transistor 12 is turned off, and the base-collector junction of transistor 12 is forward biased, thus providing a logical one to the base of transistor 20. Transistor 20 thus turns on, thus providing base current to transistor 26, thus causing transistor 26 to turn on.Simultaneously, with transistor 20 on, the voltage on the base of transistor 1 8 is insufficient to cause transistor 18 to turn on, and with transistor 1 8 turned off, transistor 1 9 does not receive sufficient base current to turn on. Thus, transistors 1 8 and 1 9 are off. With transistor 26 on, and transistors 18 and 1 9 off, output terminal 27 is effectively connected to ground and is effectively disconnected from the positive supply voltage VCC connected to terminal 1 6. Thus, in response to a logical zero OUTPUT ENABLE signal and a logical one data input signal, the output signal is a logical zero.

Conversely, with a logical zero input signal applied to terminal 11, NPN transistor 12 turns on, thus providing a logical zero to the base of transitor 20, thus causing transistor 20 to turn off.

With transistor 20 off, transistor 26 does not receive base drive, and thus transistor 26 remains off. Furthermore, with transistor 20 off, the base of NPN transistor 18 is high, and thus transistor 1 8 turns on. With transistor 1 8 on, base current is supplied to transistor 19, and transistor 1 9 turns on. With transistor 1 9 on and transistor 26 off, output terminal 27 is effectively connected to the positive supply voltage VCC connected to terminal 1 6 and is effectively disconnected from ground.The truth table depicting the operation of output circuit 10 of Figure 1 is provided in Table 1: Tables 1,2,3 OE D Z 0 0 1 0 1 0 1 0 High impedance 1 1 High impedance It is very important that output circuit 10 be constructed such that the propagation delay between the receipt of an OUTPUT ENABLE signal on terminal 24 and a data input signal on terminal 11 and the generation of an output signal on terminal 27 in response to the OUTPUT ENABLE and data input signals, is as small as possible. For this reason, transistors 12, 20, 1 8, and 26 in the circuit of Figure 1 comprise Schottky transistors, and diode 21 is a Schottky diode, because Schottky transistors and diodes have an extremely short turn off time.Transistor 1 9 is not a Schottky transistor because the voltage on the collector of transistor 1 9 is always approximately 0.3 volts (i.e. the voltage between the collector and the emitter of saturated Schottky transistor 18) higher than the voltage on the base of transistor 19, thereby preventing saturation of transistor 1 9. Because transistor 1 9 does not saturate, transistor 1 9 can be a non-Schottky transistor since the switching speed of a nonsaturated bipolar transistor is sufficiently fast.

Of importance, when the OUTPUT ENABLE signal applied to terminal 24 switches from a logical zero to a logical one, the output signal from inverter 25 switches from a logical one to a logical zero, and Schottky diode 21 turns on, thereby preventing transistors 1 8 and 1 9 from turning on. At the same time, the logical zero output signal provided by inverter 25 causes transistor 12 to turn on, thus causing transistor 26 to turn off. However, before transistor 26 turns off, transistor 12 must turn on, and transistor 20 must turn off, and resistor 23 must hold the base of transistor 26 sufficiently low to cause transistor 26 to turn off. Accordingly, while transistors 1 8 and 19 turn off rapidly in response to a high OUTPUT ENABLE signal, transistor 26 does not turn off nearly as rapidly.Accordingly, the overall propagation delay between the receipt of a logical one OUTPUT ENABLE signal on terminal 24 and the generation of a high impedance state on output terminal 27 is rather long, typically on the order of 20 nanoseconds for a tri-state output circuit dissipating approximately 25 milliwatts, and which is fabricated using bipolar junction isolation technology (where electrical isolation between elements within the integrated circuit is provided by reverse biased bipolar junctions).

Another prior art tri-state output buffer 20 is shown in the schematic diagram of Figure 2. The operation of output buffer 20 is similar to output buffer 10 of Figure 1, and thus will not be described in detail. However, in response to a logical one OUTPUT ENABLE signal on input terminal 23, inverter 24 provides logical zero output signal to the cathodes of Schottky diodes 22 and 29. Schottky diode 29 holds the base of transistor 31 low in an identical fashion as Schottky diode 21 holds the base of transistor 1 8 low in the circuit of Figure 1. Furthermore, as in the circuit of Figure 1, the logical zero output signal from inverter 24 causes transistor 25 and transistor 28 to turn off and thus removes base drive to transistor 35, thus causing transistor 35 to turn off.However, as in output buffer 10 of Figure 1, there is a relatively long propagation delay between the receipt of a logical one OUTPUT ENABLE signal on terminal 23 and the turn off of transistor 35, because this signal must be propagated through inverter 24, Schottky diode 22, and transistors 25 and 28, before resistor 30 begins to pull the base of transistor 35 low. Accordingly, the propa ation delay between the receipt of a logical one OUTPUT ENABLE signal and the generation of a high impedance state on output terminal 36 is approximately the same as for the output circuit 10 of Figure 1 ,for a comparable power consumption and fabrication technology. The truth table depicting the operation of output buffer 20 is given in Table 2.

Yet another tri-state output buffer 30 is shown in Figure 3. The operation of output buffer 30 is similar to the operation of output buffers 10 and 20 of Figures 1 and 2, respectively, and thus will not be described in detail. However, as in the case with output buffers 10 and 20, the propagation delay between the receipt of a logical one OUTPUT ENABLE signal and the turning off of transistors 46 is rather long, because transistors 33, 41, and 42 must switch before transistor 46 is pulled low by resistor 47. The truth table depicting the operation of output buffer 30 of Figure 3 is given in Table 3.

Another type of output buffer is the so called "open collector" output buffer, such as the open collector output buffer 40 shown in Figure 4.

Unlike the tri-state circuits of Figures 1,2 and 3, open collector output buffer 40 is unable to source current, but is merely able to either sink current or provide a high impedance on output terminal 54. Open collector output buffer 40 is disabled by a logical one OUTPUT ENABLE signal applied to input terminal 50. The logical high OUTPUT ENABLE signal on terminal 50 is buffered by buffer 51, and thus causes NPN transistor 53 to turn on, thus grounding the base of output transistor 49. With the base of transistor 49 grounded, transistor 49 turns off, and the high impedance is provided at output terminal 54, regardless of the value of the data input signal applied to input terminals 41. The Truth Table for the open collector output buffer of Figure 4 is given in Table 4.

Table 4 OE D Z 0 O Open collector 0 1 0 1 0 Open collector 1 1 Open collector According to this invention there is provided a tri-state output circuit comprising: a data input terminal for receiving a data signal capable of having either a first state or a second state; an enable input terminal for receiving either an enable signal or a disable signal; an output terminal; a first output switch means having a first current handling terminal connected to said output terminal, a second current handling terminal connected to a first voltage potential, and a control terminal; first means for supplying a selected voltage to said control terminal of said first output switch means in response to said data signal; and a second output switch means having a first current handling terminal connected to said output terminal, a second current handling terminal connected to a second voltage potential, and a control terminal; a second means for supplying a selected voltage to said control terminal of said second output switch means in response to said data signal; a control means independent from said first and said second means for supplying, said control means being responsive to said disable signal to supply a selected voltage to said control terminal of said first output switch means, thus causing said first output switch means to turn off irrespective of the state of said data signal and the voltage applied to said control terminal of said first output switch means by said first means for supplying and irrespective of the voltage applied to said control terminal of said second output switch means by said second means for supplying, and wherein said output circuit has a first state wherein, in response to said enable signal and a data signal having said first state, said circuit is capable of sourcing current to external circuitry connected to said output terminal and a second output state wherein, in response to said enable signal and a data signal having said second state, said circuit is capable of sinking current from external circuitry connected to said output terminal, and a third output state wherein, in response to said disable signal, said circuit provides a high impedance to external circuitry connected to said output terminal.

Said first output switch means may be a bipolar transistor, and said second output switch means may be a bipolar transistor or a Schottky transistor.

Said control means independent from said first and said second means for supply may comprise: a first disable switch means having a first current handling terminal connected to said control terminal of said first output switch means, a second current handling terminal connected to said second voltage potential, and a control terminal connected to said enable input terminal; and a second disable switch means having a first current handling terminal connected to said control terminal of said second output switch means, a second current handling terminal connected to said second voltage potential, and a control terminal connected to said enable input terminal.

Said first and second disable switch means may comprise bipolar transistors or may comprise Schottky transistors.

Preferably said control terminal of said first disable switch means and said control means of said second disable switch means are connected to said enable input terminal through a buffer means.

According to another aspect of this invention there is provided a tri-state output circuit comprising: a data input terminal for receiving a data signal capable of having either a first state or a second state; an enable input terminal for receiving either an enable signal or a disable signal; an output terminal; means for sinking current from said output terminal; means for sourcing current to said output terminal; first means for controlling said means for sinking current which, in response to a data input signal of said first state, causes current to be sunk from said output terminal; second means for controlling said means for sourcing current which, in response to a data input signal of said second state, causes current to be "sourced" to said output terminal; and a control means independent from said first and said second means for controlling, said control means being responsive to said disable signal, wherein in.response to said disable signal, said control means causes said means for sinking current and said means for sourcing current to be disabled, thereby providing a high impedance on said output terminal.

In accordance with the teachings of this invention, a novel tri-state output buffer circuit is provided which includes means for quickly turning off both the sourcing and the sinking output transistors of the buffer in response to an output disable signal. In contrast to prior art tri-state output buffers, the circuit constructed in accordance with this invention causes the sinking output transistor to be disabled with a minimum of gate delays following the receipt of an output disable signal. This circuit thus provides a high impedance on the output terminal in an extremely short time foliowing the receipt of an output disable signal.

In order that the invention may be more readily understood, and so that further features thereof may be appreciated, the invention will now be described by way of example with reference to the accompanying drawings in which: Figure 1 is a schematic diagram of a prior art tri-state buffer; Figure 2 is a schematic diagram of another prior art tri-state buffer circuit; Figure 3 is a schematic diagram of yet another prior art tri-state buffer circuit; Figure 4 is a schematic diagram of a prior art open collector buffer circuit; and Figure 5 is a schematic diagram of one embodiment of a tri-state buffer circuit constructed in accordance with the principals of this invention.

This invention will now be described with reference to the embodiment of this invention shown on the schematic diagram of Figure 5. As shown in Figure 5 an output buffer includes NPN transistor 60 having its emitter connected to output terminal 58, and its collector connected through resistor 56 to a positive voltage supply VCC connected to terminal 55. The base of transistor 60 is connected to the emitter of transistor 60 through resistor 61 and Schottky diode 62 in order to provide a current path to discharge the base of transistor 60 when transistor 59 turns off, thereby removing base drive from transistor 60. NPN transistor 59 has its collector connected to the collector of transistor 60 and its emitter connected to the base of transistor 60, and thus transistors 59 and 60 form a Darlington pair.The base of transistor 59 receives a signal which controls the operation of transistors 59 and 60 and thus controls whether current will be sourced through resistor 56 and transistor 60 to output terminal 58. Output buffer 50 also includes transistor 63 having its collector connected to output terminal 58, its emitter connected to ground, and its base connected to receive an input signal controlling the operation of transistor 63 and thus controlling whether current will be sinked from output terminal 58 through transistor 63. When output terminal 58 is to be in the high impedance state, the base of transistor 59 is pulled low by the operation of transistor 65.

Similarly, when output terminal 58 is to be in the high impedance state, the base of transistor 63 is pulled low by the operation of transistor 67. This is in direct contrast to the prior art tri-state buffer circuits wherein the base of transistor 63 is not pulled down by a specific disabling transistor 67, but rather is pulled down by the operation of other elements which also serve to propagate the data input signal. For example, when a logical one OUTPUT ENABLE signal is applied to terminal 150, buffer 1 51 provides a logical one signal to resistors R4 and R5. With resistors R4 and R5 connected to a logical one or high signal, the base-emitter junctions of transistors 65 and 67 are forward biased, and thus transistors 65 and 67 turn on.With transistors 65 and 67 turned on, the bases of transistors 59 and 63 are pulled low, and thus transistors 59, 60, and 63 turn off, thereby providing a high impedance to output terminal 58. Of importance, the propagation delay between the receipt of a logical one output enable signal on input terminal 1 50 and the bases of transistors 59 and 63 is equivalent to one gate delay, the gate delay provided by the single gate formed by buffer 151 and transistors 65 and 67.

Thus, in response to a logical one OUTPUT ENABLE signal, the output terminal 58 is set to the high impedance state after a very short propagation delay, a propagation delay which is much less than the propagation delay between the receipt of a high OUTPUT ENABLE signal and the generation of a high impedance state on the output terminal of prior art tri-state buffer.

To complete the description of the operation of output buffer 50, when a low OUTPUT ENABLE signal is applied to terminal 150, buffer 151 provides a low signal of the bases of transistors 65 and 67 through resistors 64 and 66, respectively, thus causing transistors 65 and 67 to turn off. The bases of transistors 59 and 63 are thus not pulled low, and their operation is determined by the state of the input data signal applied to terminal 51. For example, with a logical zero input data signal applied to input terminal 51, transistors 52 and 53 turn off, thus causing transistor 63 to turn off. Similarly, with transistor 53 off, the base of the transistor 59 is connected to a high voltage through resistor 54, and transistor 59 turns on.

With transistor 59 on, transistor 59 supplies base current to transistor 60, thus causing transistor 60 to turn on. With transistor 60 on, output terminal 58 is effectively connected to the positive supply voltage VCC connected to terminal 55, and output terminal 58 is effectively disconnected from ground, thus allowing output terminal 58 to source current through resistor 56 and transistor 60 to external circuitry (not shown) connected to output terminal 58.

Conversely, with a logical one data input signal applied to input terminal 51, transistors 52 and 53 turn on, thus applying base current to transistor 63 causing transistor 63 to turn on thus grounding output terminal 58. Simultaneously, with transistor 53 on, the base of transistor 59 is held sufficiently low to prevent transistor 59 from turning on. With transistor 59 off, base current is not supplied to transistor 60, and thus transistor 60 remains off, thereby disconnecting output terminal 58 from the positive supply voltage VCC connected to terminal 55. Thus output terminal 58 is capable of sinking current from external circuitry (shown) through transistor 63.

Thus, in accordance with the teachings of this invention, a tri-state output buffer is provided having an extremely short propagation delay between the receipt of an output disable signal (i.e., a high OUTPUT ENABLE signal) and the generation of a high impedance state on the output terminal of the tri-state buffer. For a typical output circuit constructed in accordance with this invention utilizing bipolar junction isolated technology and dissipating approximately 25 milliwatts of power, the propagation delay between the receipt of a logical one OUTPUT ENABLE (OE) signal on terminal 1 50 and the generation of a high impedance state on output terminal 58 is approximately 10 nanoseconds, approximately half the propagation delay of prior art output circuits. Of course, the actual propagation delay between the receipt of a logical one OE signal and the generation of a high impedance state on output terminal 58 is dependent on the power dissipation of the circuit and the specific processing technology used to fabricate an output circuit constructed in accordance with this invention.

Claims

1. A tri-state output circuit comprising: a data input terminal for receiving a data signal capable of having either a first state or a second state; an enable input terminal for receiving either an enable signal or a disable signal; an output terminal; a first output switch means having a first current handling terminal connected to said output terminal, a second current handling terminal connected to a first voltage potential, and a control terminal; first means for supplying a selected voltage to said control terminal of said first output switch means in response to said data signal; and a second output switch means having a first current handling terminal connected to said output terminal, a second current handling terminal connected to a second voltage potential, and a control terminal; a second means for supplying a selected voltage to said control terminal of said second output switch means in response to said data signal; a control means independent from said first and said second means for supplying, said control means being responsive to said disable signal to supply a selected voltage to said control terminal of said first output switch means, thus causing said first output switch means to turn off irrespective of the state of said data signal and the voltage applied to said control terminal of said first output switch means by said first means for supplying and irrespective of the voltage applied to said control terminal of said second output switch means by said second means for supplying, and wherein said output circuit has a first output state wherein, in response to said enable signal and a data signal having said first state, said circuit is capable of sourcing current to external circuitry connected to said input terminal and a second output state wherein, in response to said enable signal and a data signal having said second state, said circuit is capable of sinking current from external circuitry connected to said output terminal, and a third output state wherein, in response to said disable signal, said circuit provides a high impedance to external circuitry connected to said output terminal.

2. A circuit as claimed in claim 1 wherein said first output switch means may be a bipolar transistor.

3. A circuit as claimed in claim 1 or claim 2 wherein said second output switch means is a bipolar transistor.

4. A circuit as claimed in claim 1 or claim 2 wherein said second output switch means is a Schottky transistor.

5. A circuit according to any one of the preceding claims wherein said control means independent from said first and said second means for supply comprises; a first disable switch means having a first current handling terminal connected to said control terminal of said first output switch means, a second current handling terminal connected to said second voltage potential, and a control terminal connected to said enable input terminal; and a second disable switch means having a first current handling terminal connected to said control terminal of said second output switch means, a second current handling terminal connected to said second voltage potential, and a control terminal connected to said enable input terminal.

6. A circuit according to claim 5 wherein said first and second disable switch means may comprise bipolar transistors.

7. A circuit according to claim 5 wherein said first and second disable switch means comprise Schottky transistors.

8. A circuit according to any one of claims 5 to 7 wherein said terminal of said first disable switch means and said control terminal of said second disable switch means are connected to said enable input terminal through a buffer means.

9. A tri-state output circuit comprising: a tristate output circuit comprising: a data input terminal for receiving a data signal capable of having either a first state or a second state; an enable input terminal for receiving either an enable signal or a disable signal; an output terminal; means for sinking current from said output terminal; means for sourcing current to said output terminal; first means for controlling said means for sinking current which, in response to a data input signal of said first state, causes current to be sunk from said output terminal; second means for controlling said means for sourcing current which, in response to a data input signal of said second state, causes current to be "sourced" to said output terminal; and a control means indpendent from said first and said second means for controlling, said control means being responsive to said disable signal, wherein in response to said disable signal, said control means causes said means for sinking current and said means for sourcing current to be disabled, thereby providing a high impedance on said output terminal.

10. A tri-state output circuit substantially as herein described with reference to Figure 5 of the accompanying drawings.

11. Any novel feature or combination of features disclosed herein.