MY171818A - Low profile leaded semiconductor package - Google Patents
Low profile leaded semiconductor packageInfo
- Publication number
- MY171818A MY171818A MYPI2014000562A MYPI2014000562A MY171818A MY 171818 A MY171818 A MY 171818A MY PI2014000562 A MYPI2014000562 A MY PI2014000562A MY PI2014000562 A MYPI2014000562 A MY PI2014000562A MY 171818 A MY171818 A MY 171818A
- Authority
- MY
- Malaysia
- Prior art keywords
- semiconductor package
- low profile
- package
- leaded semiconductor
- plastic body
- Prior art date
Links
- 239000004065 semiconductor Substances 0.000 title abstract 2
- 238000000034 method Methods 0.000 abstract 2
- 238000005476 soldering Methods 0.000 abstract 1
Classifications
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- H01L23/49805—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers the leads being also applied on the sidewalls or the bottom of the substrate, e.g. leadless packages for surface mounting
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- H01L2924/13—Discrete devices, e.g. 3 terminal devices
- H01L2924/1304—Transistor
- H01L2924/1306—Field-effect transistor [FET]
- H01L2924/13091—Metal-Oxide-Semiconductor Field-Effect Transistor [MOSFET]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/181—Encapsulation
Landscapes
- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Power Engineering (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- General Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- Manufacturing & Machinery (AREA)
- Geometry (AREA)
- Lead Frames For Integrated Circuits (AREA)
- Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
- Chemical & Material Sciences (AREA)
- Materials Engineering (AREA)
Abstract
In a semiconductor package a lead (43C) having a bottom surface coplanar with the flat bottom surface (42B) of the plastic body (42) extends outward at the bottom of the vertical side surface (42A) of the plastic body (42). The result is a package with a minimal footprint that is suitable for the technique known as ?wave soldering? that is used in relatively low-cost printed circuit board assembly factories. Methods of fabricating the package are disclosed.
Applications Claiming Priority (3)
Application Number | Priority Date | Filing Date | Title |
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US201361775540P | 2013-03-09 | 2013-03-09 | |
US201361775544P | 2013-03-09 | 2013-03-09 | |
US14/056,287 US9576884B2 (en) | 2013-03-09 | 2013-10-17 | Low profile leaded semiconductor package |
Publications (1)
Publication Number | Publication Date |
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MY171818A true MY171818A (en) | 2019-10-31 |
Family
ID=51686221
Family Applications (2)
Application Number | Title | Priority Date | Filing Date |
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MYPI2018700188A MY196641A (en) | 2013-03-09 | 2014-02-27 | Low Profile Leaded Semiconductor Package |
MYPI2014000562A MY171818A (en) | 2013-03-09 | 2014-02-27 | Low profile leaded semiconductor package |
Family Applications Before (1)
Application Number | Title | Priority Date | Filing Date |
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MYPI2018700188A MY196641A (en) | 2013-03-09 | 2014-02-27 | Low Profile Leaded Semiconductor Package |
Country Status (4)
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US (3) | US9576884B2 (en) |
CN (2) | CN104167395B (en) |
MY (2) | MY196641A (en) |
TW (1) | TWI618201B (en) |
Families Citing this family (37)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US10163766B2 (en) * | 2016-11-21 | 2018-12-25 | Semiconductor Components Industries, Llc | Methods of forming leadless semiconductor packages with plated leadframes and wettable flanks |
US11469205B2 (en) * | 2013-03-09 | 2022-10-11 | Adventive International Ltd. | Universal surface-mount semiconductor package |
KR101538543B1 (en) * | 2013-08-13 | 2015-07-22 | 앰코 테크놀로지 코리아 주식회사 | Semiconductor Device and Fabricating Method Thereof |
WO2015031711A1 (en) * | 2013-08-29 | 2015-03-05 | Robert Bosch Gmbh | Molded lead frame package with embedded die |
KR102153041B1 (en) * | 2013-12-04 | 2020-09-07 | 삼성전자주식회사 | Semiconductor device package and method of manufacturing the same |
US9379071B2 (en) * | 2014-04-17 | 2016-06-28 | Nxp B.V. | Single inline no-lead semiconductor package |
US9425130B2 (en) * | 2014-10-29 | 2016-08-23 | Nxp B.V. | Package with multiple I/O side-solderable terminals |
CN105679715B (en) * | 2014-11-17 | 2018-03-30 | 兴勤电子工业股份有限公司 | The thermistor that lies low with foot stool |
US20160172275A1 (en) * | 2014-12-10 | 2016-06-16 | Stmicroelectronics S.R.L. | Package for a surface-mount semiconductor device and manufacturing method thereof |
US9786585B2 (en) * | 2015-04-20 | 2017-10-10 | Nxp B.V. | Lead-frame |
MY181499A (en) * | 2015-05-04 | 2020-12-23 | Adventive Tech Ltd | Low-profile footed power package |
TWI588951B (en) * | 2015-07-24 | 2017-06-21 | 萬國半導體股份有限公司 | Package component and preparation method thereof |
US20170064821A1 (en) * | 2015-08-31 | 2017-03-02 | Kristof Darmawikarta | Electronic package and method forming an electrical package |
JP6646491B2 (en) * | 2016-03-24 | 2020-02-14 | サンデン・オートモーティブコンポーネント株式会社 | Electronic circuit device and inverter-integrated electric compressor having the same |
US10365303B2 (en) | 2016-04-28 | 2019-07-30 | Texas Instruments Incorporated | Shunt strip |
US20170323708A1 (en) | 2016-05-03 | 2017-11-09 | Texas Instruments Incorporated | Component sheet and method of singulating |
US10335875B2 (en) | 2016-05-26 | 2019-07-02 | Texas Instruments Incorporated | Methods and devices for dicing components from a sheet of copper alloy |
US10325878B2 (en) * | 2016-06-30 | 2019-06-18 | Kulicke And Soffa Industries, Inc. | Methods for generating wire loop profiles for wire loops, and methods for checking for adequate clearance between adjacent wire loops |
JP6870249B2 (en) * | 2016-09-14 | 2021-05-12 | 富士電機株式会社 | Semiconductor devices and methods for manufacturing semiconductor devices |
JP6283131B1 (en) * | 2017-01-31 | 2018-02-21 | 株式会社加藤電器製作所 | Electronic device and method for manufacturing electronic device |
US11004742B2 (en) * | 2017-03-19 | 2021-05-11 | Texas Instruments Incorporated | Methods and apparatus for an improved integrated circuit package |
US10636729B2 (en) * | 2017-06-19 | 2020-04-28 | Texas Instruments Incorporated | Integrated circuit package with pre-wetted contact sidewall surfaces |
US10665555B2 (en) | 2018-02-07 | 2020-05-26 | Win Semiconductors Corp. | Transition structure and high-frequency package |
US20200135632A1 (en) * | 2018-10-24 | 2020-04-30 | Texas Instruments Incorporated | Die isolation on a substrate |
CN111370382A (en) * | 2018-12-25 | 2020-07-03 | 恩智浦美国有限公司 | Hybrid lead frame for semiconductor die package with improved creepage distance |
US20200235067A1 (en) * | 2019-01-22 | 2020-07-23 | Texas Instruments Incorporated | Electronic device flip chip package with exposed clip |
JP7548714B2 (en) * | 2019-03-25 | 2024-09-10 | ローム株式会社 | Electronic device, method for manufacturing electronic device, and lead frame |
CN109935566A (en) * | 2019-03-29 | 2019-06-25 | 无锡红光微电子股份有限公司 | Modified SOT223 frame |
CN116390393A (en) * | 2019-06-28 | 2023-07-04 | 法雷奥汽车动力系统(上海)有限公司 | Module for reducing or eliminating noise and vibration problems and electronic equipment provided with same |
DE102019119390A1 (en) * | 2019-07-17 | 2021-01-21 | OSRAM Opto Semiconductors Gesellschaft mit beschränkter Haftung | HOUSING FOR AN OPTOELECTRONIC COMPONENT, METHOD FOR MANUFACTURING A HOUSING FOR AN OPTOELECTRONIC COMPONENT, OPTOELECTRONIC COMPONENT AND METHOD FOR MANUFACTURING AN OPTOELECTRONIC COMPONENT |
CN110491839A (en) * | 2019-07-31 | 2019-11-22 | 广东风华高新科技股份有限公司 | A kind of radio-frequency devices |
CN112490202A (en) * | 2019-09-12 | 2021-03-12 | 朋程科技股份有限公司 | Power device packaging structure |
TWI825546B (en) * | 2022-01-03 | 2023-12-11 | 美商矽成積體電路股份有限公司 | Package structure |
CN112331583B (en) * | 2020-10-14 | 2023-04-07 | 安徽科技学院 | Packaging device for MOSFET device production |
CN112645279B (en) * | 2020-12-23 | 2023-09-05 | 东南大学 | Packaging method of MEMS wind speed and direction sensor |
US20230068748A1 (en) * | 2021-08-31 | 2023-03-02 | Texas Instruments Incorporated | Leaded semiconductor device package |
WO2022179229A1 (en) * | 2021-12-02 | 2022-09-01 | 深圳麦克韦尔科技有限公司 | Heating element module and preparation method therefor, packaging module and electronic atomization device |
Family Cites Families (18)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US6084309A (en) * | 1992-10-20 | 2000-07-04 | Fujitsu Limited | Semiconductor device and semiconductor device mounting structure |
JP4208893B2 (en) * | 1997-02-27 | 2009-01-14 | 富士通マイクロエレクトロニクス株式会社 | Manufacturing method of semiconductor device |
JP3947292B2 (en) * | 1998-02-10 | 2007-07-18 | 大日本印刷株式会社 | Manufacturing method of resin-encapsulated semiconductor device |
JP2000114426A (en) * | 1998-10-07 | 2000-04-21 | Mitsui High Tec Inc | Single-sided resin sealing type semiconductor device |
JP3334864B2 (en) * | 1998-11-19 | 2002-10-15 | 松下電器産業株式会社 | Electronic equipment |
US6307755B1 (en) * | 1999-05-27 | 2001-10-23 | Richard K. Williams | Surface mount semiconductor package, die-leadframe combination and leadframe therefor and method of mounting leadframes to surfaces of semiconductor die |
US6891256B2 (en) | 2001-10-22 | 2005-05-10 | Fairchild Semiconductor Corporation | Thin, thermally enhanced flip chip in a leaded molded package |
DE102006021959B4 (en) | 2006-05-10 | 2011-12-29 | Infineon Technologies Ag | Power semiconductor device and method for its production |
DE102006034679A1 (en) | 2006-07-24 | 2008-01-31 | Infineon Technologies Ag | Semiconductor module with power semiconductor chip and passive component and method for producing the same |
CN100464415C (en) * | 2007-09-13 | 2009-02-25 | 江苏长电科技股份有限公司 | Non-pin packaging structure of semiconductor element and packaging technology thereof |
US7838339B2 (en) | 2008-04-04 | 2010-11-23 | Gem Services, Inc. | Semiconductor device package having features formed by stamping |
JP4892033B2 (en) * | 2009-05-13 | 2012-03-07 | 日立ケーブルプレシジョン株式会社 | Lead frame manufacturing method |
CN101694837B (en) * | 2009-10-17 | 2012-09-26 | 天水华天科技股份有限公司 | Packaging part with double-row pins and four flat and pin-free surfaces and production method thereof |
US20110115069A1 (en) | 2009-11-13 | 2011-05-19 | Serene Seoh Hian Teh | Electronic device including a packaging substrate and an electrical conductor within a via and a process of forming the same |
US8575006B2 (en) | 2009-11-30 | 2013-11-05 | Alpha and Omega Semiconducotr Incorporated | Process to form semiconductor packages with external leads |
JP5628549B2 (en) | 2010-04-27 | 2014-11-19 | 芝浦メカトロニクス株式会社 | Board bonding equipment |
US9831393B2 (en) * | 2010-07-30 | 2017-11-28 | Cree Hong Kong Limited | Water resistant surface mount device package |
US8513787B2 (en) | 2011-08-16 | 2013-08-20 | Advanced Analogic Technologies, Incorporated | Multi-die semiconductor package with one or more embedded die pads |
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2013
- 2013-10-17 US US14/056,287 patent/US9576884B2/en active Active
-
2014
- 2014-02-27 MY MYPI2018700188A patent/MY196641A/en unknown
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2017
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CN108364918B (en) | 2022-08-30 |
CN104167395B (en) | 2018-03-20 |
MY196641A (en) | 2023-04-26 |
US9793197B2 (en) | 2017-10-17 |
CN108364918A (en) | 2018-08-03 |
US20140306330A1 (en) | 2014-10-16 |
US20180040545A1 (en) | 2018-02-08 |
TW201501251A (en) | 2015-01-01 |
US10008438B2 (en) | 2018-06-26 |
US20170133304A1 (en) | 2017-05-11 |
TWI618201B (en) | 2018-03-11 |
US9576884B2 (en) | 2017-02-21 |
CN104167395A (en) | 2014-11-26 |
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