CN112490202A - Power device packaging structure - Google Patents
Power device packaging structure Download PDFInfo
- Publication number
- CN112490202A CN112490202A CN201910862988.5A CN201910862988A CN112490202A CN 112490202 A CN112490202 A CN 112490202A CN 201910862988 A CN201910862988 A CN 201910862988A CN 112490202 A CN112490202 A CN 112490202A
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- Prior art keywords
- power device
- insulating substrate
- heat dissipation
- package structure
- device package
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/34—Arrangements for cooling, heating, ventilating or temperature compensation ; Temperature sensing arrangements
- H01L23/36—Selection of materials, or shaping, to facilitate cooling or heating, e.g. heatsinks
- H01L23/367—Cooling facilitated by shape of device
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/12—Mountings, e.g. non-detachable insulating substrates
- H01L23/13—Mountings, e.g. non-detachable insulating substrates characterised by the shape
Abstract
The invention provides a power device packaging structure which comprises a heat dissipation insulating substrate, a plurality of power devices, a heat dissipation back plate and a thermal interface layer. The heat dissipation insulating substrate is provided with a first face and a second face which are opposite, and the power device is coupled to the first face of the heat dissipation insulating substrate. The heat dissipation back plate is arranged on the second surface of the heat dissipation insulating substrate, wherein at least one of the surface of the heat dissipation back plate and the second surface of the heat dissipation insulating substrate is provided with at least one lug, and the lug is at least arranged in the projection area of the plurality of power devices. The thermal interface layer is arranged between the second surface of the heat dissipation insulating substrate and the surface of the heat dissipation back plate.
Description
Technical Field
The present disclosure relates to package structures, and particularly to a package structure of a power device.
Background
The power module is currently applied to various products as a main core device for electric energy conversion, and a power device is packaged in the power module. When a heat dissipation substrate in a power module is connected with a chip circuit board such as a direct copper clad ceramic substrate (DBC), the DBC has a different thermal expansion coefficient from that of the heat dissipation substrate, so that the DBC has a higher thermal stress at the edge due to the difference in thermal deformation amount during heating.
In order to reduce the thermal stress on the DBC, a thicker thermal interface layer is currently used between the heat-dissipating substrate and the DBC to reduce the thermal stress. However, as the thickness of the Thermal interface layer increases, the Thermal resistance of the package structure increases.
Disclosure of Invention
The invention provides a power device packaging structure which can solve the problem of overhigh thermal stress of a traditional power module and can reduce the structural thermal resistance.
The invention also provides a power device packaging structure which can reduce the thermal resistance of the power module under the condition of not increasing the stress of the heat dissipation insulating substrate.
The invention discloses a power device packaging structure, which comprises a heat dissipation insulating substrate, a plurality of power devices, a heat dissipation back plate and a thermal interface layer. The heat dissipation insulating substrate is provided with a first face and a second face which are opposite, and the power device is coupled to the first face of the heat dissipation insulating substrate. The heat dissipation back plate is arranged on the second surface of the heat dissipation insulating substrate, wherein at least one of the surface of the heat dissipation back plate and the second surface is provided with at least one bump, and the bump is at least arranged in the projection areas of the plurality of power devices. The thermal interface layer is arranged between the second surface of the heat dissipation insulating substrate and the surface of the heat dissipation back plate.
In an embodiment of the invention, the ratio of the surface area of the heat-dissipating back plate occupied by the at least one bump is 10% to 35%.
In an embodiment of the invention, at least one of the plurality of power devices is flip-chip bonded to the first surface.
In an embodiment of the invention, the power device package structure may further include a conductive clip disposed on an opposite side of the junction between the power device and the heat dissipation insulating substrate and electrically connecting the power device to the first surface of the heat dissipation insulating substrate.
In an embodiment of the invention, the conductive clip is made of a material such as aluminum, copper or carbon fiber.
In an embodiment of the present invention, the cross-sectional shape of each bump may be trapezoidal, triangular, circular or rectangular.
In an embodiment of the invention, the heat-dissipating insulating substrate includes a direct copper clad ceramic substrate (DBC), an Insulating Metal Substrate (IMS), or a Printed Circuit Board (PCB).
The invention also provides a power device packaging structure, which comprises a heat dissipation insulating substrate, a plurality of power devices, a heat dissipation back plate and a thermal interface layer. The heat dissipation insulating substrate is provided with a first face and a second face which are opposite, and the power device is coupled to the first face of the heat dissipation insulating substrate. The heat dissipation back plate is arranged on the second surface of the heat dissipation insulating substrate. The thermal interface layer is respectively contacted with the second surface of the heat dissipation insulating substrate and the heat dissipation back plate, and the thermal interface layer is positioned between the second surface and the heat dissipation back plate, wherein the minimum thickness of the thermal interface layer in the projection areas of the plurality of power devices is smaller than the thickness outside the projection areas of the power devices.
In another embodiment of the present invention, at least one of the heat dissipation back plate and the heat dissipation insulating substrate has at least one bump on a surface contacting the thermal interface layer, and the at least one bump is at least disposed in a projection area of the plurality of power devices.
In various embodiments of the present invention, an area occupied by the at least one bump is greater than or substantially equal to a projected area of the plurality of power devices.
In various embodiments of the present invention, the at least one bump is integrally formed with the heat-dissipating back plate or the heat-dissipating insulating substrate.
In various embodiments of the present invention, the thermal interface layer comprises a thermal conductive paste, sintered silver, or solder paste.
Based on the above, the power device package structure of the present invention is configured with a plurality of bump structures between the heat dissipation insulating substrate and the heat dissipation substrate, so as to reduce the overall thermal resistance of the power device package structure without increasing the thermal stress of the heat dissipation insulating substrate.
In order to make the aforementioned and other features and advantages of the invention more comprehensible, embodiments accompanied with figures are described in detail below.
Drawings
Fig. 1A is a schematic cross-sectional view of a power device package structure according to a first embodiment of the invention;
fig. 1B is a schematic cross-sectional view of another power device package structure of the first embodiment;
fig. 1C is a schematic cross-sectional view of a further power device package structure of the first embodiment;
fig. 1D is a schematic cross-sectional view of yet another power device package structure of the first embodiment;
fig. 2 is a schematic cross-sectional view of a power device package structure according to a second embodiment of the present invention;
fig. 3A is a schematic perspective view of a heat dissipation back plate of experimental example 1;
fig. 3B is a schematic perspective view of a heat dissipation back plate of a comparative example;
fig. 4A is a schematic view of a thermal distribution of a power device package structure of experimental example 1;
fig. 4B is a schematic diagram of a thermal profile of a power device package structure of a comparative example;
fig. 5 is a graph showing a relationship between a bump area, a chip temperature, and a stress in the power device package structure of experimental example 2.
The reference numbers illustrate:
100. 200: power device packaging structure
102: heat radiation insulation substrate
102 a: first side
102 b: second surface
104: power device
104 a: opposite sides
106: heat radiation backboard
106 a: surface of
108. 202: thermal interface layer
110. 120, 122, 204, 300: bump
112: patterned circuit
114: insulating material plate
116: lower circuit layer
118: solder joint
124: conductive clip
126: solder layer
PA: projected area
t 1: minimum thickness
t 2: thickness of
Detailed Description
The following disclosure provides many different embodiments, or examples, for implementing different features of the invention. These embodiments are merely examples and are not intended to limit the scope and application of the present invention. Moreover, the relative thicknesses and positions of various components, layers or regions may be reduced or exaggerated for clarity. In addition, similar or identical reference numerals are used in the drawings to identify similar or identical elements or features, and the description thereof will be omitted if there is a reference numeral identical to that in the previous drawings.
Fig. 1A is a schematic cross-sectional view of a power device package structure according to a first embodiment of the invention.
Referring to fig. 1A, a power device package structure 100 of the present embodiment includes a heat dissipation insulating substrate 102, a plurality of power devices 104, a heat dissipation back plate 106, and a thermal interface layer 108. A plurality of power devices 104 are coupled to the first face 102a of the heat sink insulating substrate 102. In one embodiment, at least one power device 104 is flip-chip bonded to the first face 102 a. The heat dissipating insulating substrate 102 is, for example, a direct copper clad ceramic substrate (DBC), an Insulating Metal Substrate (IMS), or a Printed Circuit Board (PCB). The heat dissipation back plate 106 is disposed on the second surface 102b of the heat dissipation insulating substrate 102, and the surface 106a of the heat dissipation back plate 106 has a plurality of bumps 110, and the bumps 110 are disposed at least in the projection area PA of the plurality of power devices 104. In the present embodiment, the bumps 110 are integrally formed with the heat dissipation back plate 106, and each of the bumps 110 has a trapezoidal cross-sectional shape. However, the present invention is not limited thereto, and the position, number, distribution range, cross-sectional shape, etc. of the bumps 110 may be changed as required. For example, the position of the bump 110 may also be disposed on the second surface 102 b; the number of bumps 110 may be 1, 2, or more; the area occupied by the bumps 110 may be greater than or substantially equal to the projected area PA; the bumps 110 and the heat-dissipating back plate 106 may be separate; the cross-sectional shape of each bump 110 may be triangular, circular, rectangular, etc. The Thermal interface layer 108 is disposed between the second surface 102b of the heat dissipation insulating substrate 102 and the surface 106a of the heat dissipation back plate 106, wherein the Thermal interface layer 108 is made of Solder, such as Thermal grease (Thermal grease), Sintered silver (Sintered Ag), or Solder paste (Eutectic Solder).
Referring to fig. 1A, the heat sink insulating substrate 102 has a patterned circuit 112, and the patterned circuit 112 is formed on an insulating material plate 114. The second surface 102b of the thermal insulating substrate 102 may have a whole lower circuit layer 116; for example, the connection between the power device 104 and the thermal insulation substrate 102 is achieved by forming a solder joint 118 on a pad (not shown) of each power device 104, and then using a flip-chip technique to make the solder joint 118 directly face the patterned circuit 114 of the thermal insulation substrate 102.
Due to the bumps 110, the path of heat generated by the power device 104 to the heat-dissipating back plate 106 can be shortened, as in a large thermal resistance and in parallel with a small thermal resistance, so that the overall structural thermal resistance can be reduced. As shown by the downward arrows in fig. 1A, most of the heat generated from the power device 104 is transferred from the bump 110 to the heat dissipation back plate 106, so that the structural thermal resistance can be reduced. Furthermore, the thermal interface layer 108 outside the projected area PA of the power device 104 (near the edge of the heat sink insulating substrate 102) is thick enough to reduce the thermal stress of the power device package structure 100 (i.e., the edge of the heat sink insulating substrate 102).
Fig. 1B is a schematic cross-sectional view of another power device package structure according to the first embodiment, wherein the same reference numerals and parts of the contents are used in fig. 1A to indicate the same or similar elements, and the description of the same technical contents is omitted. For the description of the omitted parts, reference may be made to the foregoing description, and the description will not be repeated below.
In fig. 1B, the bump 120 is disposed on the second surface 102B and protrudes toward the heat dissipation back plate 106, so that the minimum thickness of the thermal interface layer 108 between the second surface 102B of the heat dissipation insulating substrate 102 and the surface 106a of the heat dissipation back plate 106 in the projected area PA of the power device 104 is smaller than the thickness of any region except the projected area PA. Moreover, the bump 120 and the lower circuit layer 116 of the thermal insulating substrate 102 are integrally formed, so the bump 120 and the thermal insulating substrate 102 are integrally formed.
Fig. 1C is a schematic cross-sectional view of a further power device package structure according to the first embodiment, wherein the same reference numerals and parts of the contents are used in fig. 1A to indicate the same or similar elements, and the description of the same technical contents is omitted. For the description of the omitted parts, reference may be made to the foregoing description, and the description will not be repeated below.
In fig. 1C, the number of the bumps 122 is 1, the area occupied by the bumps 122 is slightly larger than the projection area PA, and the bumps 122 and the heat dissipation back plate 106 are separated, so the materials of the bumps 122 and the heat dissipation back plate 106 may be different, but the invention is not limited thereto, and the materials of the bumps 122 and the heat dissipation back plate 106 may also be the same.
Fig. 1D is a schematic cross-sectional view of still another power device package structure according to the first embodiment, wherein the same reference numerals and parts of the contents are used in fig. 1A to indicate the same or similar elements, and the description of the same technical contents is omitted. For the description of the omitted parts, reference may be made to the foregoing description, and the description will not be repeated below.
In fig. 1D, an opposite side 104a of the power device 104 bonded to the heat sink insulating substrate 102 is provided with a conductive clip 124. The conductive clip 124 electrically connects the power device 104 to the first surface 102a of the heat sink insulating substrate 102. In one embodiment, the conductive clip 124 is made of a material such as aluminum, copper, or carbon fiber. Furthermore, one conductive clip 124 may electrically connect a plurality of power devices 104 to the heat sink insulating substrate 102. However, the invention is not limited thereto, and one conductive clip 124 may only electrically connect one power device 104 to the thermal insulating substrate 102. In one embodiment, if the power device 104 is a vertical power device, a portion of the conductive clip 124 may be electrically connected to the inactive region of the vertical power device, and another portion of the conductive clip 124 may be electrically connected to the first surface 102 a. In addition, the first surface 102a and the conductive clip 124 can be electrically connected to each other through an additional solder layer 126, and the power device 104 and the conductive clip 124 can also be electrically connected to each other through the solder layer 126, but the invention is not limited thereto. The solder layer 126 is made of solder such as sintered silver or solder paste.
Fig. 2 is a cross-sectional view of a power device package structure according to a second embodiment of the present invention, wherein the reference numerals and parts of the contents of the first embodiment are used, wherein the same reference numerals are used to indicate the same or similar elements, and the description of the same technical contents is omitted. For the description of the omitted parts, reference may be made to the foregoing embodiments, which are not repeated herein.
Referring to fig. 2, the power device package structure 200 of the present embodiment includes a heat dissipation insulating substrate 102, a plurality of power devices 104, a heat dissipation back plate 106, and a thermal interface layer 202. The thermal interface layer 202 is respectively in contact with the second surface 102b of the heat dissipation insulating substrate 102 and the heat dissipation back plate 106, and the minimum thickness t1 of the thermal interface layer 202 within the projected area PA of the power device 104 is smaller than the thickness t2 outside the projected area PA of the power device 104. Therefore, the path (i.e., the minimum thickness t1) for heat generated by the power device 104 to be transferred to the heat-dissipating back plate 106 can be shortened, thereby reducing the structural thermal resistance; the thickness t2 of the thermal interface layer 202 outside the projected area PA is sufficiently thick to reduce the thermal stress of the power device package structure 200 (i.e., the edge of the heat sink insulating substrate 102).
In fig. 2, the surface of the thermal insulating substrate 102 contacting the thermal interface layer 202 further has a bump 204, and the bump 204 is disposed in the projected area PA of all the power devices 104. In the present embodiment, the bump 204 is disposed under the lower circuit layer 116 of the thermal insulating substrate 102, but the invention is not limited thereto. In another embodiment, the bump 204 may be integrally formed with the heat-dissipating back plate 106 or the heat-dissipating insulating substrate 102. In addition, the positions, number, distribution range, cross-sectional shape, etc. of the bumps 204 can be changed as required, and are described in detail in fig. 1A, 1B, 1C, and 1D, which is not repeated herein.
Experiments are listed below to verify the efficacy of the present invention, but the scope of the present invention is not limited to the following experimental contents.
Experimental example 1
A heat-dissipating back plate is fabricated as shown in fig. 3A, wherein the bumps 300 are integrally formed with the heat-dissipating back plate. The heat-dissipating back plate of fig. 3A is then used to assemble a power device package structure as shown in fig. 1A.
The thermal profile of the entire power device package structure was measured with the power device 104 heating, resulting in fig. 4A.
Comparative example
A heat-dissipating back plate as shown in fig. 3B is fabricated, and its surface is a plane. The heat-dissipating back plate of fig. 3B is then used to assemble the power device package structure shown in fig. 1A, but without bumps.
The thermal profile of the entire power device package structure was measured with the power device 104 heating, resulting in fig. 4B.
As can be seen from fig. 4A and 4B, the thermal distribution of the power device package structure with bumps is more uniform than that of the power device package structure without bumps, and there is no temperature region higher than 135 ℃ in the center of fig. 4B. By comparison, the Thermal resistance (Thermal resistance) of the experimental example 1 was 0.137 ℃/W and the Thermal resistance of the comparative example was 0.141 ℃/W. Therefore, the thermal resistance drop was 3%.
Further, the power device package structures of experimental example 1 and comparative example were subjected to a measurement of a grain stress (Dice stress) when the power devices generate heat, and the results of the stress of experimental example 1 being 128.4MPa and the stress of comparative example being 128.6MPa were obtained. It can thus be demonstrated that the provision of the bumps still allows to keep the thermal stress low.
Experimental example 2
The simulation uses several heat-dissipating back plates as shown in fig. 3A, wherein the area ratio of the bumps occupying the heat-dissipating back plates is from 0% to 40%, and the power device package structure as shown in fig. 1A is assembled, wherein the sizes of the components are all set to be the same.
The maximum temperature of the junction of the power device 104 and the die stress were then simulated with the power device 104 heating, and the results are shown in fig. 5.
As can be seen from fig. 5, the larger the bump occupation area, the lower the junction temperature of the power device, and the preferable bump occupation area is about 10% to 35%. Under the specific bump design, the occupied area of the bump is less than 25%, and the effect of reducing the junction temperature of the power device can be achieved under the condition of not increasing the stress of the crystal grains. Therefore, the invention uses the bump to shorten the heat dissipation path and ensure that the edge of the heat dissipation insulating substrate still has a sufficiently thick thermal interface layer, thereby reducing the structural thermal resistance.
In summary, in the power device package structure of the present invention, the bump structure disposed between the heat dissipation insulating substrate and the heat dissipation substrate can achieve the result that the thermal interface layers in different areas have different thicknesses, so as to reduce the thermal stress of the heat dissipation insulating substrate and also reduce the overall thermal resistance of the power device package structure.
Although the present invention has been described with reference to the above embodiments, it should be understood that various changes and modifications can be made therein by those skilled in the art without departing from the spirit and scope of the invention.
Claims (15)
1. A power device package structure, comprising:
the heat dissipation insulating substrate is provided with a first surface and a second surface which are opposite;
a plurality of power devices coupled to the first face of the heat sink insulating substrate;
the heat dissipation back plate is arranged on the second surface of the heat dissipation insulating substrate, at least one of the surface of the heat dissipation back plate and the second surface of the heat dissipation insulating substrate is provided with at least one lug, and the at least one lug is at least arranged in the projection area of the plurality of power devices; and
a thermal interface layer between the second face of the heat sink insulating substrate and the surface of the heat sink backplane.
2. The power device package structure of claim 1, wherein the at least one bump occupies an area greater than or substantially equal to the projected area of the plurality of power devices.
3. The power device package structure of claim 1, wherein the at least one bump occupies a surface area fraction of the heat dissipation backplate of 10% to 35%.
4. The power device package structure of claim 1, wherein the at least one bump is integrally formed with the heat sink back plate or heat sink insulating substrate.
5. The power device package structure of claim 1, wherein a cross-sectional shape of each of the bumps is trapezoidal, triangular, circular, or rectangular.
6. The power device package structure of claim 1, wherein at least one of the plurality of power devices is flip-chip bonded to the first face.
7. The power device package structure of claim 1, further comprising a conductive clip disposed on an opposite side of the plurality of power devices from the heat sink insulating substrate and electrically connecting the plurality of power devices to the first side of the heat sink insulating substrate.
8. The power device package structure of claim 7, wherein the material of the conductive clip comprises aluminum, copper, or carbon fiber.
9. The power device package structure of claim 1, wherein the heat dissipating insulating substrate comprises a direct copper clad ceramic substrate, an insulated metal substrate, or a printed circuit substrate.
10. The power device package structure of claim 1, wherein the thermal interface layer comprises a thermally conductive paste, sintered silver, or solder paste.
11. A power device package structure, comprising:
the heat dissipation insulating substrate is provided with a first surface and a second surface which are opposite;
a plurality of power devices coupled to the first face of the heat sink insulating substrate;
the heat dissipation back plate is arranged on the second surface of the heat dissipation insulating substrate; and
and the thermal interface layer is respectively contacted with the second surface of the heat dissipation insulating substrate and the heat dissipation back plate and is positioned between the second surface and the heat dissipation back plate, wherein the minimum thickness of the thermal interface layer in the projection areas of the plurality of power devices is smaller than the thickness of the thermal interface layer outside the projection areas of the plurality of power devices.
12. The power device package structure of claim 11, wherein a surface of at least one of the heat-dissipating back plate or the heat-dissipating insulating substrate contacting the thermal interface layer has at least one bump, and the at least one bump is at least disposed within a projected area of the plurality of power devices.
13. The power device package structure of claim 12, wherein the at least one bump occupies an area greater than or substantially equal to the projected area of the plurality of power devices.
14. The power device package structure of claim 12, wherein the at least one bump is integrally formed with the heat sink back-plate or heat sink insulating substrate.
15. The power device package structure of claim 11, wherein the thermal interface layer comprises a thermally conductive paste, sintered silver, or solder paste.
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| CN201910862988.5A CN112490202A (en) | 2019-09-12 | 2019-09-12 | Power device packaging structure |
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| CN201910862988.5A CN112490202A (en) | 2019-09-12 | 2019-09-12 | Power device packaging structure |
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