MY121544A - Execution of data processing instructions. - Google Patents

Execution of data processing instructions.

Info

Publication number
MY121544A
MY121544A MYPI94002370A MYPI9402370A MY121544A MY 121544 A MY121544 A MY 121544A MY PI94002370 A MYPI94002370 A MY PI94002370A MY PI9402370 A MYPI9402370 A MY PI9402370A MY 121544 A MY121544 A MY 121544A
Authority
MY
Malaysia
Prior art keywords
memory
instruction
data processing
executed
instructions
Prior art date
Application number
MYPI94002370A
Inventor
David Vivian Jaggar
Original Assignee
Advanced Risc Mach Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Advanced Risc Mach Ltd filed Critical Advanced Risc Mach Ltd
Publication of MY121544A publication Critical patent/MY121544A/en

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
    • G06F9/3861—Recovery, e.g. branch miss-prediction, exception handling
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/30003—Arrangements for executing specific machine instructions
    • G06F9/30072—Arrangements for executing specific machine instructions to perform conditional operations, e.g. using predicates or guards

Landscapes

  • Engineering & Computer Science (AREA)
  • Software Systems (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Advance Control (AREA)
  • Test And Diagnosis Of Digital Computers (AREA)
  • Executing Machine-Instructions (AREA)
  • Techniques For Improving Reliability Of Storages (AREA)
  • Debugging And Monitoring (AREA)

Abstract

DATA PROCESSING APPARATUS (100, 110, 120) IN WHICH SUCCESSIVE DATA PROCESSING INSTRUCTIONS ARE EXECUTED COMPRISES: MEMORY ACCESSING MEANS (110) FOR ACCESSING A DATA MEMORY IN RESPONSE TO ONE OR MORE OF THE INSTRUCTIONS, THE MEMORY ACCESSING MEANS COMPRISING MEANS FOR DETECTING WHETHER EACH MEMORY ACCESS IS INVALID; CONDITION TEST MEANS (200), RESPONSIVE TO A PROCESSING STATE OF THE APPARATUS GENERATED BY PREVIOUSLY EXECUTED INSTRUCTIONS AND OPERABLE DURING EXECUTION OF EACH INSTRUCTION, FOR DETECTING WHETHER THAT INSTRUCTION SHOULD BE EXECUTED; AND CONDITIONAL CONTROL MEANS (230, 240), RESPONSIVE TO THE MEMORY ACCESSING MEANS (110) AND TO THE CONDITION TEST MEANS (200), FOR PREVENTING COMPLETE EXECUTION OF A CURRENT INSTRUCTION IF EITHER THE MEMORY ACCESSING MEANS (110) DETECTS THAT A MEMORY ACCESS INITIATED BY THE PRECEDING INSTRUCTION IS INVALID OR THE CONDITION TEST MEANS (200) DETECTS THAT THE CURRENT INSTRUCTION SHOULD NOT BE EXECUTED.
MYPI94002370A 1993-09-23 1994-09-09 Execution of data processing instructions. MY121544A (en)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
GB9319662A GB2282245B (en) 1993-09-23 1993-09-23 Execution of data processing instructions

Publications (1)

Publication Number Publication Date
MY121544A true MY121544A (en) 2006-02-28

Family

ID=10742425

Family Applications (1)

Application Number Title Priority Date Filing Date
MYPI94002370A MY121544A (en) 1993-09-23 1994-09-09 Execution of data processing instructions.

Country Status (13)

Country Link
US (1) US5961633A (en)
EP (1) EP0721619B1 (en)
JP (1) JP3553946B2 (en)
KR (1) KR100335785B1 (en)
CN (1) CN1099633C (en)
DE (1) DE69414592T2 (en)
GB (1) GB2282245B (en)
IL (1) IL110799A (en)
IN (1) IN189692B (en)
MY (1) MY121544A (en)
RU (1) RU2137182C1 (en)
TW (1) TW332266B (en)
WO (1) WO1995008801A1 (en)

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JPH1049368A (en) * 1996-07-30 1998-02-20 Mitsubishi Electric Corp Microporcessor having condition execution instruction
WO2004053685A1 (en) * 2002-12-12 2004-06-24 Arm Limited Instruction timing control within a data processing system
US20040230781A1 (en) * 2003-05-16 2004-11-18 Via-Cyrix, Inc. Method and system for predicting the execution of conditional instructions in a processor
US8056072B2 (en) 2005-10-31 2011-11-08 Microsoft Corporation Rebootless display driver upgrades
US9378019B2 (en) 2011-04-07 2016-06-28 Via Technologies, Inc. Conditional load instructions in an out-of-order execution microprocessor
US9292470B2 (en) 2011-04-07 2016-03-22 Via Technologies, Inc. Microprocessor that enables ARM ISA program to access 64-bit general purpose registers written by x86 ISA program
EP2695055B1 (en) 2011-04-07 2018-06-06 VIA Technologies, Inc. Conditional load instructions in an out-of-order execution microprocessor
US9244686B2 (en) 2011-04-07 2016-01-26 Via Technologies, Inc. Microprocessor that translates conditional load/store instructions into variable number of microinstructions
US8880851B2 (en) 2011-04-07 2014-11-04 Via Technologies, Inc. Microprocessor that performs X86 ISA and arm ISA machine language program instructions by hardware translation into microinstructions executed by common execution pipeline
US8880857B2 (en) 2011-04-07 2014-11-04 Via Technologies, Inc. Conditional ALU instruction pre-shift-generated carry flag propagation between microinstructions in read-port limited register file microprocessor
US9032189B2 (en) 2011-04-07 2015-05-12 Via Technologies, Inc. Efficient conditional ALU instruction in read-port limited register file microprocessor
US9176733B2 (en) 2011-04-07 2015-11-03 Via Technologies, Inc. Load multiple and store multiple instructions in a microprocessor that emulates banked registers
US9898291B2 (en) 2011-04-07 2018-02-20 Via Technologies, Inc. Microprocessor with arm and X86 instruction length decoders
US9043580B2 (en) 2011-04-07 2015-05-26 Via Technologies, Inc. Accessing model specific registers (MSR) with different sets of distinct microinstructions for instructions of different instruction set architecture (ISA)
US9141389B2 (en) 2011-04-07 2015-09-22 Via Technologies, Inc. Heterogeneous ISA microprocessor with shared hardware ISA registers
US9645822B2 (en) 2011-04-07 2017-05-09 Via Technologies, Inc Conditional store instructions in an out-of-order execution microprocessor
US8924695B2 (en) 2011-04-07 2014-12-30 Via Technologies, Inc. Conditional ALU instruction condition satisfaction propagation between microinstructions in read-port limited register file microprocessor
US9274795B2 (en) 2011-04-07 2016-03-01 Via Technologies, Inc. Conditional non-branch instruction prediction
US9128701B2 (en) 2011-04-07 2015-09-08 Via Technologies, Inc. Generating constant for microinstructions from modified immediate field during instruction translation
US9317288B2 (en) 2011-04-07 2016-04-19 Via Technologies, Inc. Multi-core microprocessor that performs x86 ISA and ARM ISA machine language program instructions by hardware translation into microinstructions executed by common execution pipeline
US9336180B2 (en) 2011-04-07 2016-05-10 Via Technologies, Inc. Microprocessor that makes 64-bit general purpose registers available in MSR address space while operating in non-64-bit mode
US9146742B2 (en) 2011-04-07 2015-09-29 Via Technologies, Inc. Heterogeneous ISA microprocessor that preserves non-ISA-specific configuration state when reset to different ISA

Family Cites Families (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
BE789583A (en) * 1971-10-01 1973-02-01 Sanders Associates Inc PROGRAM CONTROL APPARATUS FOR DATA PROCESSING MACHINE
GB1480209A (en) * 1974-07-03 1977-07-20 Data Loop Ltd Digital computers
JPS54107645A (en) * 1978-02-13 1979-08-23 Hitachi Ltd Information processor
JPS6247746A (en) * 1985-08-27 1987-03-02 Fujitsu Ltd Interruption control system
JPH01229326A (en) * 1988-03-09 1989-09-13 Toshiba Corp Information processor
JPH01310443A (en) * 1988-06-09 1989-12-14 Nec Corp Information processor
US5202967A (en) * 1988-08-09 1993-04-13 Matsushita Electric Industrial Co., Ltd. Data processing apparatus for performing parallel decoding and parallel execution of a variable word length instruction
JPH0335323A (en) * 1989-06-30 1991-02-15 Toshiba Corp Control system for execution of instruction

Also Published As

Publication number Publication date
CN1134193A (en) 1996-10-23
IL110799A (en) 1997-09-30
GB2282245A (en) 1995-03-29
IN189692B (en) 2003-04-12
TW332266B (en) 1998-05-21
DE69414592T2 (en) 1999-05-06
US5961633A (en) 1999-10-05
EP0721619B1 (en) 1998-11-11
EP0721619A1 (en) 1996-07-17
GB9319662D0 (en) 1993-11-10
KR100335785B1 (en) 2002-11-30
CN1099633C (en) 2003-01-22
JPH09503876A (en) 1997-04-15
JP3553946B2 (en) 2004-08-11
DE69414592D1 (en) 1998-12-17
IL110799A0 (en) 1994-11-11
GB2282245B (en) 1998-04-15
WO1995008801A1 (en) 1995-03-30
KR960705271A (en) 1996-10-09
RU2137182C1 (en) 1999-09-10

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