JPH01310443A - Information processor - Google Patents

Abstract

PURPOSE:To shorten a loss time accompanying a memory access action by synthesizing a processing result accompanying an instruction execution and a next instruction held at the instruction register and outputting them to the instruction register when the next instruction on a memory held already to the instruction register adds the change. CONSTITUTION:When a comparator 202 of an instruction analyzing part 20 detects the overlapping of an address, a selecting synchronizing device 206 synthesizes the writing data inputted through a data line 52 and the contents of the instruction register inputted through a data line 208 held already and inputs them to an instruction register 200. The case when only a part of an instruction 102 on a memory 10 is rewritten is present. For this reason, the selecting synthesizing device 206 executes the rewriting of a part. By using two of instruction 102 before the change held at an instruction register 200 and data to need the change, the part to be changed is rewritten to the data inputted through a data line 52 and the part not to be changed is re-inputted through the data line 208 to the instruction register 200.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a pipe processing type information processing device, and particularly to reducing loss time when pipe processing is interrupted.

[Conventional technology]

Conventionally, in information processing devices that perform so-called pipe processing, in which one instruction is executed and the next instruction is simultaneously analyzed and the next instruction is prepared for execution in the next step, the content of one instruction changes the next instruction. In other words, when one instruction is a write instruction to memory and rewrites the next instruction stored in memory, the instruction analysis section executes the instruction at the same time as the execution of the instruction executed by the instruction execution section. The analysis of the next instruction that has changed is invalid, and the newly changed next instruction is reread from memory and the instruction is reanalyzed.

The configuration of a conventional information processing apparatus of this type will be specifically explained with reference to FIG. In the figure, the information processing device includes a memory 10 in which a group of instructions is stored, an instruction execution unit 30 that executes an instruction called from the memory 10, and a memo+J I
The instruction analyzer 20 includes an instruction register 200 that captures and holds the next instruction to be executed following the one instruction from O, and an instruction analyzer 20 that analyzes the contents of the next instruction.

It is assumed that the instruction execution unit 30 is currently executing the instruction 100, and at the same time, the instruction analysis unit 20 is loading the instruction 102 into the instruction register 200 and analyzing it.

When the instruction execution unit 30 writes data as a processing result to the memory 10 via the data line 51 by executing the instruction 100, the write address 300 of the data to be written and the memory of the instruction 102 being analyzed by the instruction analysis unit 20 Comparator 202 compares the two addresses of instruction address 204 on
As a result, if an overlap in addresses is found, execution of instruction 100 updates instruction 10 in memory.
2 will undergo changes.

The instruction analysis unit 20 has already read the data line 50 from the memory 10.
Although the instruction 102 before the change is fetched and analyzed through the , since the instruction 102 in the memory has been changed, the instruction 102 before the change that is being analyzed becomes invalid.

What must be analyzed at this point is the instruction 102 on the memory that has been changed, and the instruction analysis unit 20
The changed instruction 102 is re-introduced into the instruction register 200 and the instruction is re-analyzed.

[Problem to be solved by the invention]

As mentioned above, in conventional pipe processing type information processing devices, when an instruction that is being read into the instruction register and being analyzed is affected by the next instruction, a new instruction that has been changed is read in from memory. As a result, the calculation speed of the processing section is influenced by the memory having a relatively slow response speed, resulting in an increase in loss time for the information processing apparatus as a whole.

The present invention was made in view of these circumstances, and
It is an object of the present invention to provide an information processing device that reduces loss time associated with memory access operations.

[Means to solve the problem]

In order to achieve the above object, the present invention includes a storage means in which a group of instructions is stored, an instruction execution means for executing one instruction read from the storage means, and a next instruction executed from the storage means following one instruction. Pipe processing type information processing that includes an instruction register that captures and holds an instruction, and an instruction analysis means that analyzes the contents of the next instruction, and executes one instruction and analyzes the contents of the next instruction at the same time. In the apparatus, a data line that directly connects the instruction execution means and the storage means for writing the processing result accompanying the execution of the instruction by the instruction execution means into the storage means is branched and connected so that it can be input to the instruction register, and The instruction to be read, the processing result associated with the execution of the instruction, and the contents held in the instruction register are inputted, and the selection synthesis means has data selection and synthesis means that selectively outputs the instruction read from the storage means. When the next instruction in the memory that is already held in the instruction register is changed due to the execution of one instruction by the execution means, the processing result associated with the instruction execution and the next instruction held in the instruction register are synthesized. This is characterized by outputting the command to the instruction register.

In the information processing device according to the present invention, when the next instruction on the memory already held in the instruction register of the instruction analysis means is changed due to the instruction execution by the instruction execution means, the processing result accompanying the instruction execution and the Since the next instruction held in the instruction register is combined with the next instruction and output to the instruction register, there is no need to reread the changed instruction from the storage means to change the contents of the instruction register, and the response is relatively fast. Loss time associated with slow memory access operations can be reduced.

〔Example〕

Embodiments of the present invention will be described below with reference to the drawings.

FIG. 1 shows the configuration of an embodiment of an information processing apparatus according to the present invention. Note that the explanation of the parts that overlap between the configurations of the information processing apparatus shown in FIG. 1 and the information processing apparatus shown in FIG. 2 will be omitted. That is, after the instruction 100 read out from the memory 10 is executed by the instruction execution section 30, until an address overlap is detected by the comparator 202 in the instruction analysis section 20, the conventional method shown in FIG. Exactly the same as the example. Also, the same reference numerals are used for the same components. In this embodiment, the instruction 102 on the memory 10 that has been changed is transferred to the new memory 10.
It does not read from.

That is, the data line 51 is branched and the instruction analysis section 20
A data line 52 is provided for input to the selector synthesizer 206 .

The selection synthesizer 206 selects the instruction address 204 from the comparator 202.
Unless an overlap between the address and the write address 300 is detected, read data (instruction) from the memory 10 is selectively outputted so as to be input to the instruction register 200. In this state, the memory 10 in the conventional information processing apparatus shown in FIG.
This is equivalent to inputting read data (commands) directly to the instruction register 200.

Now, when the comparator 202 of the instruction analysis section 20 detects an address overlap, the selection synthesizer 206
The write data inputted through the input line 200 and the contents of the instruction register inputted through the data line 208 that have already been held are combined and input into the instruction register 200. The write data output via the data 51152 as a processing result after the instruction execution unit 30 executes the instruction does not necessarily rewrite all of the instructions 102 on the memory 10; In some cases, only a portion of the information may be rewritten. Therefore, in order to make the partial rewrite compatible, the selection synthesizer 206 uses two items: the instruction 102 before the change held in the instruction register 200 and the partial data input via the data line 52 that requires the change.
The parts to be changed are replaced with data input via the data line 52, while the parts not to be changed are selectively synthesized using data input from the instruction register 200 via the data line 208 and input to the instruction register 200. do. The instruction analyzer 20 sets the changed instruction in the instruction register 200 and reanalyzes the instruction.

〔Effect of the invention〕

As explained above, in the present invention, when the next instruction in the memory already held in the instruction register of the instruction analysis means is changed by the instruction execution by the instruction execution means, the processing result accompanying the instruction execution is changed. and the next instruction held in the instruction register are combined and output to the instruction register. According to the present invention, in order to change the contents of the instruction register, the instruction after the change is reread from the storage means. There is no need to perform this process, and loss time associated with memory access operations with relatively slow response speeds can be reduced.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing the configuration of an embodiment of an information processing apparatus according to the present invention, and FIG. 2 is a block diagram showing the configuration of a conventional information processing apparatus. 10...Memory, 20...Instruction analysis unit, 30...Instruction execution unit, 200...Instruction register, 202...Comparator , 206... Selection synthesizer. Applicant: NEC Co., Ltd. Representative: Patent attorney: Umeo Yamauchi Figures 1 and 2

Claims (1)

[Scope of Claims] A storage means for storing a group of instructions, an instruction execution means for executing one instruction read from the storage means, and a next instruction to be executed subsequent to the one instruction taken from the storage means. In a pipe processing type information processing device, which includes an instruction register for holding, and an instruction analysis means for analyzing the contents of the next instruction, and simultaneously executes one instruction and analyzes the contents of the next instruction in parallel, A data line that directly connects the instruction execution means and the storage means for writing the processing result accompanying the execution of the instruction by the instruction execution means into the storage means is branched and connected so as to be input to the instruction register, and a data line from the storage means A data selection and synthesis means receives an instruction to be read, a processing result accompanying execution of the instruction, and contents held in the instruction register, and normally outputs an instruction read from the storage means selectively, and the selection and synthesis means includes: If the next instruction on the memory already held in the instruction register is changed due to the execution of one instruction by the instruction execution means, the processing result associated with the execution of the instruction and the next instruction held in the instruction register are changed. What is claimed is: 1. An information processing device characterized in that: