MY105090A - Serial date interface. - Google Patents

Serial date interface.

Info

Publication number
MY105090A
MY105090A MYPI89001114A MYPI19891114A MY105090A MY 105090 A MY105090 A MY 105090A MY PI89001114 A MYPI89001114 A MY PI89001114A MY PI19891114 A MYPI19891114 A MY PI19891114A MY 105090 A MY105090 A MY 105090A
Authority
MY
Malaysia
Prior art keywords
data
circuit
data bus
clock pulse
resetting
Prior art date
Application number
MYPI89001114A
Inventor
Ing George Boker Dipl
Gunter Gleim Dipl-Ing
Barry Critchley Dipl-Ing
Original Assignee
Thomson Brandt Gmbh
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Thomson Brandt Gmbh filed Critical Thomson Brandt Gmbh
Publication of MY105090A publication Critical patent/MY105090A/en

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/38—Information transfer, e.g. on bus
    • G06F13/42—Bus transfer protocol, e.g. handshake; Synchronisation
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/38—Information transfer, e.g. on bus
    • G06F13/42—Bus transfer protocol, e.g. handshake; Synchronisation
    • G06F13/4204—Bus transfer protocol, e.g. handshake; Synchronisation on a parallel bus
    • G06F13/4208—Bus transfer protocol, e.g. handshake; Synchronisation on a parallel bus being a system bus, e.g. VME bus, Futurebus, Multibus
    • G06F13/4217—Bus transfer protocol, e.g. handshake; Synchronisation on a parallel bus being a system bus, e.g. VME bus, Futurebus, Multibus with synchronous protocol

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Information Transfer Systems (AREA)
  • Communication Control (AREA)
  • Selective Calling Equipment (AREA)
  • Radar Systems Or Details Thereof (AREA)
  • Bus Control (AREA)
  • Data Exchanges In Wide-Area Networks (AREA)
  • Arrangements For Transmission Of Measured Signals (AREA)
  • Ultra Sonic Daignosis Equipment (AREA)
  • Circuits Of Receivers In General (AREA)
  • Vehicle Body Suspensions (AREA)
  • Dram (AREA)

Abstract

A SERIAL DATA INTERFACE IS USED TO CONNECT PERIPHERAL CIRCUITS, WHICH RECEIVE OR TRANSMIT DATA VIA A DATA BUS, TO SAID DATA BUS. IT MUST EVALUATE THE DATA FLOW RUNNING THROUGH THE DATA BUS USING CRITERIA WHICH ALLOW THE ALLOCATION TO THE CONNECTED PERIPHERAL CIRCUIT. UNDER THE INVENTION A DATA MEMORY (4), A COMPARATOR CIRCUIT (5), A CONTROL CIRCUIT (6), AN INTERNAL SETTING/RESETTING CIRCUIT (7) AND AN INTERNAL CLOCK PULSE GENERATOR (8) ARE PRESENT. HEREBY, THE INPUT OF THE DATA MEMORY (4) CAN BE CONNECTED TO THE DATA LINE (9) OF THE DATA BUS (3) AND THE COMPARATOR CIRCUIT (5) IS LOCATED AT THE OUTPUT OF THE DATA MEMORY (4), THE COMPARATOR CIRCUIT (5) BEING FOLLOWED BY THE CONTROL CIRCUIT (6). THE INPUT OF THE INTERNAL SETTING/RESETTING CIRCUIT (7) CAN BE CONNECTED TO THE RELEASE LINE (10) AND THE CLOCK PULSE LINE (11) OF THE DATA BUS (3) AND OUTPUTS OF THE INTERNAL SETTING/RESETTING CIRCUIT (7) ARE CONNECTED TO SETTING/RESETTING INPUTS OF THE DATA MEMORY (4), THE COMPARATOR CIRCUIT (5) AND THE CONTROL CIRCUIT (6). FURTHERMORE, THE INPUT OF THE INTERNAL CLOCK PULSE GENERATOR (8) CAN BE CONNECTED TO THE RELEASE (10) AND THE DATA LINE (11) OF THE DATA BUS (3) AND THE OUTPUT OF THE INTERNAL CLOCK PULSE GENERATOR (8) IS CONNECTED TO CLOCK PULSE INPUTS OF THE DATA MEMORY (4), THE COMPARATOR CIRCUIT (5) AND THE CONTROL CIRCUIT (6). THE SERIAL DATA INTERFACE ACCORDING TO THE INVENTION IS PARTICULARLY SUITABLE FOR CONNECTING A PERIPHERAL CIRCUIT BY MEANS OF A DATA BUS WHICH MEETS THE THOMSON SPECIFICATIONS. (FIG. 1)
MYPI89001114A 1988-08-31 1989-08-15 Serial date interface. MY105090A (en)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
DE3829454A DE3829454A1 (en) 1988-08-31 1988-08-31 SERIAL DATA INTERFACE

Publications (1)

Publication Number Publication Date
MY105090A true MY105090A (en) 1994-08-30

Family

ID=6361925

Family Applications (1)

Application Number Title Priority Date Filing Date
MYPI89001114A MY105090A (en) 1988-08-31 1989-08-15 Serial date interface.

Country Status (12)

Country Link
EP (2) EP0356873B1 (en)
JP (1) JPH03501072A (en)
KR (1) KR900702459A (en)
AT (1) ATE96557T1 (en)
CA (1) CA1328929C (en)
DE (2) DE3829454A1 (en)
ES (1) ES2047072T3 (en)
FI (1) FI902153A0 (en)
HK (1) HK9596A (en)
MY (1) MY105090A (en)
TR (1) TR24012A (en)
WO (1) WO1990002377A1 (en)

Families Citing this family (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5278243A (en) * 1992-01-14 1994-01-11 Soane Technologies, Inc. High impact resistant macromolecular networks
DE4107052B4 (en) * 1991-03-06 2005-09-29 Robert Bosch Gmbh Device for the application of control devices, in particular ignition and / or injection control devices for motor vehicles

Family Cites Families (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE3139421A1 (en) * 1981-10-03 1983-04-21 Nsm-Apparatebau Gmbh & Co Kg, 6530 Bingen Serial output circuit
DE3404721C2 (en) * 1984-02-10 1991-07-25 Deutsche Thomson-Brandt Gmbh, 7730 Villingen-Schwenningen Circuit arrangement for the transmission of data
DE3534216A1 (en) * 1985-09-25 1987-04-02 Bayerische Motoren Werke Ag DATA BUS SYSTEM FOR VEHICLES
FR2591772B1 (en) * 1985-12-18 1989-09-29 Cugnez Jean Louis SYSTEM FOR CONNECTING A PERIPHERAL TO MULTIPLE COMPUTERS
DE3603751A1 (en) * 1986-02-06 1987-08-13 Siemens Ag INFORMATION TRANSFER SYSTEM FOR THE TRANSFER OF BINARY INFORMATION

Also Published As

Publication number Publication date
WO1990002377A1 (en) 1990-03-08
ES2047072T3 (en) 1994-02-16
HK9596A (en) 1996-01-26
TR24012A (en) 1991-01-28
FI902153A0 (en) 1990-04-27
JPH03501072A (en) 1991-03-07
EP0356873A1 (en) 1990-03-07
KR900702459A (en) 1990-12-07
CA1328929C (en) 1994-04-26
DE58906010D1 (en) 1993-12-02
ATE96557T1 (en) 1993-11-15
EP0404870A1 (en) 1991-01-02
EP0356873B1 (en) 1993-10-27
DE3829454A1 (en) 1990-03-01

Similar Documents

Publication Publication Date Title
MY100689A (en) Interrupt level sharing
GB2349490A (en) Memory module controller
GB2019622A (en) Digital computing apparatus
ES464099A1 (en) Input/output interface connector circuit for repowering and isolation
KR860008498A (en) In-device bus service system (機器 內 bus 利 用 system)
MY105090A (en) Serial date interface.
EP0184639B1 (en) Test system for keyboard interface circuit
EP0915566A3 (en) Reset circuit for flipflop
DE3465231D1 (en) Single clocked latch circuit
JPS5757330A (en) Data transfer system by connection of bus
JPS57199040A (en) Synchronizing device for data transfer
JPS55944A (en) Clock switching system
TH7911EX (en) Serial data link
JPS57154959A (en) Microprocessor device
JPS6478320A (en) Data processing system
EP0351959A3 (en) Multi-channel controller
JPS57139851A (en) Serial-parallel converter
KR900005661B1 (en) Data transmitting circuit and mehtod between controller and laser printer
JPS5799844A (en) Serial multiplex data transfer system
JPS5643850A (en) Intermultiplexer communication control system
JPS54127244A (en) Interruption control system
JPS5964926A (en) Malfunction preventing device
JPS6266175A (en) Circuit for testing integrated circuit as simple substance
JPS5466050A (en) Integrated circuit device
JPS57147731A (en) Common use device for interface