MXPA03006810A - Circuito de multi-etapas hibrido. - Google Patents

Circuito de multi-etapas hibrido.

Info

Publication number
MXPA03006810A
MXPA03006810A MXPA03006810A MXPA03006810A MXPA03006810A MX PA03006810 A MXPA03006810 A MX PA03006810A MX PA03006810 A MXPA03006810 A MX PA03006810A MX PA03006810 A MXPA03006810 A MX PA03006810A MX PA03006810 A MXPA03006810 A MX PA03006810A
Authority
MX
Mexico
Prior art keywords
stage
circuit
sampling
type
tape
Prior art date
Application number
MXPA03006810A
Other languages
English (en)
Inventor
Bazarjani Seyfollah
Original Assignee
Qualcomm Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Qualcomm Inc filed Critical Qualcomm Inc
Publication of MXPA03006810A publication Critical patent/MXPA03006810A/es

Links

Classifications

    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M3/00—Conversion of analogue values to or from differential modulation
    • H03M3/02—Delta modulation, i.e. one-bit differential modulation
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M3/00—Conversion of analogue values to or from differential modulation
    • H03M3/30—Delta-sigma modulation
    • H03M3/458—Analogue/digital converters using delta-sigma modulation as an intermediate step
    • H03M3/494—Sampling or signal conditioning arrangements specially adapted for delta-sigma type analogue/digital conversion systems
    • H03M3/496—Details of sampling arrangements or methods
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M3/00—Conversion of analogue values to or from differential modulation
    • H03M3/30—Delta-sigma modulation
    • H03M3/322—Continuously compensating for, or preventing, undesired influence of physical parameters
    • H03M3/324—Continuously compensating for, or preventing, undesired influence of physical parameters characterised by means or methods for compensating or preventing more than one type of error at a time, e.g. by synchronisation or using a ratiometric arrangement
    • H03M3/326—Continuously compensating for, or preventing, undesired influence of physical parameters characterised by means or methods for compensating or preventing more than one type of error at a time, e.g. by synchronisation or using a ratiometric arrangement by averaging out the errors
    • H03M3/338—Continuously compensating for, or preventing, undesired influence of physical parameters characterised by means or methods for compensating or preventing more than one type of error at a time, e.g. by synchronisation or using a ratiometric arrangement by averaging out the errors by permutation in the time domain, e.g. dynamic element matching
    • H03M3/34—Continuously compensating for, or preventing, undesired influence of physical parameters characterised by means or methods for compensating or preventing more than one type of error at a time, e.g. by synchronisation or using a ratiometric arrangement by averaging out the errors by permutation in the time domain, e.g. dynamic element matching by chopping
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M3/00—Conversion of analogue values to or from differential modulation
    • H03M3/30—Delta-sigma modulation
    • H03M3/322—Continuously compensating for, or preventing, undesired influence of physical parameters
    • H03M3/324—Continuously compensating for, or preventing, undesired influence of physical parameters characterised by means or methods for compensating or preventing more than one type of error at a time, e.g. by synchronisation or using a ratiometric arrangement
    • H03M3/326—Continuously compensating for, or preventing, undesired influence of physical parameters characterised by means or methods for compensating or preventing more than one type of error at a time, e.g. by synchronisation or using a ratiometric arrangement by averaging out the errors
    • H03M3/338—Continuously compensating for, or preventing, undesired influence of physical parameters characterised by means or methods for compensating or preventing more than one type of error at a time, e.g. by synchronisation or using a ratiometric arrangement by averaging out the errors by permutation in the time domain, e.g. dynamic element matching
    • H03M3/342—Continuously compensating for, or preventing, undesired influence of physical parameters characterised by means or methods for compensating or preventing more than one type of error at a time, e.g. by synchronisation or using a ratiometric arrangement by averaging out the errors by permutation in the time domain, e.g. dynamic element matching by double sampling, e.g. correlated double sampling
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M3/00—Conversion of analogue values to or from differential modulation
    • H03M3/30—Delta-sigma modulation
    • H03M3/38—Calibration
    • H03M3/382—Calibration at one point of the transfer characteristic, i.e. by adjusting a single reference value, e.g. bias or gain error
    • H03M3/384—Offset correction

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Compression, Expansion, Code Conversion, And Decoders (AREA)
  • Analogue/Digital Conversion (AREA)
  • Amplifiers (AREA)
  • Time-Division Multiplex Systems (AREA)
  • Filters That Use Time-Delay Elements (AREA)
  • Diaphragms For Electromechanical Transducers (AREA)
  • Executing Machine-Instructions (AREA)
  • Handling Of Sheets (AREA)

Abstract

Un circuito de multi-etapas que incluye un numero de etapas, con por lo menos una etapa siendo de un primer tipo y por lo menos una etapa siendo de un segundo tipo. Cada etapa recibe ya sea una senal de entrada de circuito o una senal de salida de una etapa precedente, procesa, (por ejemplo, filtra) la senal recibida, y proporciona una senal de salida respectiva. Cada primer tipo (o segundo tipo de etapa opera basandose en una o mas senales de reloj que tienen una frecuencia de f, (o fS/N) donde fS es la frecuencia de muestreo y N es un numero entero mayor que uno. Cada etapa de primer tipo puede implementarse con un circuito de doble muestreo correlacionado, un circuito de auto-anulacion, o un circuito pulsador de estabilizacion. Cada etapa de segundo tipo puede implementarse con un circuito de multi-muestreo (es decir, doble muestreo, o muestreo de orden mas alto). El circuito de multi-etapas puede disenarse para implementar un filtro de paso bajo, un ?S ADC o algun otro circuito.
MXPA03006810A 2001-01-31 2002-01-30 Circuito de multi-etapas hibrido. MXPA03006810A (es)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US09/773,403 US6608575B2 (en) 2001-01-31 2001-01-31 Hybrid multi-stage circuit
PCT/US2002/003011 WO2002065644A2 (en) 2001-01-31 2002-01-30 Hybrid multi-stage circuit utilizing different types of sampling circuit

Publications (1)

Publication Number Publication Date
MXPA03006810A true MXPA03006810A (es) 2004-05-05

Family

ID=25098160

Family Applications (1)

Application Number Title Priority Date Filing Date
MXPA03006810A MXPA03006810A (es) 2001-01-31 2002-01-30 Circuito de multi-etapas hibrido.

Country Status (9)

Country Link
US (1) US6608575B2 (es)
EP (1) EP1380114B1 (es)
KR (1) KR100914503B1 (es)
AT (1) ATE466410T1 (es)
AU (1) AU2002235510A1 (es)
DE (1) DE60236147D1 (es)
HK (1) HK1062088A1 (es)
MX (1) MXPA03006810A (es)
WO (1) WO2002065644A2 (es)

Families Citing this family (26)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7177301B2 (en) * 2001-12-27 2007-02-13 Intel Corporation Signal permuting
US7116721B1 (en) * 2002-05-20 2006-10-03 Cirrus Logic, Inc. Delta-sigma modulators with integral digital low-pass filtering
CN100512016C (zh) * 2004-02-10 2009-07-08 三洋电机株式会社 模数转换器
US7015842B1 (en) * 2005-01-12 2006-03-21 Teranetics, Inc. High-speed sampling architectures
US7822160B1 (en) * 2006-02-03 2010-10-26 Marvell International Ltd. Digitally-assisted power reduction technique for IQ pipeline ADCs used in wireless receivers
US7397412B1 (en) 2006-02-03 2008-07-08 Marvell International Ltd. Low power analog to digital converter
KR100794310B1 (ko) * 2006-11-21 2008-01-11 삼성전자주식회사 스위치드 커패시터 회로 및 그것의 증폭 방법
WO2008151265A1 (en) * 2007-06-05 2008-12-11 Analog Devices, Inc. Cross-coupled switched capacitor circuit with a plurality of branches
US7786911B2 (en) * 2007-11-19 2010-08-31 Teledyne Licensing, Llc Resettable high order delta-sigma analog to digital converter
US7679540B2 (en) * 2007-11-30 2010-03-16 Infineon Technologies Ag Double sampling DAC and integrator
US7782237B2 (en) * 2008-06-13 2010-08-24 The Board Of Trustees Of The Leland Stanford Junior University Semiconductor sensor circuit arrangement
KR20110021426A (ko) * 2009-08-26 2011-03-04 삼성전자주식회사 아날로그-디지털 컨버터, 및 이를 포함하는 이미지 처리 장치
CN102025378B (zh) * 2009-09-14 2014-06-18 晨星软件研发(深圳)有限公司 共用运算放大器的多通道∑-△转换电路及其辅助方法
US8611483B2 (en) 2011-06-03 2013-12-17 Maxlinear, Inc. Multi-layer time-interleaved analog-to-digital convertor (ADC)
US8384579B2 (en) * 2011-07-19 2013-02-26 Freescale Semiconductor, Inc. Systems and methods for data conversion
US8531324B2 (en) 2011-07-19 2013-09-10 Freescale Semiconductor, Inc. Systems and methods for data conversion
KR102092904B1 (ko) 2013-11-06 2020-03-24 삼성전자주식회사 스위치드-커패시터 적분기, 이의 동작 방법, 및 이를 포함하는 장치들
WO2016078713A1 (en) * 2014-11-20 2016-05-26 Teledyne Dalsa B.V. A circuit controller for controlling a pixel circuit and a method of controlling a pixel circuit
US9985594B2 (en) * 2015-04-02 2018-05-29 The United States Of America As Represented By The Administrator Of The National Aeronautics And Space Administration Gated CDS integrator
US9641192B1 (en) 2016-06-14 2017-05-02 Semiconductor Components Industries, Llc Methods and apparatus for a delta sigma ADC with parallel-connected integrators
US9774345B1 (en) * 2016-09-20 2017-09-26 Kabushiki Kaisha Toshiba Successive approximation register analog-to-digital converter
JP6855802B2 (ja) * 2017-01-16 2021-04-07 カシオ計算機株式会社 情報処理装置、方法、及びプログラム、ｄ／ａ変換装置、電子楽器
WO2020048893A1 (en) * 2018-09-04 2020-03-12 Signify Holding B.V. Arrangement for amplifying an input signal
KR102082006B1 (ko) 2019-05-24 2020-02-26 문성현 체포기
US10615818B1 (en) 2019-06-02 2020-04-07 Nxp Usa, Inc. Mixed chopping and correlated double sampling two-step analog-to-digital converter
US10868554B1 (en) * 2019-12-06 2020-12-15 Analog Devices International Unlimited Company Time-efficient offset cancellation for multi-stage converters

Family Cites Families (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4633223A (en) * 1981-10-13 1986-12-30 Intel Corporation DC offset correction circuit utilizing switched capacitor differential integrator
US5648779A (en) * 1994-12-09 1997-07-15 Advanced Micro Devices, Inc. Sigma-delta modulator having reduced delay from input to output
US5682161A (en) * 1996-05-20 1997-10-28 General Electric Company High-order delta sigma modulator
US5768315A (en) * 1996-07-22 1998-06-16 Motorola, Inc. Band-pass sigma-delta converter and commutating filter therefor
US5982315A (en) * 1997-09-12 1999-11-09 Qualcomm Incorporated Multi-loop Σ Δ analog to digital converter
US6140950A (en) * 1998-08-17 2000-10-31 Linear Technology Corporation Delta-sigma modulator with improved full-scale accuracy
US6255974B1 (en) * 1999-01-08 2001-07-03 Mitsubishi Electric And Electronics Usa, Inc Programmable dynamic range sigma delta A/D converter

Also Published As

Publication number Publication date
WO2002065644A3 (en) 2003-11-06
US20020140589A1 (en) 2002-10-03
US6608575B2 (en) 2003-08-19
AU2002235510A1 (en) 2002-08-28
KR100914503B1 (ko) 2009-08-31
EP1380114B1 (en) 2010-04-28
HK1062088A1 (en) 2004-10-15
EP1380114A2 (en) 2004-01-14
KR20040052476A (ko) 2004-06-23
ATE466410T1 (de) 2010-05-15
DE60236147D1 (de) 2010-06-10
WO2002065644A2 (en) 2002-08-22

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