MX2017016201A - Asignacion masiva de bloques de instruccion a una ventana de instruccion de procesador. - Google Patents

Asignacion masiva de bloques de instruccion a una ventana de instruccion de procesador.

Info

Publication number
MX2017016201A
MX2017016201A MX2017016201A MX2017016201A MX2017016201A MX 2017016201 A MX2017016201 A MX 2017016201A MX 2017016201 A MX2017016201 A MX 2017016201A MX 2017016201 A MX2017016201 A MX 2017016201A MX 2017016201 A MX2017016201 A MX 2017016201A
Authority
MX
Mexico
Prior art keywords
instructions
instruction
block
bulk
bulk allocation
Prior art date
Application number
MX2017016201A
Other languages
English (en)
Inventor
Smith Aaron
C Burger Douglas
Gray Jan
Original Assignee
Microsoft Technology Licensing Llc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Microsoft Technology Licensing Llc filed Critical Microsoft Technology Licensing Llc
Publication of MX2017016201A publication Critical patent/MX2017016201A/es

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
    • G06F9/3854—Instruction completion, e.g. retiring, committing or graduating
    • G06F9/3858—Result writeback, i.e. updating the architectural state or memory
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/0802—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
    • G06F12/0875—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches with dedicated cache, e.g. instruction or stack
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
    • G06F9/3802—Instruction prefetching
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
    • G06F9/3836—Instruction issuing, e.g. dynamic instruction scheduling or out of order instruction execution
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
    • G06F9/3836—Instruction issuing, e.g. dynamic instruction scheduling or out of order instruction execution
    • G06F9/3853—Instruction issuing, e.g. dynamic instruction scheduling or out of order instruction execution of compound instructions
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F2212/00—Indexing scheme relating to accessing, addressing or allocation within memory systems or architectures
    • G06F2212/45—Caching of specific data in cache memory
    • G06F2212/452—Instruction code

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Software Systems (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Devices For Executing Special Programs (AREA)
  • Executing Machine-Instructions (AREA)
  • Advance Control (AREA)
  • Memory System Of A Hierarchy Structure (AREA)

Abstract

Un núcleo de procesador en una microestructura basada en bloque de instrucción incluye una unidad de control que asigna, de manera masiva, instrucciones en una ventana de instrucción al extraer los bloques de instrucción y recursos asociados incluyendo bits de control y operandos a la vez. Dicha asignación masiva soporta la eficiencia incrementada en el núcleo de procesador al habilitar el manejo consistente y la implementación de política a través de todas las instrucciones en el bloque durante la ejecución. Por ejemplo, cuando un bloque de instrucción se ramifica en sí mismo, puede ser reutilizado en un proceso de actualización en lugar de volver a ser extraído de la memoria caché de instrucción. Ya que todos los recursos para ese bloque de instrucción están en un lugar, las instrucciones pueden permanecer en su lugar y solo los bits válidos tienen que ser borrados. La asignación masiva también facilita la compartición de operando por instrucciones en un bloque y mensajería explícita entre instrucciones.
MX2017016201A 2015-06-26 2016-06-23 Asignacion masiva de bloques de instruccion a una ventana de instruccion de procesador. MX2017016201A (es)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US14/752,685 US9720693B2 (en) 2015-06-26 2015-06-26 Bulk allocation of instruction blocks to a processor instruction window
PCT/US2016/038851 WO2016210028A1 (en) 2015-06-26 2016-06-23 Bulk allocation of instruction blocks to a processor instruction window

Publications (1)

Publication Number Publication Date
MX2017016201A true MX2017016201A (es) 2018-03-01

Family

ID=56551534

Family Applications (1)

Application Number Title Priority Date Filing Date
MX2017016201A MX2017016201A (es) 2015-06-26 2016-06-23 Asignacion masiva de bloques de instruccion a una ventana de instruccion de procesador.

Country Status (15)

Country Link
US (1) US9720693B2 (es)
EP (1) EP3314406B1 (es)
JP (1) JP2018518776A (es)
KR (1) KR102575940B1 (es)
CN (1) CN107810482B (es)
AU (1) AU2016281600A1 (es)
BR (1) BR112017024362A2 (es)
CA (1) CA2986269A1 (es)
CL (1) CL2017003318A1 (es)
CO (1) CO2017013277A2 (es)
HK (1) HK1246441A1 (es)
IL (1) IL256170A (es)
MX (1) MX2017016201A (es)
PH (1) PH12017550126A1 (es)
WO (1) WO2016210028A1 (es)

Families Citing this family (12)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US9940136B2 (en) 2015-06-26 2018-04-10 Microsoft Technology Licensing, Llc Reuse of decoded instructions
US10175988B2 (en) 2015-06-26 2019-01-08 Microsoft Technology Licensing, Llc Explicit instruction scheduler state information for a processor
US10191747B2 (en) 2015-06-26 2019-01-29 Microsoft Technology Licensing, Llc Locking operand values for groups of instructions executed atomically
US10409599B2 (en) 2015-06-26 2019-09-10 Microsoft Technology Licensing, Llc Decoding information about a group of instructions including a size of the group of instructions
US10409606B2 (en) 2015-06-26 2019-09-10 Microsoft Technology Licensing, Llc Verifying branch targets
US10346168B2 (en) 2015-06-26 2019-07-09 Microsoft Technology Licensing, Llc Decoupled processor instruction window and operand buffer
US11755484B2 (en) 2015-06-26 2023-09-12 Microsoft Technology Licensing, Llc Instruction block allocation
US10095519B2 (en) 2015-09-19 2018-10-09 Microsoft Technology Licensing, Llc Instruction block address register
CN110851073B (zh) 2018-08-20 2023-06-02 慧荣科技股份有限公司 储存装置及巨集指令的执行方法
CN110851372B (zh) 2018-08-20 2023-10-31 慧荣科技股份有限公司 储存装置及快取区定址方法
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US20240036760A1 (en) * 2022-07-28 2024-02-01 Arm Limited Control of bulk memory instructions

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Also Published As

Publication number Publication date
US9720693B2 (en) 2017-08-01
JP2018518776A (ja) 2018-07-12
KR20180021165A (ko) 2018-02-28
BR112017024362A2 (pt) 2018-07-31
HK1246441A1 (zh) 2018-09-07
EP3314406B1 (en) 2020-10-14
CO2017013277A2 (es) 2018-01-16
KR102575940B1 (ko) 2023-09-06
WO2016210028A1 (en) 2016-12-29
IL256170A (en) 2018-02-28
CN107810482A (zh) 2018-03-16
CA2986269A1 (en) 2016-12-29
EP3314406A1 (en) 2018-05-02
CL2017003318A1 (es) 2018-06-29
US20160378493A1 (en) 2016-12-29
PH12017550126A1 (en) 2018-02-26
CN107810482B (zh) 2021-10-22
AU2016281600A1 (en) 2017-12-07

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