MX2016013399A - Circuito para generar señales de fase de reloj precisas para serdes de alta velocidad. - Google Patents

Circuito para generar señales de fase de reloj precisas para serdes de alta velocidad.

Info

Publication number
MX2016013399A
MX2016013399A MX2016013399A MX2016013399A MX2016013399A MX 2016013399 A MX2016013399 A MX 2016013399A MX 2016013399 A MX2016013399 A MX 2016013399A MX 2016013399 A MX2016013399 A MX 2016013399A MX 2016013399 A MX2016013399 A MX 2016013399A
Authority
MX
Mexico
Prior art keywords
clock signals
differential
cml
cmos
clock
Prior art date
Application number
MX2016013399A
Other languages
English (en)
Inventor
Arcudia Kenneth
Chen Zhiqin
Original Assignee
Qualcomm Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Qualcomm Inc filed Critical Qualcomm Inc
Publication of MX2016013399A publication Critical patent/MX2016013399A/es

Links

Classifications

    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K5/00—Manipulating of pulses not covered by one of the other main groups of this subclass
    • H03K5/156—Arrangements in which a continuous pulse train is transformed into a train having a desired pattern
    • H03K5/1565—Arrangements in which a continuous pulse train is transformed into a train having a desired pattern the output pulses having a constant duty cycle
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
    • H03L7/00—Automatic control of frequency or phase; Synchronisation
    • H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
    • H03L7/00—Automatic control of frequency or phase; Synchronisation
    • H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
    • H03L7/08—Details of the phase-locked loop
    • H03L7/0807—Details of the phase-locked loop concerning mainly a recovery circuit for the reference signal
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
    • H03L7/00—Automatic control of frequency or phase; Synchronisation
    • H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
    • H03L7/08—Details of the phase-locked loop
    • H03L7/081—Details of the phase-locked loop provided with an additional controlled phase shifter
    • H03L7/0812—Details of the phase-locked loop provided with an additional controlled phase shifter and where no voltage or current controlled oscillator is used
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
    • H03L7/00—Automatic control of frequency or phase; Synchronisation
    • H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
    • H03L7/08—Details of the phase-locked loop
    • H03L7/081—Details of the phase-locked loop provided with an additional controlled phase shifter
    • H03L7/0812—Details of the phase-locked loop provided with an additional controlled phase shifter and where no voltage or current controlled oscillator is used
    • H03L7/0814—Details of the phase-locked loop provided with an additional controlled phase shifter and where no voltage or current controlled oscillator is used the phase shifting device being digitally controlled
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M9/00—Parallel/series conversion or vice versa

Landscapes

  • Physics & Mathematics (AREA)
  • Nonlinear Science (AREA)
  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Pulse Circuits (AREA)
  • Stabilization Of Oscillater, Synchronisation, Frequency Synthesizers (AREA)
  • Manipulation Of Pulses (AREA)

Abstract

Se divulgan sistemas y métodos para generar señales de fase de reloj con relaciones de temporización precisas; por ejemplo, cuatro señales de reloj separadas por 90 grados pueden ser generadas a partir de señales de reloj CML diferenciales; un convertidor CML a CMOS convierte las señales de reloj CML diferenciales en señales de reloj CMOS diferenciales y proporciona la corrección de ciclo de trabajo; células de retraso producen señales de reloj retrasadas a partir de la señales de reloj CMOS diferenciales; las señales de reloj CMOS diferenciales y las señales de reloj retrasadas se combinan lógicamente para producir cuatro señales de reloj de cuarto con tiempos activos de periodo de reloj de un cuarto; pasadores de establecer-restablecer producen las cuatro señales de reloj a partir de la señales de reloj de cuarto; un módulo de calibración controla los retrasos de las células de retraso y controla la corrección del ciclo de trabajo del convertidor CML a CMOS para ajustar las relaciones de temporización de las cuatro señales de reloj; las cuatro señales de reloj pueden ser utilizadas, por ejemplo, en un deserializador.
MX2016013399A 2014-04-21 2015-03-11 Circuito para generar señales de fase de reloj precisas para serdes de alta velocidad. MX2016013399A (es)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US14/257,913 US9225324B2 (en) 2014-04-21 2014-04-21 Circuit for generating accurate clock phase signals for high-speed SERDES
PCT/US2015/019970 WO2015163988A1 (en) 2014-04-21 2015-03-11 Circuit for generating accurate clock phase dignals for a high-speed serializer/deserializere

Publications (1)

Publication Number Publication Date
MX2016013399A true MX2016013399A (es) 2017-02-15

Family

ID=52780034

Family Applications (1)

Application Number Title Priority Date Filing Date
MX2016013399A MX2016013399A (es) 2014-04-21 2015-03-11 Circuito para generar señales de fase de reloj precisas para serdes de alta velocidad.

Country Status (10)

Country Link
US (1) US9225324B2 (es)
EP (1) EP3134973B1 (es)
JP (1) JP6133523B1 (es)
KR (1) KR101694926B1 (es)
CN (1) CN106464260B (es)
BR (1) BR112016024426A2 (es)
ES (1) ES2646551T3 (es)
HU (1) HUE033627T2 (es)
MX (1) MX2016013399A (es)
WO (1) WO2015163988A1 (es)

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US10680592B2 (en) * 2017-10-19 2020-06-09 Xilinx, Inc. Quadrature clock correction circuit for transmitters
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KR102204356B1 (ko) * 2018-07-06 2021-01-18 한국전자기술연구원 저전력 펄스폭변조 송신기
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KR20220001578A (ko) 2020-06-30 2022-01-06 삼성전자주식회사 대칭적인 구조를 갖는 클럭 변환 회로
KR20220098854A (ko) 2021-01-05 2022-07-12 에스케이하이닉스 주식회사 지연 변동을 보상하는 반도체 장치 및 이를 포함하는 클록 전달 회로
CN116185925A (zh) * 2021-11-29 2023-05-30 深圳市中兴微电子技术有限公司 时钟链路、电子设备
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Also Published As

Publication number Publication date
WO2015163988A9 (en) 2016-11-24
US9225324B2 (en) 2015-12-29
KR101694926B1 (ko) 2017-01-10
ES2646551T3 (es) 2017-12-14
JP6133523B1 (ja) 2017-05-24
KR20160126086A (ko) 2016-11-01
CN106464260B (zh) 2019-04-26
BR112016024426A2 (pt) 2017-08-15
WO2015163988A1 (en) 2015-10-29
HUE033627T2 (en) 2017-12-28
EP3134973B1 (en) 2017-09-13
EP3134973A1 (en) 2017-03-01
US20150303909A1 (en) 2015-10-22
CN106464260A (zh) 2017-02-22
JP2017517937A (ja) 2017-06-29

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