MX171698B - Circuito de regularizacion y evaluacion del regimen de circuitos virtuales, que utiliza una via de transmision de multiplexaje temporal asincronico - Google Patents

Circuito de regularizacion y evaluacion del regimen de circuitos virtuales, que utiliza una via de transmision de multiplexaje temporal asincronico

Info

Publication number
MX171698B
MX171698B MX022797A MX2279790A MX171698B MX 171698 B MX171698 B MX 171698B MX 022797 A MX022797 A MX 022797A MX 2279790 A MX2279790 A MX 2279790A MX 171698 B MX171698 B MX 171698B
Authority
MX
Mexico
Prior art keywords
virtual circuit
cells
asynchronous
regularization
buffers
Prior art date
Application number
MX022797A
Other languages
English (en)
Spanish (es)
Inventor
Denis Le Bihan
Original Assignee
Alcatel Nv
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Priority claimed from FR8913342A external-priority patent/FR2653285B1/fr
Priority claimed from FR8913341A external-priority patent/FR2653284B1/fr
Application filed by Alcatel Nv filed Critical Alcatel Nv
Publication of MX171698B publication Critical patent/MX171698B/es

Links

Classifications

    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04J—MULTIPLEX COMMUNICATION
    • H04J3/00—Time-division multiplex systems

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Networks & Wireless Communication (AREA)
  • Signal Processing (AREA)
  • Data Exchanges In Wide-Area Networks (AREA)
  • Time-Division Multiplex Systems (AREA)
MX022797A 1989-10-12 1990-10-11 Circuito de regularizacion y evaluacion del regimen de circuitos virtuales, que utiliza una via de transmision de multiplexaje temporal asincronico MX171698B (es)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
FR8913342A FR2653285B1 (fr) 1989-10-12 1989-10-12 Dispositif d'evaluation du debit de circuits virtuels empruntant une voie de transmission a multiplexage temporel asynchrone.
FR8913341A FR2653284B1 (fr) 1989-10-12 1989-10-12 Dispositif de regularisation de debit de circuit virtuels empruntant une voie de transmission a multiplexage temporel asynchrone.

Publications (1)

Publication Number Publication Date
MX171698B true MX171698B (es) 1993-11-10

Family

ID=26227595

Family Applications (1)

Application Number Title Priority Date Filing Date
MX022797A MX171698B (es) 1989-10-12 1990-10-11 Circuito de regularizacion y evaluacion del regimen de circuitos virtuales, que utiliza una via de transmision de multiplexaje temporal asincronico

Country Status (6)

Country Link
JP (1) JP2862659B2 (zh)
KR (1) KR0168422B1 (zh)
CN (1) CN1029446C (zh)
AU (2) AU625628B2 (zh)
MX (1) MX171698B (zh)
RU (1) RU2098920C1 (zh)

Families Citing this family (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
FR2657482B1 (fr) * 1990-01-19 1993-12-31 Boyer Pierre Methode et systeme de lissage et de controle de debits de communications temporelles asynchrones.
JP3947424B2 (ja) * 2002-05-02 2007-07-18 株式会社エヌ・ティ・ティ・ドコモ パケット送信制御装置、移動ノード、制御ノード、パケット通信方法、及びパケット通信システム
GB0211173D0 (en) 2002-05-16 2002-06-26 Zarlink Semiconductor Inc Virtual counter for data rate conversion
KR101676857B1 (ko) * 2015-12-18 2016-11-17 (주)세라테크 개폐 커버가 구비된 건식 족욕기

Family Cites Families (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4475192A (en) * 1982-02-16 1984-10-02 At&T Bell Laboratories Data packet flow control scheme for switching networks
US4583219A (en) * 1984-07-16 1986-04-15 At&T Bell Laboratories Trunk for packet switching
US4630261A (en) * 1984-07-30 1986-12-16 International Business Machines Corp. Integrated buffer management and signaling technique
FR2616024B1 (fr) * 1987-05-26 1989-07-21 Quinquis Jean Paul Systeme et methode de controle de flux de paquets
FR2616025B1 (fr) * 1987-05-26 1989-07-21 Lespagnol Albert Methode et systeme de controle de flux de paquets
DE3732937A1 (de) * 1987-09-30 1989-04-20 Philips Patentverwaltung Schaltungsanordnung zur vermeidung von ueberlast in einem breitband-vermittlungssystem

Also Published As

Publication number Publication date
CN1029446C (zh) 1995-08-02
KR910008997A (ko) 1991-05-31
AU6397590A (en) 1991-04-18
KR0168422B1 (ko) 1999-02-01
AU1716192A (en) 1992-07-30
AU625628B2 (en) 1992-07-16
CN1050960A (zh) 1991-04-24
JPH03150944A (ja) 1991-06-27
AU636097B2 (en) 1993-04-08
RU2098920C1 (ru) 1997-12-10
JP2862659B2 (ja) 1999-03-03

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