MX169668B - Sistema de procesamiento de datos con administracion de recursos del sistema para si mismo y para una procesadora extraña asociada - Google Patents

Sistema de procesamiento de datos con administracion de recursos del sistema para si mismo y para una procesadora extraña asociada

Info

Publication number
MX169668B
MX169668B MX020739A MX2073990A MX169668B MX 169668 B MX169668 B MX 169668B MX 020739 A MX020739 A MX 020739A MX 2073990 A MX2073990 A MX 2073990A MX 169668 B MX169668 B MX 169668B
Authority
MX
Mexico
Prior art keywords
processors
operating system
pairs
processor
memory
Prior art date
Application number
MX020739A
Other languages
English (en)
Inventor
John Mario Loffredo
Kenneth Russell Sanderson
Gustavo Armando Suarez
John Monroe Dinwiddie Jr
Bobby Joe Freeman
Lonnie Edward Grice
Original Assignee
Ibm
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Ibm filed Critical Ibm
Publication of MX169668B publication Critical patent/MX169668B/es

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring
    • G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
    • G06F11/16—Error detection or correction of the data by redundancy in hardware
    • G06F11/1658—Data re-synchronization of a redundant component, or initial sync of replacement, additional or spare unit
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring
    • G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
    • G06F11/16—Error detection or correction of the data by redundancy in hardware
    • G06F11/1629—Error detection by comparing the output of redundant processing systems
    • G06F11/1641—Error detection by comparing the output of redundant processing systems where the comparison is not performed by the redundant processing components
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring
    • G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
    • G06F11/16—Error detection or correction of the data by redundancy in hardware
    • G06F11/1675—Temporal synchronisation or re-synchronisation of redundant processing components
    • G06F11/1679—Temporal synchronisation or re-synchronisation of redundant processing components at clock signal level
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F15/00—Digital computers in general; Data processing equipment in general
    • G06F15/16—Combinations of two or more digital computers each having at least an arithmetic unit, a program unit and a register, e.g. for a simultaneous processing of several programs
    • G06F15/177—Initialisation or configuration control
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L69/00—Network arrangements, protocols or services independent of the application payload and not provided for in the other groups of this subclass
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring
    • G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
    • G06F11/16—Error detection or correction of the data by redundancy in hardware
    • G06F11/1608—Error detection by comparing the output signals of redundant hardware

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • Quality & Reliability (AREA)
  • Computer Hardware Design (AREA)
  • Signal Processing (AREA)
  • Computer Networks & Wireless Communication (AREA)
  • Computer Security & Cryptography (AREA)
  • Software Systems (AREA)
  • Hardware Redundancy (AREA)
  • Multi Processors (AREA)
  • Steering-Linkage Mechanisms And Four-Wheel Steering (AREA)
  • Soil Working Implements (AREA)
  • Debugging And Monitoring (AREA)
  • Memory System Of A Hierarchy Structure (AREA)

Abstract

La presente invención se refiere a en un sistema de procesamiento de datos del tipo en el cual las rutinas de inicialización del sistema controlan la auto-prueba y la inicialización de cada uno de un primer par y un segundo par socio de procesadoras, y su respectivo hardware asociado, donde cada par de procesadoras y su hardware asociado es sacado hacia una operación de paso seguro con el otro par, sobre la auto-prueba e inicialización satisfactorias, y donde los pares de procesadoras y su hardware efectúan posteriormente operaciones idénticas en paso seguro bajo el control de un primer sistema operativo, y programas que tienen una primera arquitectura de instrucción, comprendiendo la mejora: un primer par adicional de procesadoras y un par socio adicional de procesadoras, adaptado cada par para efectuar operaciones idénticas bajo el control de un segundo sistema operativo, y programas que tienen una segunda arquitectura de instrucción; un elemento para acoplar directamente cada procesadora de los pares adicionales con una procesadora respectiva del primero y segundo par socios; un elemento lógico controlado por instrucciones de programa de aplicación que se ejecutan en el primero y segundo pares socios de procesadoras, para desacoplar el primero y segundo pares socios de procesadoras de su hardware asociado, y acoplar concurrentemente el primero y segundo pares socios de procesadoras con procesadoras respectivas en los pares adicionales, por medio de dicho elemento de acoplamiento directo para la transferencia de comandos y datos entre los mismos; un elemento controlado por el programa de aplicación asociado con el primro y segundo pares socios de procesadoras, para iniciar y controlar la auto-prueba de la inicialización de los pares adicionales de procesadoras, por medio de comandos y datos aplicados a dicho elemento de acoplamiento directo, mientras que el primer par de procesadoras son desacopladas de su hardware; un segundo elemento lógico efectivo durante la inicialización del sistema, para inhibir el sacado del primero y segundo pares socios de procesadoras, hacia la operación de paso seguro, hasta que los pares adicionales de procesadoras son auto-probados e inicializado de una manera indiscernible para el primer sistema operativo; y un elemento que inicia el sacado concurrente de los primero y segundo pares socios de procesadoras, y el sacado de dicho primer par adicional y pares socios de procesadoras en operación de paso seguro al completarse toda la auto-prueba e inicialización de una manera indiscernible para el primer sistema operativo.
MX020739A 1989-05-17 1990-05-16 Sistema de procesamiento de datos con administracion de recursos del sistema para si mismo y para una procesadora extraña asociada MX169668B (es)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US07/353,112 US5113522A (en) 1989-05-17 1989-05-17 Data processing system with system resource management for itself and for an associated alien processor

Publications (1)

Publication Number Publication Date
MX169668B true MX169668B (es) 1993-07-16

Family

ID=23387808

Family Applications (1)

Application Number Title Priority Date Filing Date
MX020739A MX169668B (es) 1989-05-17 1990-05-16 Sistema de procesamiento de datos con administracion de recursos del sistema para si mismo y para una procesadora extraña asociada

Country Status (9)

Country Link
US (1) US5113522A (es)
EP (1) EP0405736B1 (es)
JP (1) JP2618075B2 (es)
AT (1) ATE161341T1 (es)
BR (1) BR9002303A (es)
CA (1) CA2009550C (es)
DE (1) DE69031815T2 (es)
MX (1) MX169668B (es)
SG (1) SG43796A1 (es)

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JPH0375863A (ja) 1991-03-29
CA2009550A1 (en) 1990-11-17
DE69031815D1 (de) 1998-01-29
EP0405736A3 (es) 1994-02-02
DE69031815T2 (de) 1998-06-25
BR9002303A (pt) 1991-07-30
CA2009550C (en) 1995-08-08
EP0405736B1 (en) 1997-12-17
EP0405736A2 (en) 1991-01-02
US5113522A (en) 1992-05-12
ATE161341T1 (de) 1998-01-15
JP2618075B2 (ja) 1997-06-11
SG43796A1 (en) 1997-11-14

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