MX161925A - Mejoras en sistema procesador de datos con memoria principal - Google Patents

Mejoras en sistema procesador de datos con memoria principal

Info

Publication number
MX161925A
MX161925A MX5087A MX508787A MX161925A MX 161925 A MX161925 A MX 161925A MX 5087 A MX5087 A MX 5087A MX 508787 A MX508787 A MX 508787A MX 161925 A MX161925 A MX 161925A
Authority
MX
Mexico
Prior art keywords
data processing
processing system
main memory
memory
main
Prior art date
Application number
MX5087A
Other languages
English (en)
Spanish (es)
Inventor
John F Henry Jr
Paul J Natusch
David C Senerchia
Original Assignee
Digital Equipment Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Digital Equipment Corp filed Critical Digital Equipment Corp
Publication of MX161925A publication Critical patent/MX161925A/es

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/06—Addressing a physical block of locations, e.g. base addressing, module addressing, memory dedication
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/06—Addressing a physical block of locations, e.g. base addressing, module addressing, memory dedication
    • G06F12/0607—Interleaved addressing
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C8/00—Arrangements for selecting an address in a digital store
    • G11C8/18—Address timing or clocking circuits; Address control signal generation or management, e.g. for row address strobe [RAS] or column address strobe [CAS] signals

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Static Random-Access Memory (AREA)
  • Dram (AREA)
MX5087A 1986-01-29 1987-01-29 Mejoras en sistema procesador de datos con memoria principal MX161925A (es)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US06/823,951 US4791552A (en) 1986-01-29 1986-01-29 Apparatus and method for addressing semiconductor arrays in a main memory unit on consecutive system clock cycles

Publications (1)

Publication Number Publication Date
MX161925A true MX161925A (es) 1991-03-06

Family

ID=25240223

Family Applications (1)

Application Number Title Priority Date Filing Date
MX5087A MX161925A (es) 1986-01-29 1987-01-29 Mejoras en sistema procesador de datos con memoria principal

Country Status (10)

Country Link
US (1) US4791552A (instruction)
KR (1) KR910004398B1 (instruction)
CN (1) CN1007843B (instruction)
AU (1) AU6932387A (instruction)
CA (1) CA1275329C (instruction)
ES (1) ES2002952A6 (instruction)
IL (1) IL81426A (instruction)
IN (1) IN170451B (instruction)
MX (1) MX161925A (instruction)
WO (1) WO1987004822A1 (instruction)

Families Citing this family (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP3215105B2 (ja) * 1990-08-24 2001-10-02 富士通株式会社 メモリアクセス装置
JP2740063B2 (ja) * 1990-10-15 1998-04-15 株式会社東芝 半導体記憶装置
US6941428B2 (en) 2002-09-25 2005-09-06 International Business Machines Corporation Memory controller optimization
US8200887B2 (en) * 2007-03-29 2012-06-12 Violin Memory, Inc. Memory management system and method
US9093445B2 (en) * 2011-08-26 2015-07-28 International Business Machines Corporation Packaging identical chips in a stacked structure

Family Cites Families (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3753014A (en) * 1971-03-15 1973-08-14 Burroughs Corp Fast inhibit gate with applications
US3931613A (en) * 1974-09-25 1976-01-06 Data General Corporation Data processing system
GB1536853A (en) * 1975-05-01 1978-12-20 Plessey Co Ltd Data processing read and hold facility
US4378589A (en) * 1976-12-27 1983-03-29 International Business Machines Corporation Undirectional looped bus microcomputer architecture
US4435757A (en) * 1979-07-25 1984-03-06 The Singer Company Clock control for digital computer
US4287563A (en) * 1979-11-13 1981-09-01 Motorola, Inc. Versatile microprocessor bus interface
US4393461A (en) * 1980-10-06 1983-07-12 Honeywell Information Systems Inc. Communications subsystem having a self-latching data monitor and storage device
US4631659A (en) * 1984-03-08 1986-12-23 Texas Instruments Incorporated Memory interface with automatic delay state
JPS618785A (ja) * 1984-06-21 1986-01-16 Fujitsu Ltd 記憶装置アクセス制御方式

Also Published As

Publication number Publication date
AU6932387A (en) 1987-08-25
KR880700971A (ko) 1988-04-13
ES2002952A6 (es) 1988-10-01
CN1007843B (zh) 1990-05-02
IL81426A (en) 1990-11-29
KR910004398B1 (ko) 1991-06-27
IN170451B (instruction) 1992-03-28
IL81426A0 (en) 1987-08-31
WO1987004822A1 (en) 1987-08-13
US4791552A (en) 1988-12-13
CN87101605A (zh) 1987-12-30
CA1275329C (en) 1990-10-16

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