KR880700972A - 페이지 메모리 처리장치 - Google Patents

페이지 메모리 처리장치

Info

Publication number
KR880700972A
KR880700972A KR870700828A KR870700828A KR880700972A KR 880700972 A KR880700972 A KR 880700972A KR 870700828 A KR870700828 A KR 870700828A KR 870700828 A KR870700828 A KR 870700828A KR 880700972 A KR880700972 A KR 880700972A
Authority
KR
South Korea
Prior art keywords
processing device
page memory
memory processing
page
processing
Prior art date
Application number
KR870700828A
Other languages
English (en)
Other versions
KR940011668B1 (ko
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed filed Critical
Publication of KR880700972A publication Critical patent/KR880700972A/ko
Application granted granted Critical
Publication of KR940011668B1 publication Critical patent/KR940011668B1/ko

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/10—Address translation
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/14—Protection against unauthorised use of memory or access to memory
    • G06F12/1416—Protection against unauthorised use of memory or access to memory by checking the object accessibility, e.g. type of access defined by the memory independently of subject rights
    • G06F12/145—Protection against unauthorised use of memory or access to memory by checking the object accessibility, e.g. type of access defined by the memory independently of subject rights the protection being virtual, e.g. for virtual blocks or segments before a translation mechanism
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/0802—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
    • G06F12/0877—Cache access modes
    • G06F12/0882—Page mode
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/10—Address translation
    • G06F12/1027—Address translation using associative or pseudo-associative address translation means, e.g. translation look-aside buffer [TLB]
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/10—Address translation
    • G06F12/1027—Address translation using associative or pseudo-associative address translation means, e.g. translation look-aside buffer [TLB]
    • G06F12/1045—Address translation using associative or pseudo-associative address translation means, e.g. translation look-aside buffer [TLB] associated with a data cache

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Security & Cryptography (AREA)
  • Memory System Of A Hierarchy Structure (AREA)
  • Storage Device Security (AREA)
KR1019870700828A 1986-01-15 1986-11-06 페이지 메모리 관리 장치 KR940011668B1 (ko)

Applications Claiming Priority (4)

Application Number Priority Date Filing Date Title
US06/819,180 US4763244A (en) 1986-01-15 1986-01-15 Paged memory management unit capable of selectively supporting multiple address spaces
US819,180 1986-01-15
PCT/US1986/002378 WO1987004544A1 (en) 1986-01-15 1986-11-06 Paged memory management unit capable of selectively supporting multiple address spaces
USPUS86/02378 1986-11-06

Publications (2)

Publication Number Publication Date
KR880700972A true KR880700972A (ko) 1988-04-13
KR940011668B1 KR940011668B1 (ko) 1994-12-23

Family

ID=25227414

Family Applications (1)

Application Number Title Priority Date Filing Date
KR1019870700828A KR940011668B1 (ko) 1986-01-15 1986-11-06 페이지 메모리 관리 장치

Country Status (6)

Country Link
US (2) US4763244A (ko)
EP (1) EP0253824B1 (ko)
JP (1) JP2567594B2 (ko)
KR (1) KR940011668B1 (ko)
DE (1) DE3688978T2 (ko)
WO (1) WO1987004544A1 (ko)

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US5023773A (en) * 1988-02-10 1991-06-11 International Business Machines Corporation Authorization for selective program access to data in multiple address spaces
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US5239635A (en) * 1988-06-06 1993-08-24 Digital Equipment Corporation Virtual address to physical address translation using page tables in virtual memory
US5247632A (en) * 1989-01-23 1993-09-21 Eastman Kodak Company Virtual memory management arrangement for addressing multi-dimensional arrays in a digital data processing system
US5121487A (en) * 1989-02-21 1992-06-09 Sun Microsystems, Inc. High speed bus with virtual memory data transfer capability using virtual address/data lines
US5237668A (en) * 1989-10-20 1993-08-17 International Business Machines Corporation Process using virtual addressing in a non-privileged instruction to control the copying of a page of data in or between multiple media
US5226133A (en) * 1989-12-01 1993-07-06 Silicon Graphics, Inc. Two-level translation look-aside buffer using partial addresses for enhanced speed
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US5197130A (en) * 1989-12-29 1993-03-23 Supercomputer Systems Limited Partnership Cluster architecture for a highly parallel scalar/vector multiprocessor system
WO1991014986A1 (en) * 1990-03-23 1991-10-03 Eastman Kodak Company Virtual memory management and allocation arrangement for digital data processing system
US5263142A (en) * 1990-04-12 1993-11-16 Sun Microsystems, Inc. Input/output cache with mapped pages allocated for caching direct (virtual) memory access input/output data based on type of I/O devices
US5410671A (en) * 1990-05-01 1995-04-25 Cyrix Corporation Data compression/decompression processor
US5355469A (en) * 1990-07-30 1994-10-11 Delphi Data, A Division Of Sparks Industries, Inc. Method for detecting program errors
US5771368A (en) * 1990-10-29 1998-06-23 Sun Microsystems, Inc. Memory addressing scheme for increasing the number of memory locations available in a computer for storing higher precision numbers
GB2251102B (en) * 1990-12-21 1995-03-15 Sun Microsystems Inc Translation lookaside buffer
US5285528A (en) * 1991-02-22 1994-02-08 International Business Machines Corporation Data structures and algorithms for managing lock states of addressable element ranges
US5640528A (en) * 1991-10-24 1997-06-17 Intel Corporation Method and apparatus for translating addresses using mask and replacement value registers
US5627987A (en) * 1991-11-29 1997-05-06 Kabushiki Kaisha Toshiba Memory management and protection system for virtual memory in computer system
US5696925A (en) * 1992-02-25 1997-12-09 Hyundai Electronics Industries, Co., Ltd. Memory management unit with address translation function
JP2839060B2 (ja) * 1992-03-02 1998-12-16 インターナショナル・ビジネス・マシーンズ・コーポレイション データ処理システムおよびデータ処理方法
US5493661A (en) * 1992-03-06 1996-02-20 International Business Machines Corporation Method and system for providing a program call to a dispatchable unit's base space
WO1993018461A1 (en) * 1992-03-09 1993-09-16 Auspex Systems, Inc. High-performance non-volatile ram protected write cache accelerator system
US5555395A (en) * 1993-05-28 1996-09-10 Dell U.S.A. L.P. System for memory table cache reloads in a reduced number of cycles using a memory controller to set status bits in the main memory table
US5682495A (en) * 1994-12-09 1997-10-28 International Business Machines Corporation Fully associative address translation buffer having separate segment and page invalidation
US5752275A (en) * 1995-03-31 1998-05-12 Intel Corporation Translation look-aside buffer including a single page size translation unit
US5724604A (en) * 1995-08-02 1998-03-03 Motorola, Inc. Data processing system for accessing an external device and method therefor
US5802541A (en) * 1996-02-28 1998-09-01 Motorola, Inc. Method and apparatus in a data processing system for using chip selects to perform a memory management function
US5914730A (en) * 1997-09-09 1999-06-22 Compaq Computer Corp. System and method for invalidating and updating individual GART table entries for accelerated graphics port transaction requests
US6249906B1 (en) * 1998-06-26 2001-06-19 International Business Machines Corp. Adaptive method and system to minimize the effect of long table walks
EP1471421A1 (en) * 2003-04-24 2004-10-27 STMicroelectronics Limited Speculative load instruction control
US7739524B2 (en) * 2005-08-29 2010-06-15 The Invention Science Fund I, Inc Power consumption management
US8516300B2 (en) * 2005-08-29 2013-08-20 The Invention Science Fund I, Llc Multi-votage synchronous systems
US7877584B2 (en) * 2005-08-29 2011-01-25 The Invention Science Fund I, Llc Predictive processor resource management
US8402257B2 (en) * 2005-08-29 2013-03-19 The Invention Science Fund I, PLLC Alteration of execution of a program in response to an execution-optimization information
US7774558B2 (en) * 2005-08-29 2010-08-10 The Invention Science Fund I, Inc Multiprocessor resource optimization
US7493516B2 (en) * 2005-08-29 2009-02-17 Searete Llc Hardware-error tolerant computing
US8209524B2 (en) * 2005-08-29 2012-06-26 The Invention Science Fund I, Llc Cross-architecture optimization
US7779213B2 (en) * 2005-08-29 2010-08-17 The Invention Science Fund I, Inc Optimization of instruction group execution through hardware resource management policies
US8255745B2 (en) * 2005-08-29 2012-08-28 The Invention Science Fund I, Llc Hardware-error tolerant computing
US8214191B2 (en) * 2005-08-29 2012-07-03 The Invention Science Fund I, Llc Cross-architecture execution optimization
US20070050605A1 (en) * 2005-08-29 2007-03-01 Bran Ferren Freeze-dried ghost pages
US7725693B2 (en) * 2005-08-29 2010-05-25 Searete, Llc Execution optimization using a processor resource management policy saved in an association with an instruction group
US8181004B2 (en) * 2005-08-29 2012-05-15 The Invention Science Fund I, Llc Selecting a resource management policy for a resource available to a processor
US7644251B2 (en) * 2005-12-19 2010-01-05 Sigmatel, Inc. Non-volatile solid-state memory controller
US7376807B2 (en) * 2006-02-23 2008-05-20 Freescale Semiconductor, Inc. Data processing system having address translation bypass and method therefor
US7401201B2 (en) * 2006-04-28 2008-07-15 Freescale Semiconductor, Inc. Processor and method for altering address translation
US9697211B1 (en) * 2006-12-01 2017-07-04 Synopsys, Inc. Techniques for creating and using a hierarchical data structure
US8621154B1 (en) 2008-04-18 2013-12-31 Netapp, Inc. Flow based reply cache
US8161236B1 (en) 2008-04-23 2012-04-17 Netapp, Inc. Persistent reply cache integrated with file system
US8171227B1 (en) 2009-03-11 2012-05-01 Netapp, Inc. System and method for managing a flow based reply cache
TWI492051B (zh) * 2012-09-05 2015-07-11 Silicon Motion Inc 資料儲存裝置與快閃記憶體控制方法
US10846235B2 (en) 2018-04-28 2020-11-24 International Business Machines Corporation Integrated circuit and data processing system supporting attachment of a real address-agnostic accelerator

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US4718008A (en) * 1986-01-16 1988-01-05 International Business Machines Corporation Method to control paging subsystem processing in a virtual memory data processing system during execution of critical code sections
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Also Published As

Publication number Publication date
US4763244A (en) 1988-08-09
JP2567594B2 (ja) 1996-12-25
US4800489A (en) 1989-01-24
EP0253824A1 (en) 1988-01-27
JPS63502224A (ja) 1988-08-25
DE3688978D1 (de) 1993-10-07
EP0253824B1 (en) 1993-09-01
KR940011668B1 (ko) 1994-12-23
DE3688978T2 (de) 1994-01-20
EP0253824A4 (en) 1990-03-21
WO1987004544A1 (en) 1987-07-30

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Legal Events

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A201 Request for examination
E902 Notification of reason for refusal
G160 Decision to publish patent application
E701 Decision to grant or registration of patent right
GRNT Written decision to grant
FPAY Annual fee payment

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Year of fee payment: 4

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