LU502411B1 - Oscillator based on leakage current delay unit - Google Patents

Oscillator based on leakage current delay unit Download PDF

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Publication number
LU502411B1
LU502411B1 LU502411A LU502411A LU502411B1 LU 502411 B1 LU502411 B1 LU 502411B1 LU 502411 A LU502411 A LU 502411A LU 502411 A LU502411 A LU 502411A LU 502411 B1 LU502411 B1 LU 502411B1
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LU
Luxembourg
Prior art keywords
transistor
leakage current
delay unit
current delay
phase inverter
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LU502411A
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German (de)
Inventor
Dingxin Li
Guohao Zhang
Sizhen Li
Kai Yu
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Synergy Innovation Inst Of Gdut Heyuan
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    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K3/00—Circuits for generating electric pulses; Monostable, bistable or multistable circuits
    • H03K3/02—Generators characterised by the type of circuit or by the means used for producing pulses
    • H03K3/027—Generators characterised by the type of circuit or by the means used for producing pulses by the use of logic circuits, with internal or external positive feedback
    • H03K3/03—Astable circuits
    • H03K3/0315—Ring oscillators
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K3/00—Circuits for generating electric pulses; Monostable, bistable or multistable circuits
    • H03K3/01—Details
    • H03K3/011—Modifications of generator to compensate for variations in physical values, e.g. voltage, temperature
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K3/00—Circuits for generating electric pulses; Monostable, bistable or multistable circuits
    • H03K3/01—Details
    • H03K3/017—Adjustment of width or dutycycle of pulses
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K3/00—Circuits for generating electric pulses; Monostable, bistable or multistable circuits
    • H03K3/02—Generators characterised by the type of circuit or by the means used for producing pulses
    • H03K3/027—Generators characterised by the type of circuit or by the means used for producing pulses by the use of logic circuits, with internal or external positive feedback
    • H03K3/03—Astable circuits
    • H03K3/0315—Ring oscillators
    • H03K3/0322—Ring oscillators with differential cells

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  • Logic Circuits (AREA)
  • Pulse Circuits (AREA)
  • Stabilization Of Oscillater, Synchronisation, Frequency Synthesizers (AREA)

Abstract

An oscillator based on a leakage current delay unit, including a leakage current delay unit, a phase inverter INV1, a phase inverter INV2, a phase inverter INV3, a phase inverter INV4, a transmission gate TG1 and a transmission gate TG2; The leakage current delay unit includes a leakage current delay unit LDU1 and a leakage current delay unit LDU2, which include in-phase input ends VIN, inverted input ends VINB, in-phase output ends VOUT and inverted output ends VOUTB; The in-phase input end VIN of the leakage current delay unit LDU1 and the inverted input end VINB of the leakage current delay unit LDU2 are respectively connected between the output end of the phase inverter INV3 and the input end of the phase inverter INV4.

Description

BL-5516
OSCILLATOR BASED ON LEAKAGE CURRENT DELAY UNIT LUS02411
TECHNICAL FIELD
[0001] The present disclosure relates to an oscillator in the field of intelligent Internet of Things, in particular to an oscillator based on a leakage current delay unit.
BACKGROUND ART
[0002] Internet of Things is “The Internet of Things”, and one form is based on an intelligent node to realize interconnection among any articles. The intelligent node is usually realized as a system on chip, which may adopt photovoltaic, piezoelectric, thermoelectric and radio frequency as energy source, and a charge pump energy harvester and a load are included in the system on chip.
[0003] The charge pump energy harvester is composed of a charge pump, an oscillator and other modules, the function of the charge pump is energy harvesting, and the function of the oscillator is to provide a clock signal to the charge pump and other modules. For the sake of efficient energy harvesting, the power consumption of the oscillator shall be reduced as far as possible. In addition, the duty cycle of the charge pump clock signal needs to be stabilized at 50%, and excessive deviation will reduce the input power of the charge pump. The load includes a sensor, a signal processor and a wireless transceiver, etc.
[0004] An existing literature (X. Liu and E. Sanchez-Sinencio. À switched capacitor energy harvester based on a single-cycle criterion for MPPT to eliminate storage capacitor [J]. IEEE Trans. Circuits Systems I, 2018, 69(2): 793-803) provides an oscillator based on a leakage current delay unit, and its circuit is as shown in FIG 1.
LDUI and LDU2 are leakage current delay units, VIN in the symbol is an in-phase input end, VINB is an inverted input end, VOUT is an in-phase output end, VOUTB is an inverted output end, INV1 and INV2 are phase inverters, and the left side of the symbol is an input end and the right side of the symbol is an output end. VINI is in-phase input voltage of LDU1, VINIB is inverted input voltage of LDU1, CLK is an in-phase clock signal and also used as an output clock signal of the oscillator in the existing literature, CLKB is an inverted clock signal, VOUT2 is in-phase output voltage of LDU2, and VOUT2B is inverted output voltage of LDU2. The leakage current delay unit circuit is as shown in FIG 2, NM1, NM2, NM3, NM4 and NM5 are N-channel field effect transistors, PM1, PM2 and PM3 are P-channel field effect transistors, and
VDD is a power end.
[0005] In the existing literature, when the oscillator works, LDU is divided into two states: reset and charge, and the working steps of the oscillator are as follows:
[0006] Step 1: when VINI and VINIB are changed to a high level and a low level,
LDUI1 enters the reset state, and CLKB and CLK are changed to the high level and low level;
[0007] Step 2: LDU2 enters the reset state, and VOUT2B and VOUT? are changed to the high level and low level;
[0008] Step 3: VINI and VINIB are changed to the low level and high level, and
LDUI1 enters the charge state; 1
BL-5516
[0009] Step 4: when PM3 gate-to-source voltage in LDU] is reduced until PM3 in LU502411
LDUI1 is opened, CLKB and CLK are changed to the low level and high level, and then
LDU2 enters the charge state;
[0010] Step 5: when PM3 gate-to-source voltage in LDU2 is reduced until PM3 in
LDU2 is opened, VOUT2B and VOUT?2 are changed to the low level and high level, and then the oscillator returns to the Step 1.
[0011] Since adopting the leakage current delay unit, the oscillator in the existing literature has the characteristic of low power consumption, however the reset state of
LDUI1 is momentary, LDU1 has the situation of incomplete reset, which results in hard control for the clock signal duty cycle during the front end design process of the oscillator. In addition, a source of PM3 in LDU is connected to the power end VDD, resulting in great influence of fluctuation of power and voltage on the duty cycle of the output clock signal.
SUMMARY
[0012] For the problems of hard control for the clock signal duty cycle during the front end design process of the oscillator and great influence of fluctuation of power and voltage on the duty cycle output clock signal, the technical problems solved by the present disclosure are how to eliminate the situation of incomplete reset of the leakage current delay unit, simplify the front end design of the oscillator and weaken the influence of fluctuation of power and voltage on the duty cycle of the output clock signal, to be stabilized at 50%.
[0013] In order to achieve the above purpose, the present disclosure provides an oscillator based on a leakage current delay unit, including a leakage current delay unit, a phase inverter INV1, a phase inverter INV2, a phase inverter INV3, a phase inverter
INV4, a transmission gate TG1 and a transmission gate TG2;
[0014] The leakage current delay unit includes a leakage current delay unit LDU1 and a leakage current delay unit LDU2, which include in-phase input ends VIN, inverted input ends VINB, in-phase output ends VOUT and inverted output ends VOUTB:;
[0015] The in-phase output end VOUT of the leakage current delay unit LDUI is connected with the input end of the phase inverter INV1, the output end of the phase inverter INV1 is connected to the input end of the transmission gate TG1, and the output end of the transmission gate TG1 is connected to the input end of the phase inverter
INV3. The output end of the phase inverter INV3 is connected to the input end of the phase inverter INV4; and the inverted output end VOUTB of the leakage current delay unit LDU2 is connected to the input end of the phase inverter INV2, the output end of the phase inverter INV2 is connected to the input end of the transmission gate TG2, and the output end of the transmission gate TG2 is connected to the input end of the phase inverter INV3;
[0016] The in-phase control end of the transmission gate TG1 and the inverted control end of the transmission gate TG2 are respectively connected to the output end of the phase inverter INV4, and the inverted control end of the transmission gate TG1 and the in-phase control end of transmission gate TG2 are respectively connected between the output end of the phase inverter INV3 and the input end of the phase inverter INV4. The 2
BL-5516 inverted input end VINB of the leakage current delay unit LDU1 and the in-phase input LU502411 end VIN of the leakage current delay unit LDU2 are respectively connected to the output end of the phase inverter INV4;
[0017] The in-phase input end VIN of the leakage current delay unit LDU1 and the inverted input end VINB of the leakage current delay unit LDU2 are respectively connected between the output end of the phase inverter INV3 and the input end of the phase inverter INV4, and voltage CLK is transmitted outwards by a wire between the output end of the phase inverter INV3 and the input end of the phase inverter INV4 to be used as an output clock signal of the oscillator.
[0018] Further, the circuit structure of the leakage current delay unit includes a transistor NM 1, a transistor NM2, a transistor NM3, a transistor PM1, a transistor PM2, a transistor PM3 and a transistor PM4;
[0019] A gate of the transistor PM3 is connected to a drain of the transistor NM3 to lead out the inverted output end VOUTB of the leakage current delay unit, and the gate of the transistor NM3 is connected to the drain of the transistor PM3 so as to lead out the in-phase output end VOUT of the leakage current delay unit;
[0020] The gate of the transistor PM1 leads out the inverted input end VINB of the leakage current delay unit, the source of the transistor PM1 is connected to the power end VDD, and the drain is connected to the inverted output end VOUTB,;
[0021] The gate of the transistor PM2 leads out the in-phase input end VIN of the leakage current delay unit, the source of the transistor PM2 is connected to the power end VDD, and the drain is connected to the source of the transistor PM3;
[0022] The gate of the transistor NM1 is connected to the in-phase input end VIN of the leakage current delay unit, the source of the transistor NMI is grounded, and the drain is connected to the in-phase output end VOUT. The gate of the transistor NM2 is connected to the inverted input end VINB, the source of the transistor NM2 is grounded, and the drain is connected to the source of the transistor NM3. The gate of the transistor
PM4 is connected to the power end VDD, the source of the transistor PM4 is connected to the source of the transistor PM3, and the drain is connected to the in-phase output end
VOUT.
[0023] Further, the transistor NMI, the transistor NM2 and the transistor NM3 are
N-channel field effect transistors.
[0024] Further, the transistor PMI, the transistor PM2, the transistor PM3 and transistor PM4 are P-channel field effect transistors.
[0025] After adopting the above structure, the present disclosure eliminates the situation of incomplete reset of the leakage current delay unit and simplifies the front end design of the oscillator. The working state of the leakage current delay unit is divided into reset and charge, so the influence of the power and voltage on the duty cycle is weakened, so that the duty cycle of the oscillator output signal may be stabilized at 50%.
BRIEF DESCRIPTION OF THE DRAWINGS
[0026] To better clarify the embodiment of the present disclosure or the technical solution in the prior art, the drawings required to illustrate the embodiments or the prior 3
BL-5516 art will be simply described below. It is apparent that the drawings described below LU502411 merely illustrate some embodiments of the present disclosure. Those ordinarily skilled in the art can obtain other drawings according to the structures of these drawings without creative labor on the basis of those drawings.
[0027] FIG 1 is a structural schematic diagram of a circuit of an oscillator in the prior art.
[0028] FIG 2 is a structural schematic diagram of a circuit of a leakage current delay unit in the prior art.
[0029] FIG 3 is a structural schematic diagram of a circuit of one embodiment of an oscillator in the present disclosure.
[0030] FIG 4 is a structural schematic diagram of a circuit of one embodiment of a leakage current delay unit in the present disclosure.
DETAILED DESCRIPTION OF THE EMBODIMENTS
[0031] The technical solutions in the embodiments of the present disclosure are clearly and completely elaborated below in combination with the drawings. It is apparent that the described embodiments are only a part of the embodiments of the present disclosure but not all. Based on the embodiments of the present disclosure, all the other embodiments obtained by those of ordinary skill in the art on the premise of not contributing creative effort should belong to the protection scope of the present disclosure.
[0032] In addition, if the descriptions “first” and “second” are involved in the embodiments of the present disclosure, the descriptions “first” and “second” are merely used for description, instead of being understood as indicating or implying relative importance or impliedly indicating the quantity of the showed technical features.
[0033] For the problems of hard control for the clock signal duty cycle during the front end design process of the oscillator and great influence of fluctuation of power and voltage on the duty cycle clock signal, the technical problems solved by the present disclosure are how to eliminate the situation of incomplete reset of the leakage current delay unit, simplify the front end design of the oscillator and weaken the influence of fluctuation of power and voltage on the duty cycle of the output clock signal, to be stabilized at 50%.
[0034] Specifically, as shown in FIG 3, the present disclosure provides an oscillator based on a leakage current delay unit, including a leakage current delay unit, a phase inverter INV, a phase inverter INV2, a phase inverter INV3, a phase inverter INV4, a transmission gate TG1 and a transmission gate TG2;
[0035] The leakage current delay unit includes a leakage current delay unit LDU1 and a leakage current delay unit LDU2, which include in-phase input ends VIN, inverted input ends VINB, in-phase output ends VOUT and inverted output ends VOUTB:;
[0036] The in-phase output end VOUT of the leakage current delay unit LDUI is connected with the input end of the phase inverter INV1, the output end of the phase inverter INV1 is connected to the input end of the transmission gate TG1, and the output end of the transmission gate TG1 is connected to the input end of the phase inverter
INV3. The output end of the phase inverter INV3 is connected to the input end of the 4
BL-5516 phase inverter INV4; and the inverted output end VOUTB of the leakage current delay LU502411 unit LDU2 is connected to the input end of the phase inverter INV2, the output end of the phase inverter INV2 is connected to the input end of the transmission gate TG2, and the output end of the transmission gate TG2 1s connected to the input end of the phase inverter INV3;
[0037] The in-phase control end of the transmission gate TG1 and the inverted control end of the transmission gate TG2 are respectively connected to the output end of the phase inverter INV4, and the inverted control end of the transmission gate TG1 and the in-phase control end of transmission gate TG2 are respectively connected between the output end of the phase inverter INV3 and the input end of the phase inverter INV4. The inverted input end VINB of the leakage current delay unit LDU1 and the in-phase input end VIN of the leakage current delay unit LDU2 are respectively connected to the output end of the phase inverter INV4;
[0038] The in-phase input end VIN of the leakage current delay unit LDU1 and the inverted input end VINB of the leakage current delay unit LDU2 are respectively connected between the output end of the phase inverter INV3 and the input end of the phase inverter INV4, and voltage CLK is transmitted outwards by a wire between the output end of the phase inverter INV3 and the input end of the phase inverter INV4 to be used as an output clock signal of the oscillator.
[0039] Further, the circuit structure of the leakage current delay unit includes a transistor NM 1, a transistor NM2, a transistor NM3, a transistor PM1, a transistor PM2, a transistor PM3 and a transistor PM4;
[0040] A gate of the transistor PM3 is connected to a drain of the transistor NM3 to lead out the inverted output end VOUTB of the leakage current delay unit, and the gate of the transistor NM3 is connected to the drain of the transistor PM3 so as to lead out the in-phase output end VOUT of the leakage current delay unit;
[0041] The gate of the transistor PM1 leads out the inverted input end VINB of the leakage current delay unit, the source of the transistor PM1 is connected to the power end VDD, and the drain is connected to the inverted output end VOUTB,;
[0042] The gate of the transistor PM2 leads out the in-phase input end VIN of the leakage current delay unit, the source of the transistor PM2 is connected to the power end VDD, and the drain is connected to the source of the transistor PM3;
[0043] The gate of the transistor NM1 is connected to the in-phase input end VIN of the leakage current delay unit, the source of the transistor NMI is grounded, and the drain is connected to the in-phase output end VOUT. The gate of the transistor NM2 is connected to the inverted input end VINB, the source of the transistor NM2 is grounded, and the drain is connected to the source of the transistor NM3. The gate of the transistor
PM4 is connected to the power end VDD, the source of the transistor PM4 is connected to the source of the transistor PM3, and the drain is connected to the in-phase output end
VOUT.
[0044] Preferably, the transistor NMI, the transistor NM2 and the transistor NM3 are
N-channel field effect transistors, and the transistor PMI, the transistor PM2, the transistor PM3 and the transistor PM4 P-channel field effect transistors.
[0045] When the oscillator provided by the present disclosure works, the leakage 5
BL-5516 current delay unit is divided into two states: reset and charge, and the working steps are LU502411 as follows:
[0046] Step 1: when CLK and CLKB are changed to the high level and low level, the leakage current delay unit LDU1 and the leakage current delay unit LDU2 enter the reset state and the charge state. VOUT] is changed to the low level, VOUT2B keeps the high level, the transmission gate TG1 is closed, the transmission gate TG2 is opened,
CLK and CLKB keep the high level and low level, wherein VOUTI1 is the in-phase output voltage of the leakage current delay unit LDU1, VOUT2B is the inverted output voltage of the leakage current delay unit LDU2, CLK is the in-phase clock signal and also the output clock signal of the oscillator provided by the present disclosure, and
CLKB is the inverted clock signal;
[0047] Step 2: when the gate-to-source voltage of the transistor NM3 of the leakage current delay unit LDU?2 rises until to open the transistor NM3 in the leakage current delay unit LDU2, VOUT2B is changed to the low level,
[0048] Step 3: CLK and CLKB are changed to the low level and high level, the leakage current delay unit LDU1 and the leakage current delay unit LDU2 enter the charge state and reset state, VOUT keeps the low level, VOUT2B is changed to the high level, the transmission gate TG1 is opened, the transmission gate TG2 is closed, and CLK and
CLKB keep the low level and high level,
[0049] Step 4: when the gate-to-source voltage of the transistor NM3 of the leakage current delay unit LDUI1 rises until to open the transistor NM3 in the leakage current delay unit LDU1, VOUT] is changed to the high level, and the oscillator provided by the present disclosure returns to Step 1.
[0050] After adopting the above structure, the present disclosure eliminates the situation of incomplete reset of the leakage current delay unit and simplifies the front end design of the oscillator. The working state of the leakage current delay unit is divided into reset and charge, so the influence of the power and voltage on the duty cycle of the output clock signal is weakened, to be stabilized at 50%.
[0051] The above is the preferred embodiment of the present disclosure, instead of limiting the patent scope of the present disclosure. Without departing from the concept of the present disclosure, the equal structural transformations made according to the contents of the specification and the drawings or direct/indirect application in other related technical fields fall within the scope of protection of the present disclosure. 6

Claims (4)

BL-5516 CLAIMS LU502411
1. An oscillator based on a leakage current delay unit, comprising a leakage current delay unit, a phase inverter INV1, a phase inverter INV2, a phase inverter INV3, a phase inverter INV4, a transmission gate TG1 and a transmission gate TG2; the leakage current delay unit comprises a leakage current delay unit LDU1 and a leakage current delay unit LDU2, each of the leakage current delay unit LDUI and leakage current delay unit LDU2 comprises an in-phase input end VIN, an inverted input end VINB, an in-phase output end VOUT and an inverted output end VOUTB; the in-phase output end VOUT of the leakage current delay unit LDUI is connected with the input end of the phase inverter INV1, the output end of the phase inverter INV1 is connected to the input end of the transmission gate TG1, and the output end of the transmission gate TG1 is connected to the input end of the phase inverter INV3; the output end of the phase inverter INV3 is connected to the input end of the phase inverter INV4; and the inverted output end VOUTB of the leakage current delay unit LDU2 is connected to the input end of the phase inverter INV2, the output end of the phase inverter INV2 is connected to the input end of the transmission gate TG2, and the output end of the transmission gate TG2 is connected to the input end of the phase inverter INV3; the in-phase control end of the transmission gate TG1 and the inverted control end of the transmission gate TG2 are respectively connected to the output end of the phase inverter INV4, and the inverted control end of the transmission gate TG1 and the in-phase control end of transmission gate TG2 are respectively connected between the output end of the phase inverter INV3 and the input end of the phase inverter INV4; the inverted input end VINB of the leakage current delay unit LDU1 and the in-phase input end VIN of the leakage current delay unit LDU2 are respectively connected to the output end of the phase inverter INV4; the in-phase input end VIN of the leakage current delay unit LDU1 and the inverted input end VINB of the leakage current delay unit LDU2 are respectively connected between the output end of the phase inverter INV3 and the input end of the phase inverter INV4, and voltage CLK is transmitted outwards by a wire between the output end of the phase inverter INV3 and the input end of the phase inverter INV4 to be used as an output clock signal of the oscillator.
2. The oscillator of claim 1, wherein the circuit structure of the leakage current delay unit comprises a transistor NM1, a transistor NM2, a transistor NM3, a transistor PM], a transistor PM2, a transistor PM3 and a transistor PM4; a gate of the transistor PM3 is connected to a drain of the transistor NM3 to lead out the inverted output end VOUTB of the leakage current delay unit, and the gate of the transistor NM3 is connected to the drain of the transistor PM3 so as to lead out the in-phase output end VOUT of the leakage current delay unit; the gate of the transistor PM1 leads out the inverted input end VINB of the leakage current delay unit, the source of the transistor PM1 is connected to the power end VDD, and the drain is connected to the inverted output end VOUTB; the gate of the transistor PM2 leads out the in-phase input end VIN of the leakage current delay unit, the source of the transistor PM2 is connected to the power end VDD, 7
BL-5516 and the drain is connected to the source of the transistor PM3; LUS02411 the gate of the transistor NMI is connected to the in-phase input end VIN of the leakage current delay unit, the source of the transistor NM1 is grounded, and the drain is connected to the in-phase output end VOUT; the gate of the transistor NM2 is connected to the inverted input end VINB, the source of the transistor NM2 is grounded, and the drain is connected to the source of the transistor NM3; the gate of the transistor PM4 1s connected to the power end VDD, the source of the transistor PM4 1s connected to the source of the transistor PM3, and the drain is connected to the in-phase output end VOUT.
3. The oscillator of claim 2, wherein the transistor NM1, the transistor NM2 and the transistor NM3 are N-channel field effect transistors.
4. The oscillator of claim 2 or 3, wherein the transistor PM1, the transistor PM2, the transistor PM3 and transistor PM4 are P-channel field effect transistors. 8
LU502411A 2022-01-09 2022-06-29 Oscillator based on leakage current delay unit LU502411B1 (en)

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CN113659963A (en) * 2021-08-24 2021-11-16 郝报田 Oscillator circuit

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RAMAKRISHNA S BALAJI ET AL: "Design and performance analysis of low frequency CMOS ring oscillator using 90nm technology", 2016 IEEE INTERNATIONAL CONFERENCE ON RECENT TRENDS IN ELECTRONICS, INFORMATION & COMMUNICATION TECHNOLOGY (RTEICT), IEEE, 20 May 2016 (2016-05-20), pages 1796 - 1801, XP033038232, DOI: 10.1109/RTEICT.2016.7808144 *
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