CN113659963A

CN113659963A - Oscillator circuit

Info

Publication number: CN113659963A
Application number: CN202110973086.6A
Authority: CN
Inventors: 郝报田
Original assignee: Individual
Current assignee: Individual
Priority date: 2021-08-24
Filing date: 2021-08-24
Publication date: 2021-11-16

Abstract

The invention discloses an oscillator circuit, which relates to the field of integrated circuit design, and comprises: the leakage compensation module is coupled with the reference current generation module and used for compensating the proportional leakage current in the reference current generation module; the reference current generating module is used for generating current inversely proportional to temperature and enhancing circuit precision at high temperature; compared with the prior art, the invention has the beneficial effects that: the invention provides the self-biasing technology, avoids the requirement of additional current source input, reduces the power consumption and saves the area and the cost; injecting the leakage current of the device into a reference current generating circuit, and enabling the delay of the delay unit to be related to the leakage current by adjusting the bias current of the delay unit, thereby solving the problem of high-temperature deviation of the clock frequency of the oscillator; the delay unit formed by the two-stage differential circuit is coupled to the reference current generating circuit, so that the power consumption is saved, and the duty ratio of an output clock is improved.

Description

Oscillator circuit

Technical Field

The invention relates to the field of integrated circuit design, in particular to an oscillator circuit.

Background

The oscillating current is a current whose magnitude and direction change with a period, and a circuit capable of generating the oscillating current is called an oscillating circuit. The oscillator circuit is used as a chip clock source and provides a reference clock for a chip part or a global digital and analog circuit, and the duty ratio, the frequency precision and the power consumption of the oscillator output clock are important indexes.

The current oscillator circuit technology has the following disadvantages: (1): influenced by the leakage current of the device, the frequency deviation is more at high temperature, and the precision is not ideal; (2): a bias current or an additional independent bias current generating circuit is needed, so that low power consumption is difficult to achieve; (3): by adopting the single-ended input and output ring oscillator, the duty ratio of an output clock is not ideal and needs to be improved.

Disclosure of Invention

It is an object of the present invention to provide an oscillator circuit to solve the above problems in the prior art.

In order to achieve the purpose, the invention provides the following technical scheme:

an oscillator circuit, comprising:

the leakage compensation module is coupled with the reference current generation module and used for compensating the proportional leakage current in the reference current generation module;

the reference current generating module is used for generating current inversely proportional to temperature and enhancing circuit precision at high temperature;

the first time delay module is coupled with the reference current generation module to form current multiplexing, differential input voltage signals and differential output after time delay;

the second time delay module is coupled with the reference current generation module to form current multiplexing, differential input voltage signals and differential output after time delay;

the first delay module and the second delay module jointly form a delay unit, and the delay unit at least comprises two delay modules which jointly form a ring oscillator;

the leakage compensation module is connected with the reference current generation module, and the reference current generation module is connected with the delay unit.

As a still further scheme of the invention: the leakage compensation module comprises a MOS tube PM5B, a MOS tube PM5A, a MOS tube PM6B, a MOS tube PM6A, a MOS tube PM1C, a MOS tube NM4B and a MOS tube NM4A, wherein the S pole of the MOS tube PM5B is connected with the S pole of the MOS tube PM5A, the S pole of the MOS tube PM1C, the G pole of the MOS tube PM1C and the voltage VDD, the G pole of the MOS tube PM5B is connected with the D pole of the MOS tube PM5B and the S pole of the MOS tube PM6B, the D pole of the MOS tube PM5A is connected with the S pole of the MOS tube PM6A, the G pole of the MOS tube PM6A is connected with the G pole of the MOS tube PM6B, the D pole of the MOS tube PM6B and the D pole of the MOS tube NM4 NM 9, and the G pole of the MOS tube NM4 NM B is connected with the G pole of the MOS tube NM A, the D pole of the MOS tube NM4 NM 53 and the D pole of the MOS tube NM C.

As a still further scheme of the invention: the reference current generation module comprises a MOS tube PM1A, a MOS tube PM1B, a MOS tube NM1A, a MOS tube PM0, a resistor R0 and a MOS tube NM1B, wherein the S pole of the MOS tube PM1A is connected with the S pole of the MOS tube PM1B and the voltage VDD, the G pole of the MOS tube PM1A is connected with the G pole of the MOS tube PM1B, the G pole of the MOS tube PM1C, the D pole of the MOS tube PM1B and the D pole of the MOS tube NM1B, the D pole of the MOS tube PM1A is connected with the D pole of the MOS tube NM1A, the G pole of the MOS tube NM1A, the D pole of the MOS tube PM6A and the G pole of the MOS tube NM1B, the S pole of the MOS tube NM1A is connected with the S pole of the MOS tube NM1B, the S pole of the resistor R0 is connected with the other end of the resistor R0, and the other end of the resistor R0 is grounded.

As a still further scheme of the invention: the first time delay module comprises an amplifier U1, a MOS tube NM2A and a MOS tube NM2B, wherein the fourth end of the amplifier U1 is connected with the D pole of the MOS tube NM2A, the third end of the amplifier U1 is connected with the D pole of the MOS tube NM2B, the S pole of the MOS tube NM2A is connected with the S pole of the MOS tube NM2B, and the G pole of the MOS tube NM2A is connected with the G pole of the MOS tube NM 2B.

As a still further scheme of the invention: the second time delay module comprises an amplifier U2, a MOS tube NM3A and a MOS tube NM3B, wherein the fourth end of the amplifier U2 is connected with the D pole of the MOS tube NM3A and the first end of the amplifier U1, the third end of the amplifier U2 is connected with the D pole of the MOS tube NM3B and the second end of the amplifier U1, the S pole of the MOS tube NM3A is connected with the S pole of the MOS tube NM3B, the G pole of the MOS tube NM3A is connected with the G pole of the MOS tube NM3B, the first end of the amplifier U2 is connected with the third end of the amplifier U1, and the second end of the amplifier U2 is connected with the fourth end of the amplifier U1.

As a still further scheme of the invention: amplifier U1 includes MOS transistor PM3A, MOS transistor PM3B, MOS transistor PM3D, MOS transistor PM4C, MOS transistor PM4B, MOS transistor PM4A, MOS transistor PM3C, and MOS transistor PM4D, the S-pole of MOS transistor PM3A is connected to the S-pole of MOS transistor PM3A, the S-pole of MOS transistor PM4A, and voltage VDD, the D-pole of MOS transistor PM3A is connected to the G-pole of MOS transistor PM3A, the D-pole of MOS transistor PM3A, the G-pole of MOS transistor PM4A, the D-pole of MOS transistor PM3A is connected to the S-pole of MOS transistor PM3A, the D-pole of MOS transistor PM3A is connected to the D-pole of MOS transistor PM4, the D-pole of MOS transistor PM4 PM3A, the D-pole of MOS transistor PM4, the D-pole of MOS transistor PM3A, the MOS transistor PM 4G-pole of MOS transistor PM A, the MOS transistor PM 4G, and the voltage VDD, and the MOS transistor PM 4D-pole of MOS transistor PM3A is connected to the MOS transistor PM A.

Compared with the prior art, the invention has the beneficial effects that: the invention provides the self-biasing technology, avoids the requirement of additional current source input, reduces the power consumption and saves the area and the cost; injecting the leakage current of the device into a reference current generating circuit, and enabling the delay of the delay unit to be related to the leakage current by adjusting the bias current of the delay unit, thereby solving the problem of high-temperature deviation of the clock frequency of the oscillator; the delay unit formed by the two-stage differential circuit is coupled to the reference current generating circuit, so that the power consumption is saved, and the duty ratio of an output clock is improved.

Drawings

Fig. 1 is a circuit diagram of an oscillator circuit.

Fig. 2 is an internal circuit diagram of the first delay module.

Fig. 3 is a waveform diagram of the internal operation of the oscillator circuit.

Detailed Description

The technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the drawings in the embodiments of the present invention, and it is obvious that the described embodiments are only a part of the embodiments of the present invention, and not all embodiments, and all other embodiments obtained by a person of ordinary skill in the art without creative efforts based on the embodiments of the present invention belong to the protection scope of the present invention.

Example 1: referring to fig. 1, an oscillator circuit includes:

the first delay module and the second delay module jointly form a delay unit, the delay unit at least comprises two delay modules, and the delay modules are connected with each other to form a ring oscillator;

In a specific embodiment: the reference current generation module forms a bias current inversely proportional to the temperature on a resistor R0, the magnitude of the bias current is vgs _ mir/R0, and the vgs _ mir is the S-pole output voltage of the MOS transistor NM 1B; because MOS transistors PM1A and PM1B are equal in size (or proportional), MOS transistors NM1A and NM1B are equal in size (or proportional), vgs _ mir = vgs _ src, and vgs _ src is the S-pole output voltage of MOS transistor NM1A, so that the current flowing through the circuit is vgs _ mir/R0= vgs _ src/R0;

because MOS transistors NM1A, NM1B, NM2A, NM2B, NM3A, NM3B are equal in size (or proportional, and equal is assumed here), and resistance current vgs _ src/R0 is the sum of the currents of MOS transistors NM1B, NM2A, NM2B, NM3A, NM3B, the currents flowing through NM2A/NM2B/NM3A/NM3B are equal and vgs _ src/R0/5;

the first delay module is differential input and differential output; due to the connection mode of the MOS transistors PM3B and PM3C and the MOS transistors PM4B and PM4D, the signal of the output OUTP/OUTN point is VDD at the highest and VDD-vgs4A at the lowest, namely, the amplitude is vgs4A

Assuming that the output terminal OUTP is lowered from VDD to VDD-vgs4A, the current provided by the MOS transistor NM2B needs to discharge the parasitic capacitance (Cp) of the OUTP node for a time T1, where Cp × vgs4A = (vgs _ src/R0/5) = T1, and since vgs4A is approximately equal to vgs _ src, T1=5 × R0 Cp; the parasitic capacitance Cp is composed of the parasitic capacitances of the transistors in fig. 2, which are not shown. Parasitic capacitance Cp, such as the OUTN terminal, is composed of the D-pole of PM3A, the G-pole of PM3B/C/D, and the G-pole parasitic capacitance of PM 4C.

The first delay module and the second delay module are cross-coupled together to form a ring oscillator, and the types of components of the first delay module and the second delay module are the same;

the total delay Tp =2 × T1=10 × R0 × Cp of the ring oscillator; the frequency f =1/Tp =1/(10 × R0 × Cp) of the ring oscillator;

assuming that resistor R0 and parasitic capacitance Cp are temperature independent, the final output clock frequency is also temperature independent;

in practical situations, because the G poles and the D poles of MOS transistors PM3A, PM3B, PM3C, PM3D and MOS transistors PM4, PM4, PM4, PM4D have leakage currents (the leakage currents are more significant at high temperatures), the discharge currents of the delay cells are not completely determined by MOS transistors NM2A and NM2B, so that a frequency error is introduced;

by coupling the leakage compensation module to the reference current generation module, the MOS transistors NM2A, NM2B, NM3A, and NM3B include proportional leakage currents for compensation, so that the discharge current of the delay unit is more ideal, and the clock output frequency is more ideal.

In this embodiment: referring to fig. 1, the leakage compensation module includes a MOS transistor PM5B, a MOS transistor PM5A, a MOS transistor PM6B, a MOS transistor PM6A, a MOS transistor PM1C, a MOS transistor NM4B, and a MOS transistor NM4A, wherein an S-pole of the MOS transistor PM5B is connected to an S-pole of the MOS transistor PM5A, an S-pole of the MOS transistor PM1C, a G-pole of the MOS transistor PM1C, and a voltage VDD, a G-pole of the MOS transistor PM5B is connected to a D-pole of the MOS transistor PM5B and an S-pole of the MOS transistor PM6B, a D-pole of the MOS transistor PM5A is connected to an S-pole of the MOS transistor PM6A, a G-pole of the MOS transistor PM6A is connected to a G-pole of the MOS transistor PM6B, a D-pole of the MOS transistor PM6B, a D-pole of the MOS transistor NM4B, and a G-pole of the MOS transistor NM4B is connected to a G-pole of the MOS transistor NM4A, a G-pole of the MOS transistor NM4 NM 53, a D-pole of the MOS transistor NM 4C, and a D C.

In this embodiment: referring to fig. 1, the reference current generating module includes a MOS transistor PM1A, a MOS transistor PM1B, a MOS transistor NM1A, a MOS transistor PM0, a resistor R0, and a MOS transistor NM1B, wherein an S-pole of the MOS transistor PM1A is connected to an S-pole of the MOS transistor PM1B and a voltage VDD, a G-pole of the MOS transistor PM1A is connected to a G-pole of the MOS transistor PM1B, a G-pole of the MOS transistor PM1C, a D-pole of the MOS transistor PM1B, and a D-pole of the MOS transistor NM1B, a D-pole of the MOS transistor PM1A is connected to a D-pole of the MOS transistor NM1A, a G-pole of the MOS transistor NM1A, a D-pole of the MOS transistor PM6A, and a G-pole of the MOS transistor NM1B, an S-pole of the MOS transistor NM1A is connected to an S-pole of the PMD transistor, an S-pole of the MOS transistor 5391 1B is connected to the R0, and the other end of the resistor NM 0 is grounded.

In this embodiment: referring to fig. 1 and 2, the first delay module includes an amplifier U1, a MOS transistor NM2A, and a MOS transistor NM2B, a fourth terminal of the amplifier U1 is connected to a D-pole of the MOS transistor NM2A, a third terminal of the amplifier U1 is connected to a D-pole of the MOS transistor NM2B, an S-pole of the MOS transistor NM2A is connected to an S-pole of the MOS transistor NM2B, and a G-pole of the MOS transistor NM2A is connected to a G-pole of the MOS transistor NM 2B.

In this embodiment: referring to fig. 1 and 2, the second delay module includes an amplifier U2, a MOS transistor NM3A, and a MOS transistor NM3B, a fourth terminal of the amplifier U2 is connected to a D-pole of the MOS transistor NM3A and a first terminal of the amplifier U1, a third terminal of the amplifier U2 is connected to a D-pole of the MOS transistor NM3B and a second terminal of the amplifier U1, an S-pole of the MOS transistor NM3A is connected to an S-pole of the MOS transistor NM3B, a G-pole of the MOS transistor NM3A is connected to a G-pole of the MOS transistor NM3B, a first terminal of the amplifier U2 is connected to a third terminal of the amplifier U1, and a second terminal of the amplifier U2 is connected to a fourth terminal of the amplifier U1.

In this embodiment: referring to fig. 2, amplifier U1 includes MOS transistor PM3A, MOS transistor PM3B, MOS transistor PM3D, MOS transistor PM4C, MOS transistor PM4B, MOS transistor PM4A, MOS transistor PM3C, and MOS transistor PM4D, the S-pole of MOS transistor PM3A is connected to the S-pole of MOS transistor PM3A, the S-pole of MOS transistor PM4A, and voltage VDD, the D-pole of MOS transistor PM3A is connected to the G-pole of MOS transistor PM3A, the D-pole of MOS transistor PM3A, the G-pole of MOS transistor PM4A, the D-pole of MOS transistor PM3A is connected to the S-pole of MOS transistor PM3A, the G-pole of MOS transistor PM3A is connected to the D-pole of MOS transistor PM3, the D-pole of MOS transistor PM4, the D-pole of MOS transistor PM3A, the G-pole of MOS transistor PM4, the MOS transistor A, the MOS transistor PM 4D-pole of MOS transistor A, and the MOS transistor PM 4D-pole of MOS transistor A are connected to the MOS transistor A, and the MOS transistor PM 4.

The working principle of the invention is as follows: the leakage compensation module is coupled with the reference current generation module and compensates the proportional leakage current in the reference current generation module; the reference current generation module generates current in inverse proportion to temperature and enhances circuit precision at high temperature; the first delay module and the second delay module jointly form a delay unit, and the first delay module and the second delay module are connected with each other to form a ring oscillator; thereby outputting a clock signal.

It will be evident to those skilled in the art that the invention is not limited to the details of the foregoing illustrative embodiments, and that the present invention may be embodied in other specific forms without departing from the spirit or essential attributes thereof. The present embodiments are therefore to be considered in all respects as illustrative and not restrictive, the scope of the invention being indicated by the appended claims rather than by the foregoing description, and all changes which come within the meaning and range of equivalency of the claims are therefore intended to be embraced therein. Any reference sign in a claim should not be construed as limiting the claim concerned.

Furthermore, it should be understood that although the present description refers to embodiments, not every embodiment may contain only a single embodiment, and such description is for clarity only, and those skilled in the art should integrate the description, and the embodiments may be combined as appropriate to form other embodiments understood by those skilled in the art.

Claims

1. An oscillator circuit, characterized in that:

the oscillator circuit includes:

2. The oscillator circuit according to claim 1, wherein the leakage compensation module includes a MOS transistor PM5B, a MOS transistor PM5A, a MOS transistor PM6B, a MOS transistor PM6A, a MOS transistor PM1C, a MOS transistor NM4B, and a MOS transistor NM4A, wherein an S-pole of the MOS transistor PM5B is connected to an S-pole of the MOS transistor PM5A, an S-pole of the MOS transistor PM1C, a G-pole of the MOS transistor PM1C, and a voltage VDD, a G-pole of the MOS transistor PM5B is connected to a D-pole of the MOS transistor PM5B and an S-pole of the MOS transistor PM6B, a D-pole of the MOS transistor PM5A is connected to an S-pole of the MOS transistor PM6A, a G-pole of the MOS transistor PM6A is connected to a G-pole of the MOS transistor PM6B, a D-pole of the MOS transistor PM6B, a D-pole of the MOS transistor PM4B, and a G-pole of the MOS transistor NM4 NM B is connected to an NM-pole of the MOS transistor NM4 NM 56, a G-pole of the MOS transistor PM4, a D-pole 828653 and a D-pole of the MOS transistor NM 4C.

3. The oscillator circuit according to claim 1, wherein the reference current generating module includes a MOS transistor PM1A, a MOS transistor PM1B, a MOS transistor NM1A, a MOS transistor PM0, a resistor R0, and a MOS transistor NM1B, an S pole of the MOS transistor PM1A is connected to an S pole of the MOS transistor PM1B and a voltage VDD, a G pole of the MOS transistor PM1A is connected to a G pole of the MOS transistor PM1B, a G pole of the MOS transistor PM1C, a D pole of the MOS transistor PM1B, and a D pole of the MOS transistor NM1B, a D pole of the MOS transistor PM1 6329 is connected to a D pole of the MOS transistor NM1A, a G pole of the MOS transistor NM1A, a D pole of the MOS transistor PM6A, and a G pole of the MOS transistor NM1B, an S pole of the MOS transistor NM1A is connected to an S pole of the MOS transistor NM1A, an S pole of the MOS transistor NM1 585 is connected to the other end of the resistor NM 0, and the resistor R0 is grounded.

4. The oscillator circuit of claim 1, wherein the first delay module comprises an amplifier U1, a MOS transistor NM2A and a MOS transistor NM2B, a fourth terminal of the amplifier U1 is connected to a D-pole of the MOS transistor NM2A, a third terminal of the amplifier U1 is connected to a D-pole of the MOS transistor NM2B, an S-pole of the MOS transistor NM2A is connected to an S-pole of the MOS transistor NM2B, and a G-pole of the MOS transistor NM2A is connected to a G-pole of the MOS transistor NM 2B.

5. The oscillator circuit of claim 1, wherein the second delay module comprises an amplifier U2, a MOS transistor NM3A and a MOS transistor NM3B, a fourth terminal of the amplifier U2 is connected to a D-pole of the MOS transistor NM3A and a first terminal of the amplifier U1, a third terminal of the amplifier U2 is connected to a D-pole of the MOS transistor NM3B and a second terminal of the amplifier U1, an S-pole of the MOS transistor NM3A is connected to an S-pole of the MOS transistor NM3B, a G-pole of the MOS transistor NM3A is connected to a G-pole of the MOS transistor NM3B, a first terminal of the amplifier U2 is connected to a third terminal of the amplifier U1, and a second terminal of the amplifier U2 is connected to a fourth terminal of the amplifier U1.

6. The oscillator circuit according to claim 4, wherein amplifier U1 includes MOS transistor PM3A, MOS transistor PM3B, MOS transistor PM3D, MOS transistor PM4C, MOS transistor PM4B, MOS transistor PM4A, MOS transistor PM3C, and MOS transistor PM4D, the S-pole of MOS transistor PM3A is connected to the S-pole of MOS transistor PM3A, the S-pole of MOS transistor PM4A, and voltage VDD, the D-pole of MOS transistor PM3A is connected to the G-pole of MOS transistor PM3A, the D-pole of MOS transistor PM3A, the G-pole of MOS transistor PM4A, the D-pole of MOS transistor PM3 PM A is connected to the S-pole of MOS transistor PM3A, the G-pole of MOS transistor PM 3G A, the G-pole of MOS transistor PM3, the MOS transistor PM 4G-pole A is connected to the S-pole of MOS transistor PM3, the MOS transistor PM 4G-pole A, the MOS transistor PM-pole of MOS transistor A, the MOS transistor PM 4G-pole of MOS transistor A is connected to the MOS transistor A, the MOS transistor PM 4G-pole of MOS transistor A, the MOS transistor PM-pole of MOS transistor A, and the MOS transistor PM-pole of the MOS transistor A is connected to the MOS transistor A.