CN115113682B - Input reference voltage adjusting circuit - Google Patents
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- CN115113682B CN115113682B CN202210886190.6A CN202210886190A CN115113682B CN 115113682 B CN115113682 B CN 115113682B CN 202210886190 A CN202210886190 A CN 202210886190A CN 115113682 B CN115113682 B CN 115113682B
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- G—PHYSICS
- G05—CONTROLLING; REGULATING
- G05F—SYSTEMS FOR REGULATING ELECTRIC OR MAGNETIC VARIABLES
- G05F3/00—Non-retroactive systems for regulating electric variables by using an uncontrolled element, or an uncontrolled combination of elements, such element or such combination having self-regulating properties
- G05F3/02—Regulating voltage or current
- G05F3/08—Regulating voltage or current wherein the variable is dc
- G05F3/10—Regulating voltage or current wherein the variable is dc using uncontrolled devices with non-linear characteristics
- G05F3/16—Regulating voltage or current wherein the variable is dc using uncontrolled devices with non-linear characteristics being semiconductor devices
- G05F3/20—Regulating voltage or current wherein the variable is dc using uncontrolled devices with non-linear characteristics being semiconductor devices using diode- transistor combinations
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Abstract
The embodiment of the disclosure provides an input reference voltage adjusting circuit, and belongs to the technical field of integrated circuits. The input reference voltage adjustment circuit includes: the current control circuit, the current mirror circuit, the bias circuit and the differential pair tube. The current control circuit generates a first current signal and provides the first current signal to the current mirror circuit and the bias circuit through the first node; the current mirror circuit generates a first image signal of the first current signal and provides the first image signal to the source voltage of the differential pair of tubes via the second node; the bias circuit generates a second image signal of the first current signal and provides bias voltage to the differential pair of tubes through a third node based on the second image signal; the differential pair transistor reduces disturbance of the first mirror signal to the amplitude of the input reference voltage according to the coupling action of the bias voltage and the source voltage on the input reference voltage at the same time, and the transient change of the bias voltage is opposite to the transient change of the source voltage.
Description
Technical Field
Embodiments of the present disclosure relate to the field of integrated circuit technology, and in particular, to an input reference voltage adjustment circuit.
Background
The DC-DC switching power supply is an important component widely applied in the field of power supply management, and can be applied to the fields of mobile phones, mobile power supplies, network communication, automobile electronics, consumer electronics and the like. With the rapid development of power management technology, the requirements on indexes such as efficiency, transient response speed, load adjustment rate, linear adjustment rate and the like of a DC-DC switching power supply are higher and higher, and when the DC-DC switching power supply enters a current-saving mode, transient disturbance of input reference voltage of a differential pair transistor in the DC-DC switching power supply is easily caused due to transient reduction of tail current, so that misoperation of an output signal is caused, the misoperation is transmitted to the next stage of the differential pair transistor, and error response of the DC-DC switching power supply is caused.
Disclosure of Invention
An object of an embodiment of the present disclosure is to provide an input reference voltage adjusting circuit, which increases the stability of a circuit by adding a bias circuit to a differential pair tube and reducing the disturbance amplitude of the input reference voltage by using the potential output by the bias circuit when the tail current changes.
To achieve the above object, a first aspect of the embodiments of the present disclosure provides an input reference voltage adjusting circuit, including: the current control circuit, the current mirror circuit, the bias circuit and the differential pair tube. Wherein the current control circuit is configured to generate a first current signal and provide the first current signal to the current mirror circuit, the bias circuit via a first node; the current mirror circuit is configured to generate a first image signal of the first current signal and provide the first image signal to a source voltage of the differential pair of tubes via a second node; the bias circuit is configured to generate a second image signal of the first current signal and provide a bias voltage to the differential pair of tubes via a third node based on the second image signal; the differential pair of transistors is configured to reduce a disturbance of the first mirror signal to the magnitude of the input reference voltage based on a coupling of the bias voltage and the source voltage to the input reference voltage simultaneously, a transient change in the bias voltage being of opposite polarity to a transient change in the source voltage.
In some embodiments of the present disclosure, the current control circuit includes: a first transistor, a second transistor, a third transistor, and a first current source. Wherein a first pole of the first transistor is coupled to a first voltage terminal, a second pole of the first transistor is coupled to a first pole of the second transistor, and a control pole of the first transistor is coupled to a second pole of the second transistor and a second pole of the third transistor; the control electrode of the second transistor is coupled with the level control end; a first electrode of the third transistor is coupled to the first voltage terminal, a second electrode of the third transistor is coupled to a control electrode of the third transistor, and a control electrode of the third transistor is coupled to the first node; the first end of the first current source is coupled to the second pole of the third transistor, and the second end of the first current source is coupled to the second voltage end.
In some embodiments of the present disclosure, the differential pair tube includes: an eighth transistor and a ninth transistor. The control electrode of the eighth transistor is coupled to the input reference voltage end, the substrate of the eighth transistor is coupled to the third node, the first electrode of the eighth transistor is coupled to the second node, and the second electrode of the eighth transistor is coupled to the first output end; the control electrode of the ninth transistor is coupled to the feedback voltage terminal, the substrate of the ninth transistor is coupled to the third node, the first electrode of the ninth transistor is coupled to the second node, and the second electrode of the ninth transistor is coupled to the second output terminal.
In some embodiments of the present disclosure, when the eighth transistor and the ninth transistor are both PMOS transistors, the current mirror circuit includes: and a fifth transistor. The control electrode of the fifth transistor is coupled to the first node, the first electrode of the fifth transistor is coupled to the first voltage terminal, and the second electrode of the fifth transistor is coupled to the second node.
In some embodiments of the present disclosure, when the eighth transistor and the ninth transistor are both PMOS transistors, the bias circuit includes: a fourth transistor, a sixth transistor, a seventh transistor, and a first resistor. The control electrode of the fourth transistor is coupled to the first node, the first electrode of the fourth transistor is coupled to the first voltage terminal, and the second electrode of the fourth transistor is coupled to the first electrode of the sixth transistor; the control electrode of the sixth transistor is coupled with the first electrode of the sixth transistor and the control electrode of the seventh transistor, and the second electrode of the sixth transistor is coupled with the second voltage end; a first pole of the seventh transistor is coupled to the third node, and a second pole of the seventh transistor is coupled to the second voltage terminal; the first end of the first resistor is coupled to a first voltage end, and the second end of the first resistor is coupled to the third node.
In some embodiments of the present disclosure, when the eighth transistor and the ninth transistor are both NMOS transistors, the current mirror circuit includes: a tenth transistor, an eleventh transistor, and a twelfth transistor, wherein a control electrode of the tenth transistor is coupled to the first node, a first electrode of the tenth transistor is coupled to a first voltage terminal, and a second electrode of the tenth transistor is coupled to the first electrode of the eleventh transistor; a control electrode of the eleventh transistor is coupled to the first electrode of the eleventh transistor and the control electrode of the twelfth transistor, and a second electrode of the eleventh transistor is coupled to the second voltage terminal; the first pole of the twelfth transistor is coupled to the second node, and the second pole of the twelfth transistor is coupled to the second voltage terminal. In some embodiments of the present disclosure, when the eighth transistor and the ninth transistor are both NMOS transistors, the bias circuit includes: a thirteenth transistor and a second resistor, wherein a control electrode of the thirteenth transistor is coupled to the first node, a first electrode of the thirteenth transistor is coupled to a first voltage terminal, and a second electrode of the thirteenth transistor is coupled to the third node; the first end of the second resistor is coupled to the third node, and the second end of the second resistor is coupled to a second voltage end.
In some embodiments of the present disclosure, when the control electrode of the second transistor receives the high level signal input from the level control terminal, the second transistor is turned off, and the first current signal flowing through the third transistor is a preset current signal generated by the first current source; when the control electrode of the second transistor receives the low-level signal input by the level control end, the second transistor is conducted, and the first current signal flowing through the third transistor is a shunt current signal generated by the first current source, wherein the preset current signal is larger than the shunt current signal.
In some embodiments of the present disclosure, when the eighth transistor and the ninth transistor are PMOS transistors, and the control electrode of the second transistor receives the change of the input signal of the level control terminal from the high level signal to the low level signal, the first current signal is changed from the preset current signal to the shunt current signal, the source voltage is transiently reduced, and the bias voltage is transiently increased; or when the control electrode of the second transistor receives that the input signal of the level control end is changed from the low level signal to the high level signal, the first current signal is changed from the shunt current signal to the preset current signal, the source voltage is increased in a transient state, and the bias voltage is reduced in a transient state.
In some embodiments of the present disclosure, when the eighth transistor and the ninth transistor are NMOS transistors, and the control electrode of the second transistor receives the change of the input signal of the level control terminal from the high level signal to the low level signal, the first current signal is changed from the preset current signal to the shunt current signal, the source voltage is increased transiently, and the bias voltage is decreased transiently; or when the control electrode of the second transistor receives that the input signal of the level control end is changed from the low level signal to the high level signal, the first current signal is changed from the shunt current signal to the preset current signal, the source voltage is reduced in a transient state, and the bias voltage is increased in a transient state.
A second aspect of an embodiment of the present disclosure provides an input reference voltage adjustment circuit, comprising: first to ninth transistors, a first current source, and a first resistor. The first electrode of the first transistor is coupled with the first voltage end, the second electrode of the first transistor is coupled with the first electrode of the second transistor, and the control electrode of the first transistor is coupled with the second electrode of the second transistor; the control electrode of the second transistor is coupled with the level control end; the control electrode of the third transistor is coupled to the first node, the first electrode of the third transistor is coupled to the first voltage terminal, and the second electrode of the third transistor is coupled to the second electrode of the second transistor; a first end of the first current source is coupled with a second pole of the second transistor, and a second end of the first current source is coupled with a second voltage end; the control electrode of the fourth transistor is coupled to the first node, the first electrode of the fourth transistor is coupled to the first voltage terminal, and the second electrode of the fourth transistor is coupled to the first electrode of the sixth transistor; the control electrode of the fifth transistor is coupled to the first node, the first electrode of the fifth transistor is coupled to the first voltage terminal, and the second electrode of the fifth transistor is coupled to the second node; the control electrode of the sixth transistor is coupled with the first electrode of the sixth transistor and the control electrode of the seventh transistor, and the second electrode of the sixth transistor is coupled with the second voltage end; a first pole of the seventh transistor is coupled to the third node, and a second pole of the seventh transistor is coupled to the second voltage terminal; a first end of the first resistor is coupled to a first voltage end, and a second end of the first resistor is coupled to the third node; the control electrode of the eighth transistor is coupled to the input reference voltage end, the substrate of the eighth transistor is coupled to the third node, the first electrode of the eighth transistor is coupled to the second node, and the second electrode of the eighth transistor is coupled to the first output end; the control electrode of the ninth transistor is coupled to the feedback voltage terminal, the substrate of the ninth transistor is coupled to the third node, the first electrode of the ninth transistor is coupled to the second node, and the second electrode of the ninth transistor is coupled to the second output terminal.
A third aspect of the disclosed embodiments provides an input reference voltage adjustment circuit comprising: first to third transistors, eighth to thirteenth transistors, a first current source, and a second resistor. The first electrode of the first transistor is coupled with the first voltage end, the second electrode of the first transistor is coupled with the first electrode of the second transistor, and the control electrode of the first transistor is coupled with the second electrode of the second transistor; the control electrode of the second transistor is coupled with the level control end; the control electrode of the third transistor is coupled to the first node, the first electrode of the third transistor is coupled to the first voltage terminal, and the second electrode of the third transistor is coupled to the second electrode of the second transistor; a first end of the first current source is coupled with a second pole of the second transistor, and a second end of the first current source is coupled with a second voltage end; the control electrode of the eighth transistor is coupled to the input reference voltage end, the substrate of the eighth transistor is coupled to the third node, the first electrode of the eighth transistor is coupled to the second node, and the second electrode of the eighth transistor is coupled to the first output end; the control electrode of the ninth transistor is coupled to the feedback voltage terminal, the substrate of the ninth transistor is coupled to the third node, the first electrode of the ninth transistor is coupled to the second node, and the second electrode of the ninth transistor is coupled to the second output terminal; the control electrode of the tenth transistor is coupled to the first node, the first electrode of the tenth transistor is coupled to the first voltage terminal, and the second electrode of the tenth transistor is coupled to the first electrode of the eleventh transistor; a control electrode of the eleventh transistor is coupled to the first electrode of the eleventh transistor and the control electrode of the twelfth transistor, and a second electrode of the eleventh transistor is coupled to the second voltage terminal; a first pole of the twelfth transistor is coupled to the second node, and a second pole of the twelfth transistor is coupled to the second voltage terminal; a control electrode of the thirteenth transistor is coupled to the first node, a first electrode of the thirteenth transistor is coupled to a first voltage terminal, and a second electrode of the thirteenth transistor is coupled to the third node; the first end of the second resistor is coupled to the third node, and the second end of the second resistor is coupled to a second voltage end.
According to the technical scheme, the bias circuit is added on the differential pair tube, so that the disturbance amplitude of the coupled input reference voltage is reduced by utilizing the reverse transient change of the bias voltage and the source voltage, and the stability of the circuit is improved.
Additional features and advantages of embodiments of the present disclosure will be set forth in the detailed description which follows.
Drawings
The accompanying drawings are included to provide a further understanding of embodiments of the disclosure and are incorporated in and constitute a part of this specification, illustrate embodiments of the disclosure and together with the description serve to explain, without limitation, the embodiments of the disclosure. In the drawings:
FIG. 1 is an exemplary circuit diagram of a differential pair circuit;
FIG. 2 is a schematic block diagram of an input reference voltage adjustment circuit according to an embodiment of the present disclosure;
FIG. 3 illustrates an exemplary circuit diagram of an input reference voltage adjustment circuit according to an embodiment of the present disclosure;
fig. 4 illustrates another exemplary circuit diagram of an input reference voltage adjustment circuit according to an embodiment of the present disclosure.
Elements in the figures are illustrated schematically and not drawn to scale.
Detailed Description
In order to make the objects, technical solutions and advantages of the embodiments of the present disclosure more apparent, the technical solutions of the embodiments of the present disclosure will be clearly and completely described below with reference to the accompanying drawings. It will be apparent that the described embodiments are some, but not all, of the embodiments of the present disclosure. All other embodiments, which can be made by those skilled in the art based on the described embodiments of the present disclosure without the need for creative efforts, are also within the scope of the protection of the present disclosure.
Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by one of ordinary skill in the art to which the presently disclosed subject matter belongs. It will be further understood that terms, such as those defined in commonly used dictionaries, should be interpreted as having a meaning that is consistent with their meaning in the context of the specification and relevant art and will not be interpreted in an idealized or overly formal sense unless expressly so defined herein. As used herein, a statement that two or more parts are "connected" or "coupled" together shall mean that the parts are joined together either directly or joined through one or more intermediate parts.
In all embodiments of the present disclosure, since the source and drain (emitter and collector) of the transistor are symmetrical and the on-current directions between the source and drain (emitter and collector) of the N-type transistor and the P-type transistor are opposite, in embodiments of the present disclosure, the controlled middle terminal of the transistor is referred to as the control pole and the remaining two terminals of the transistor are referred to as the first pole and the second pole, respectively. In addition, terms such as "first" and "second" are used merely to distinguish one component (or portion of a component) from another component (or another portion of a component).
Fig. 1 shows an exemplary circuit diagram of a differential pair circuit 100. In the example of fig. 1, the current source A1 generates a current I1, and when the circuit enters the current-saving mode, the tail current I1 generated by the current source A1 decreases, and the source voltage Vs on the differential pair transistor is reduced transiently. Due to the coupling effect of the parasitic capacitance, a transient change of Vs is coupled into the input reference voltage Vref, causing a transient falling disturbance of Vref. If the transient disturbance of Vref is large, the misoperation of the output signal is caused, and the misoperation is transmitted to the next stage, so that the response of the system error is caused.
Embodiments of the present disclosure provide an input reference voltage adjusting circuit that improves the stability of a circuit by adding a bias circuit to a differential pair, and reducing the disturbance amplitude of the input reference voltage with the potential output by the bias circuit when the tail current changes. Fig. 2 shows a schematic block diagram of an input reference voltage adjustment circuit 200 according to an embodiment of the present disclosure. As shown in fig. 2, the input reference voltage adjusting circuit 200 may include: a current control circuit 210, a current mirror circuit 220, a bias circuit 230, and a differential pair of tubes 240.
The current control circuit 210 may be coupled to the current mirror circuit 220 and the bias circuit 230. The current control circuit 210 is configured to generate a first current signal I1 and to provide said first current signal I1 to said current mirror circuit 220, said bias circuit 230 via a first node N1.
The current mirror circuit 220 may be coupled to the current control circuit 210 and the differential pair transistor 240. The current mirror circuit 220 is configured to generate a first image signal I2 of the first current signal I1 and to provide the first image signal I2 to the source voltage of the differential pair of transistors 240 via a second node N2. Here, the first image signal I2 is a current signal. In some embodiments of the present disclosure, the first image signal I2 is an image signal of the first current signal I1.
The bias circuit 230 may couple the current control circuit 210 and the differential pair transistor 240. The bias circuit 230 is configured to generate a second image signal I4 of the first current signal I1 and to provide a bias voltage to the differential pair of tubes 240 via a third node N3 based on the second image signal I4. Here, the second image signal I4 is a current signal.
Differential pair 240 may be coupled to current mirror circuit 220, bias circuit 230. The differential pair transistor 240 is configured to reduce disturbance of the amplitude of the input reference voltage Vref by the first image signal I2 according to the coupling effect of the bias voltage and the source voltage on the input reference voltage Vref at the same time, wherein the transient change of the bias voltage is opposite to the transient change of the source voltage.
The input reference voltage adjusting circuit according to the embodiment of the disclosure reduces the disturbance amplitude of tail current to the input reference voltage by adding a bias circuit on the differential pair tube and utilizing the potential output by the bias circuit. Thus, the input reference voltage adjustment circuit according to embodiments of the present disclosure reduces the disturbance of the amplitude of the input reference voltage, improving circuit stability, as compared to the differential pair-tube circuit of fig. 1.
Fig. 3 shows an exemplary circuit diagram of an input reference voltage adjustment circuit 200 according to an embodiment of the present disclosure. As shown in fig. 3, the current control circuit 210 may include: a first transistor M1, a second transistor M2, a third transistor M3 and a first current source Ibias. The first pole of the first transistor M1 is coupled to the first voltage terminal V1, the second pole of the first transistor M1 is coupled to the first pole of the second transistor M2, and the control pole of the first transistor M1 is coupled to the second pole of the second transistor M2 and the second pole of the third transistor M3. The control electrode of the second transistor M2 is coupled to the level control terminal crl. The input signal of the level control terminal crl comprises a high level signal and a low level signal. The first pole of the third transistor M3 is coupled to the first voltage terminal V1, the second pole of the third transistor M3 is coupled to the control pole of the third transistor M3, and the control pole of the third transistor M3 is coupled to the first node N1. The first end of the first current source Ibias is coupled to the second pole of the third transistor M3, and the second end of the first current source Ibias is coupled to the second voltage end V2. The example of fig. 3 is not limited to the specific circuit configuration of the first current source Ibias.
The differential pair of tubes 240 may include: an eighth transistor M8 and a ninth transistor M9. The control electrode of the eighth transistor M8 is coupled to the input reference voltage terminal Vref, the substrate of the eighth transistor M8 is coupled to the third node N3, the first electrode of the eighth transistor M8 is coupled to the second node N2, and the second electrode of the eighth transistor M8 is coupled to the first output terminal Vo1. The control electrode of the ninth transistor M9 is coupled to the feedback voltage terminal Vfb, the substrate of the ninth transistor M9 is coupled to the third node N3, the first electrode of the ninth transistor M9 is coupled to the second node N2, and the second electrode of the ninth transistor M9 is coupled to the second output terminal Vo2.
The input reference voltage adjusting circuit provided by the embodiments of the present disclosure may be applicable to an operational amplifier circuit and a comparator circuit, and thus, the first output terminal Vo1 and the second output terminal Vo2 may provide output current signals to other circuits in the operational amplifier circuit or the comparator circuit, and a circuit in which the first output terminal Vo1 and the second output terminal Vo2 are coupled is not limited in the embodiments of the present disclosure.
In the exemplary circuit diagram shown in fig. 3, the eighth transistor M8 and the ninth transistor M9 are PMOS transistors, and correspondingly, the current mirror circuit 220 in fig. 3 may include: and a fifth transistor M5. The control electrode of the fifth transistor M5 is coupled to the first node N1, the first electrode of the fifth transistor M5 is coupled to the first voltage terminal V1, and the second electrode of the fifth transistor M5 is coupled to the second node N2.
Correspondingly, the bias circuit 230 in fig. 3 may include: a fourth transistor M4, a sixth transistor M6, a seventh transistor M7, and a first resistor R1. The control electrode of the fourth transistor M4 is coupled to the first node N1, the first electrode of the fourth transistor M4 is coupled to the first voltage terminal V1, and the second electrode of the fourth transistor M4 is coupled to the first electrode of the sixth transistor M6. The control electrode of the sixth transistor M6 is coupled to the first electrode of the sixth transistor M6 and the control electrode of the seventh transistor M7, and the second electrode of the sixth transistor M6 is coupled to the second voltage terminal V2. A first pole of the seventh transistor M7 is coupled to the third node N3, and a second pole of the seventh transistor M7 is coupled to the second voltage terminal V2. The first end of the first resistor R1 is coupled to the first voltage end V1, and the second end of the first resistor R1 is coupled to the third node N3.
When the eighth transistor M8 and the ninth transistor M9 are both NMOS transistors, as shown in fig. 4, the current mirror circuit 220 may include: a tenth transistor M10, an eleventh transistor M11, and a twelfth transistor M12. The control electrode of the tenth transistor M10 is coupled to the first node N1, the first electrode of the tenth transistor M10 is coupled to the first voltage terminal V1, and the second electrode of the tenth transistor M10 is coupled to the first electrode of the eleventh transistor M11. The control electrode of the eleventh transistor M11 is coupled to the first electrode of the eleventh transistor M11 and the control electrode of the twelfth transistor M12, and the second electrode of the eleventh transistor M11 is coupled to the second voltage terminal V2. A first pole of the twelfth transistor M12 is coupled to the second node N2, and a second pole of the twelfth transistor M12 is coupled to the second voltage terminal V2.
Correspondingly, the bias circuit 230 may include: a thirteenth transistor M13 and a second resistor R2. The control electrode of the thirteenth transistor M13 is coupled to the first node N1, the first electrode of the thirteenth transistor M13 is coupled to the first voltage terminal V1, and the second electrode of the thirteenth transistor M13 is coupled to the third node N3. The first end of the second resistor R2 is coupled to the third node N3, and the second end of the second resistor R2 is coupled to the second voltage end V2.
In the examples of fig. 3 and 4, the internal power supply Vdd in the DC-DC switching power supply is output from the first voltage terminal V1, and the second voltage terminal V2 is grounded. In the example in fig. 3, the first transistor M1 to the fifth transistor M5 are PMOS transistors, and the sixth transistor M6 and the seventh transistor M7 are NMOS transistors. In the example in fig. 4, the first to third transistors M1 to M3, the tenth transistor M10, and the thirteenth transistor M13 are PMOS transistors, and the eleventh transistor M11 and the twelfth transistor M12 are NMOS transistors. It will be appreciated by those skilled in the art that variations of the circuits shown in fig. 3 and 4 based on the above inventive concepts are also within the scope of the present disclosure. In this modification, the above-described transistor and voltage terminal may also have different settings from the examples shown in fig. 3, 4.
The operation of the input reference voltage adjustment circuit 200 according to the embodiment of the present disclosure is described below in conjunction with the example of fig. 3.
Since the second transistor M2 is a PMOS transistor, and the PMOS transistor has a high-level turn-off characteristic and a low-level turn-on characteristic, when the control electrode of the second transistor M2 receives the high-level signal input by the level control terminal crl, the second transistor M2 is turned off, and the first transistor M1 is also turned off, so that all the preset current signals generated by the first current source Ibias flow through the third transistor M3, i.e., the first current signal I1 at this time is a preset current signal, defined as Ia. When the control electrode of the second transistor M2 receives the low level signal input from the level control terminal crl, the second transistor is turned on, so that the preset current signal Ia generated by the first current source Ibias is split, one of the branches flows through the first transistor M1 and the second transistor M2, and the other branch flows through the third transistor M3, so that the first current signal I1 flowing through the third transistor M3 is not the preset current signal Ia, but is a split current signal far smaller than the preset current signal Ia, which is defined as Ir.
When the input reference voltage adjusting circuit provided in the embodiments of the present disclosure is applied to the DC-DC switching power supply circuit, if the DC-DC switching power supply circuit is set to the current-saving mode, the input signal of the level control terminal crl received by the control electrode of the second transistor M2 is changed from the high level signal to the low level signal, and at this time, the first current signal I1 is changed from the preset current signal Ia to the shunt current signal Ir, and since the third transistor M3 and the fifth transistor M5 form a current mirror, the currents flowing through the third transistor M3 and the fifth transistor M5 are equal. Thus, the first image signal I2 of the shunt current signal Ir is outputted from the second pole of the fifth transistor M5. Since the first image signal I2 is changed from the preset current signal Ia to the shunt current signal Ir, the first image signal I2 is reduced, resulting in a transient reduction of the source voltage VS in the differential pair transistor 240, and due to the coupling effect of the parasitic capacitance, the transient variation of the source voltage VS is coupled into the input reference voltage Vref, resulting in a transient reduction disturbance of the input reference voltage Vref.
In the bias circuit 230, the fourth transistor M4 and the third transistor M3 form a current mirror, so that the current flowing through the third transistor M3 and the fourth transistor M4 is equal, and the current I3 flowing through the fourth transistor M4 is equal to the first current signal I1. In addition, the current I3 flowing through the fourth transistor M4 flows into the sixth transistor M6, and the sixth transistor M6 and the seventh transistor M7 form a current mirror, so that the current flowing through the sixth transistor M6 and the seventh transistor M7 are equal, i.e., the current I3 flowing through the fourth transistor M4 is equal to the second mirror signal I4, i.e., i1=i3=i4. When the first current signal I1 is changed from the preset current signal Ia to the shunt current signal Ir, the second image signal I4 is also changed from the preset current signal Ia to the shunt current signal Ir. That is, the current supplied to the first resistor R1 becomes small, the voltage dividing transient of the first resistor R1 becomes small, and the voltage transient on the bias voltage VB rises. By coupling the parasitic capacitance to the base voltage terminal and the input reference voltage terminal, the bias voltage VB can counteract the falling amplitude of a portion of the source voltage VS, so that the voltage amplitude of the source voltage VS coupled to the input reference voltage Vref is reduced, since the polarity of the transient change of the bias voltage VB acting on the base voltage terminal is opposite to that of the source voltage VS. Meanwhile, the bias voltage VB may also be coupled to the input reference voltage terminal to offset the falling trend of part of the input reference voltage Vref. Thus, the reverse transient variation of the bias voltage VB and the source voltage VS can reduce the disturbance amplitude of the coupled input reference voltage Vref.
Similarly, when the DC-DC switching power supply circuit is set to the normal operation mode by the current saving mode, the input signal of the level control terminal crl received by the control electrode of the second transistor M2 is changed from the low level signal to the high level signal, and at this time, the first current signal I1 is changed from the shunt current signal Ir to the preset current signal Ia, so that the first image signal I2 is changed from the shunt current signal Ir to the preset current signal Ia, and the first image signal I2 is increased, resulting in a transient increase of the source voltage VS in the differential pair transistor 240, and the transient change of the source voltage VS is coupled to the input reference voltage Vref due to the coupling effect of the parasitic capacitance, thereby causing a transient increase disturbance of the input reference voltage Vref. In the bias circuit 230, when the first current signal I1 is changed from the shunt current signal Ir to the preset current signal Ia, the second image signal I4 is also changed from the shunt current signal Ir to the preset current signal Ia. That is, the current supplied to the first resistor R1 becomes large, the voltage dividing transient of the first resistor R1 becomes large, and the voltage transient on the bias voltage VB decreases. Through parasitic capacitance coupling to the base voltage terminal and the input reference voltage terminal, the bias voltage VB can counteract the rising amplitude of part of the source voltage VS, so that the voltage amplitude of the source voltage VS coupled to the input reference voltage Vref is improved. Meanwhile, the bias voltage VB may also be coupled to the input reference voltage terminal to offset the rising trend of part of the input reference voltage Vref. Thus, the reverse transient variation of the bias voltage VB and the source voltage VS can reduce the disturbance amplitude of the coupled input reference voltage Vref.
If the operation of the input reference voltage adjusting circuit 200 according to the embodiment of the present disclosure is described with reference to the example of fig. 4, when the control electrode of the second transistor M2 receives the low level signal input by the level control terminal crl, the second transistor is turned on, and thus the preset current signal Ia generated by the first current source Ibias is split, so that the first current signal I1 flowing through the third transistor M3 is not the preset current signal Ia, but is far smaller than the split current signal Ir of the preset current signal Ia. When the input signal of the level control terminal crl received by the control electrode of the second transistor M2 is changed from the high level signal to the low level signal, the first current signal I1 is changed from the preset current signal Ia to the shunt current signal Ir, and the third transistor M3 and the tenth transistor M10 form a current mirror, so that the currents flowing through the third transistor M3 and the tenth transistor M10 are equal. Thus, the mirror signal I5 of the shunt current signal Ir is output from the second pole of the tenth transistor M10. Since the eleventh transistor M11 and the twelfth transistor M12 form a current mirror, the first image signal I6 output from the second pole of the twelfth transistor M12 is equal to the shunt current signal Ir. Since the first image signal I6 is changed from the preset current signal Ia to the shunt current signal Ir, the first image signal I6 is reduced, resulting in a transient increase of the source voltage VS in the differential pair transistor 240, and due to the coupling effect of the parasitic capacitance, the transient variation of the source voltage VS is coupled into the input reference voltage Vref, resulting in a transient rising disturbance of the input reference voltage Vref.
In the bias circuit 230 shown in fig. 4, since the thirteenth transistor M13 and the third transistor M3 form a current mirror, the current flowing through the third transistor M3 and the thirteenth transistor M13 is equal, and the second current mirror signal I7 flowing through the thirteenth transistor M13 is equal to the first current signal I1. When the first current signal I1 is changed from the preset current signal Ia to the shunt current signal Ir, the second image signal I7 is also changed from the preset current signal Ia to the shunt current signal Ir. That is, the current supplied to the second resistor R2 becomes smaller, the voltage dividing transient of the second resistor R2 becomes smaller, and the voltage transient on the bias voltage VB becomes smaller. By coupling the parasitic capacitance to the base voltage terminal and the input reference voltage terminal, the bias voltage VB can counteract the rising amplitude of a portion of the source voltage VS, resulting in a reduced voltage amplitude of the source voltage VS coupled to the input reference voltage Vref, since the polarity of the transient change of the bias voltage VB acting on the base voltage terminal is opposite to the polarity of the transient change of the source voltage VS. Meanwhile, the bias voltage VB may also be coupled to the input reference voltage terminal to offset the rising trend of part of the input reference voltage Vref. Thus, the reverse transient variation of the bias voltage VB and the source voltage VS can reduce the disturbance amplitude of the coupled input reference voltage Vref.
Similarly, when the DC-DC switching power supply circuit is set to the normal operation mode by the current saving mode, the input signal of the level control terminal crl received by the control electrode of the second transistor M2 is changed from the low level signal to the high level signal, and at this time, the first current signal I1 is changed from the shunt current signal Ir to the preset current signal Ia, so that the first image signal I6 is changed from the shunt current signal Ir to the preset current signal Ia, the first image signal I6 is increased, resulting in a transient reduction of the source voltage VS in the differential pair transistor 240, and the transient variation of the source voltage VS is coupled to the input reference voltage Vref due to the coupling effect of the parasitic capacitance, thereby causing a transient falling disturbance of the input reference voltage Vref. In the bias circuit 230, when the first current signal I1 is changed from the shunt current signal Ir to the preset current signal Ia, the second image signal I7 is also changed from the shunt current signal Ir to the preset current signal Ia. That is, the current supplied to the second resistor R2 becomes large, the voltage dividing transient of the second resistor R2 becomes large, and the voltage transient on the bias voltage VB rises. Through parasitic capacitance coupling to the base voltage terminal and the input reference voltage terminal, the bias voltage VB can counteract the falling amplitude of part of the source voltage VS, so that the voltage amplitude of the source voltage VS coupled to the input reference voltage Vref is improved. Meanwhile, the bias voltage VB may also be coupled to the input reference voltage terminal to offset the falling trend of part of the input reference voltage Vref. Thus, the reverse transient variation of the bias voltage VB and the source voltage VS can reduce the disturbance amplitude of the coupled input reference voltage Vref.
In summary, the input reference voltage adjusting circuit according to the embodiment of the disclosure reduces the disturbance amplitude of the coupled input reference voltage Vref, avoids malfunction of the output signal, and improves the stability of the circuit.
The flowcharts and block diagrams in the figures illustrate the architecture, functionality, and operation of possible implementations of apparatus and methods according to various embodiments of the present disclosure. In this regard, each block in the flowchart or block diagrams may represent a module, segment, or portion of instructions, which comprises one or more executable instructions for implementing the specified logical function(s). In some alternative implementations, the functions noted in the block may occur out of the order noted in the figures. For example, two blocks shown in succession may, in fact, be executed substantially concurrently, or the blocks may sometimes be executed in the reverse order, depending upon the functionality involved. It will also be noted that each block of the block diagrams and/or flowchart illustration, and combinations of blocks in the block diagrams and/or flowchart illustration, can be implemented by special purpose hardware-based systems which perform the specified functions or acts, or combinations of special purpose hardware and computer instructions.
As used herein and in the appended claims, the singular forms of words include the plural and vice versa, unless the context clearly dictates otherwise. Thus, when referring to the singular, the plural of the corresponding term is generally included. Similarly, the terms "comprising" and "including" are to be construed as being inclusive rather than exclusive. Likewise, the terms "comprising" and "or" should be interpreted as inclusive, unless such an interpretation is expressly prohibited herein. Where the term "example" is used herein, particularly when it follows a set of terms, the "example" is merely exemplary and illustrative and should not be considered exclusive or broad.
Further aspects and scope of applicability will become apparent from the description provided herein. It should be understood that various aspects of the present application may be implemented alone or in combination with one or more other aspects. It should also be understood that the description and specific examples are intended for purposes of illustration only and are not intended to limit the scope of the present disclosure.
While several embodiments of the present disclosure have been described in detail, it will be apparent to those skilled in the art that various modifications and variations can be made to the embodiments of the present disclosure without departing from the spirit and scope of the disclosure. The scope of the present disclosure is defined by the appended claims.
Claims (12)
1. An input reference voltage adjustment circuit, comprising: a current control circuit, a current mirror circuit, a bias circuit and a differential pair transistor,
wherein the current control circuit is configured to generate a first current signal and provide the first current signal to the current mirror circuit, the bias circuit via a first node;
the current mirror circuit is configured to generate a first image signal of the first current signal and provide the first image signal to a source voltage of the differential pair of tubes via a second node;
the bias circuit is configured to generate a second image signal of the first current signal and provide a bias voltage to the differential pair of tubes via a third node based on the second image signal;
the differential pair of transistors is configured to reduce a disturbance of the first mirror signal to the magnitude of the input reference voltage based on a coupling of the bias voltage and the source voltage to the input reference voltage simultaneously, a transient change in the bias voltage being of opposite polarity to a transient change in the source voltage.
2. The input reference voltage adjustment circuit of claim 1, wherein the current control circuit comprises: a first transistor, a second transistor, a third transistor and a first current source,
Wherein a first pole of the first transistor is coupled to a first voltage terminal, a second pole of the first transistor is coupled to a first pole of the second transistor, and a control pole of the first transistor is coupled to a second pole of the second transistor and a second pole of the third transistor;
the control electrode of the second transistor is coupled with the level control end;
a first electrode of the third transistor is coupled to the first voltage terminal, a second electrode of the third transistor is coupled to a control electrode of the third transistor, and a control electrode of the third transistor is coupled to the first node;
the first end of the first current source is coupled to the second pole of the third transistor, and the second end of the first current source is coupled to the second voltage end.
3. The input reference voltage regulation circuit of claim 2, wherein the differential pair of tubes comprises: an eighth transistor and a ninth transistor,
the control electrode of the eighth transistor is coupled to the input reference voltage end, the substrate of the eighth transistor is coupled to the third node, the first electrode of the eighth transistor is coupled to the second node, and the second electrode of the eighth transistor is coupled to the first output end;
The control electrode of the ninth transistor is coupled to the feedback voltage terminal, the substrate of the ninth transistor is coupled to the third node, the first electrode of the ninth transistor is coupled to the second node, and the second electrode of the ninth transistor is coupled to the second output terminal.
4. The input reference voltage adjustment circuit of claim 3, wherein when the eighth transistor and the ninth transistor are both PMOS transistors, the current mirror circuit comprises: a fifth transistor is provided which has a third transistor,
the control electrode of the fifth transistor is coupled to the first node, the first electrode of the fifth transistor is coupled to the first voltage terminal, and the second electrode of the fifth transistor is coupled to the second node.
5. The input reference voltage adjustment circuit of claim 3, wherein when the eighth transistor and the ninth transistor are both PMOS transistors, the bias circuit comprises: a fourth transistor, a sixth transistor, a seventh transistor and a first resistor,
the control electrode of the fourth transistor is coupled to the first node, the first electrode of the fourth transistor is coupled to the first voltage terminal, and the second electrode of the fourth transistor is coupled to the first electrode of the sixth transistor;
The control electrode of the sixth transistor is coupled with the first electrode of the sixth transistor and the control electrode of the seventh transistor, and the second electrode of the sixth transistor is coupled with the second voltage end;
a first pole of the seventh transistor is coupled to the third node, and a second pole of the seventh transistor is coupled to the second voltage terminal;
the first end of the first resistor is coupled to a first voltage end, and the second end of the first resistor is coupled to the third node.
6. The input reference voltage adjustment circuit of claim 3, wherein when the eighth transistor and the ninth transistor are both NMOS transistors, the current mirror circuit comprises: a tenth transistor, an eleventh transistor, and a twelfth transistor,
the control electrode of the tenth transistor is coupled to the first node, the first electrode of the tenth transistor is coupled to the first voltage terminal, and the second electrode of the tenth transistor is coupled to the first electrode of the eleventh transistor;
a control electrode of the eleventh transistor is coupled to the first electrode of the eleventh transistor and the control electrode of the twelfth transistor, and a second electrode of the eleventh transistor is coupled to the second voltage terminal;
The first pole of the twelfth transistor is coupled to the second node, and the second pole of the twelfth transistor is coupled to the second voltage terminal.
7. The input reference voltage adjustment circuit of claim 3, wherein when the eighth transistor and the ninth transistor are both NMOS transistors, the bias circuit comprises: a thirteenth transistor and a second resistor,
the control electrode of the thirteenth transistor is coupled to the first node, the first electrode of the thirteenth transistor is coupled to the first voltage terminal, and the second electrode of the thirteenth transistor is coupled to the third node;
the first end of the second resistor is coupled to the third node, and the second end of the second resistor is coupled to a second voltage end.
8. The input reference voltage adjustment circuit of claim 3, wherein,
when the control electrode of the second transistor receives a high-level signal input by the level control end, the second transistor is turned off, and the first current signal flowing through the third transistor is a preset current signal generated by the first current source;
when the control electrode of the second transistor receives the low-level signal input by the level control end, the second transistor is turned on, the first current signal flowing through the third transistor is a shunt current signal generated by the first current source,
Wherein the preset current signal is greater than the shunt current signal.
9. The input reference voltage adjustment circuit of claim 8, wherein when the eighth transistor and the ninth transistor are PMOS transistors and the control electrode of the second transistor receives the input signal from the level control terminal changing from the high level signal to the low level signal, the first current signal changes from the preset current signal to the shunt current signal, the source voltage is transiently reduced, and the bias voltage is transiently increased; or alternatively
When the control electrode of the second transistor receives that the input signal of the level control end is changed from the low level signal to the high level signal, the first current signal is changed from the shunt current signal to the preset current signal, the source voltage is increased in a transient state, and the bias voltage is reduced in a transient state.
10. The input reference voltage adjustment circuit of claim 8, wherein when the eighth transistor and the ninth transistor are NMOS transistors and the control electrode of the second transistor receives the input signal from the level control terminal changing from the high level signal to the low level signal, the first current signal changes from the preset current signal to the shunt current signal, the source voltage is transiently increased, and the bias voltage is transiently decreased; or alternatively
When the control electrode of the second transistor receives that the input signal of the level control end is changed from the low level signal to the high level signal, the first current signal is changed from the shunt current signal to the preset current signal, the source voltage is reduced in a transient state, and the bias voltage is increased in a transient state.
11. An input reference voltage adjustment circuit, comprising: first to ninth transistors, a first current source and a first resistor,
the first electrode of the first transistor is coupled with the first voltage end, the second electrode of the first transistor is coupled with the first electrode of the second transistor, and the control electrode of the first transistor is coupled with the second electrode of the second transistor;
the control electrode of the second transistor is coupled with the level control end;
the control electrode of the third transistor is coupled to a first node, the first electrode of the third transistor is coupled to the first voltage end, and the second electrode of the third transistor is coupled to the second electrode of the second transistor;
a first end of the first current source is coupled with a second pole of the second transistor, and a second end of the first current source is coupled with a second voltage end;
The control electrode of the fourth transistor is coupled to the first node, the first electrode of the fourth transistor is coupled to the first voltage terminal, and the second electrode of the fourth transistor is coupled to the first electrode of the sixth transistor;
the control electrode of the fifth transistor is coupled to the first node, the first electrode of the fifth transistor is coupled to the first voltage terminal, and the second electrode of the fifth transistor is coupled to the second node;
the control electrode of the sixth transistor is coupled with the first electrode of the sixth transistor and the control electrode of the seventh transistor, and the second electrode of the sixth transistor is coupled with the second voltage end;
a first pole of the seventh transistor is coupled to a third node, and a second pole of the seventh transistor is coupled to the second voltage terminal;
a first end of the first resistor is coupled to a first voltage end, and a second end of the first resistor is coupled to the third node;
the control electrode of the eighth transistor is coupled to the input reference voltage end, the substrate of the eighth transistor is coupled to the third node, the first electrode of the eighth transistor is coupled to the second node, and the second electrode of the eighth transistor is coupled to the first output end;
the control electrode of the ninth transistor is coupled to the feedback voltage terminal, the substrate of the ninth transistor is coupled to the third node, the first electrode of the ninth transistor is coupled to the second node, and the second electrode of the ninth transistor is coupled to the second output terminal.
12. An input reference voltage adjustment circuit, comprising: first to third transistors, eighth to thirteenth transistors, a first current source and a second resistor,
the first electrode of the first transistor is coupled with the first voltage end, the second electrode of the first transistor is coupled with the first electrode of the second transistor, and the control electrode of the first transistor is coupled with the second electrode of the second transistor;
the control electrode of the second transistor is coupled with the level control end;
the control electrode of the third transistor is coupled to a first node, the first electrode of the third transistor is coupled to the first voltage end, and the second electrode of the third transistor is coupled to the second electrode of the second transistor;
a first end of the first current source is coupled with a second pole of the second transistor, and a second end of the first current source is coupled with a second voltage end;
the control electrode of the eighth transistor is coupled with the input reference voltage end, the substrate of the eighth transistor is coupled with the third node, the first electrode of the eighth transistor is coupled with the second node, and the second electrode of the eighth transistor is coupled with the first output end;
the control electrode of the ninth transistor is coupled to the feedback voltage terminal, the substrate of the ninth transistor is coupled to the third node, the first electrode of the ninth transistor is coupled to the second node, and the second electrode of the ninth transistor is coupled to the second output terminal;
The control electrode of the tenth transistor is coupled to the first node, the first electrode of the tenth transistor is coupled to the first voltage terminal, and the second electrode of the tenth transistor is coupled to the first electrode of the eleventh transistor;
a control electrode of the eleventh transistor is coupled to the first electrode of the eleventh transistor and the control electrode of the twelfth transistor, and a second electrode of the eleventh transistor is coupled to the second voltage terminal;
a first pole of the twelfth transistor is coupled to the second node, and a second pole of the twelfth transistor is coupled to the second voltage terminal;
a control electrode of the thirteenth transistor is coupled to the first node, a first electrode of the thirteenth transistor is coupled to a first voltage terminal, and a second electrode of the thirteenth transistor is coupled to the third node;
the first end of the second resistor is coupled to the third node, and the second end of the second resistor is coupled to a second voltage end.
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