CN115113682A - Input reference voltage adjusting circuit - Google Patents
Input reference voltage adjusting circuit Download PDFInfo
- Publication number
- CN115113682A CN115113682A CN202210886190.6A CN202210886190A CN115113682A CN 115113682 A CN115113682 A CN 115113682A CN 202210886190 A CN202210886190 A CN 202210886190A CN 115113682 A CN115113682 A CN 115113682A
- Authority
- CN
- China
- Prior art keywords
- transistor
- coupled
- electrode
- node
- voltage
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 230000001052 transient effect Effects 0.000 claims abstract description 49
- 230000008859 change Effects 0.000 claims abstract description 16
- 230000001808 coupling effect Effects 0.000 claims abstract description 9
- 230000003247 decreasing effect Effects 0.000 claims description 8
- 230000033228 biological regulation Effects 0.000 claims description 5
- 238000010586 diagram Methods 0.000 description 12
- 230000003071 parasitic effect Effects 0.000 description 9
- 239000003990 capacitor Substances 0.000 description 7
- 230000000630 rising effect Effects 0.000 description 5
- 230000008878 coupling Effects 0.000 description 4
- 238000010168 coupling process Methods 0.000 description 4
- 238000005859 coupling reaction Methods 0.000 description 4
- 230000007423 decrease Effects 0.000 description 3
- 230000004044 response Effects 0.000 description 3
- 230000004048 modification Effects 0.000 description 2
- 238000012986 modification Methods 0.000 description 2
- 238000004891 communication Methods 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 230000007257 malfunction Effects 0.000 description 1
- 238000000034 method Methods 0.000 description 1
- 230000009467 reduction Effects 0.000 description 1
Images
Classifications
-
- G—PHYSICS
- G05—CONTROLLING; REGULATING
- G05F—SYSTEMS FOR REGULATING ELECTRIC OR MAGNETIC VARIABLES
- G05F3/00—Non-retroactive systems for regulating electric variables by using an uncontrolled element, or an uncontrolled combination of elements, such element or such combination having self-regulating properties
- G05F3/02—Regulating voltage or current
- G05F3/08—Regulating voltage or current wherein the variable is dc
- G05F3/10—Regulating voltage or current wherein the variable is dc using uncontrolled devices with non-linear characteristics
- G05F3/16—Regulating voltage or current wherein the variable is dc using uncontrolled devices with non-linear characteristics being semiconductor devices
- G05F3/20—Regulating voltage or current wherein the variable is dc using uncontrolled devices with non-linear characteristics being semiconductor devices using diode- transistor combinations
- G05F3/26—Current mirrors
Landscapes
- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Nonlinear Science (AREA)
- Electromagnetism (AREA)
- General Physics & Mathematics (AREA)
- Radar, Positioning & Navigation (AREA)
- Automation & Control Theory (AREA)
- Amplifiers (AREA)
Abstract
The embodiment of the disclosure provides an input reference voltage adjusting circuit, and belongs to the technical field of integrated circuits. The input reference voltage adjustment circuit includes: the current control circuit comprises a current control circuit, a current mirror circuit, a bias circuit and a differential pair transistor. The current control circuit generates a first current signal and provides the first current signal to the current mirror circuit and the bias circuit through a first node; the current mirror circuit generates a first image signal of the first current signal and provides the first image signal to the source voltage of the differential pair transistor through a second node; the bias circuit generates a second image signal of the first current signal and provides bias voltage to the differential pair transistor through a third node based on the second image signal; and the differential pair transistor reduces the disturbance of the first image signal to the amplitude of the input reference voltage according to the coupling effect of the bias voltage and the source voltage on the input reference voltage at the same time, and the transient change of the bias voltage and the transient change of the source voltage have opposite polarities.
Description
Technical Field
The embodiment of the disclosure relates to the technical field of integrated circuits, in particular to an input reference voltage adjusting circuit.
Background
The DC-DC switching power supply is an important component widely applied to the field of power supply management, and can be applied to the fields of mobile phones, mobile power supplies, network communication, automotive electronics, consumer electronics and the like. With the rapid development of power management technology, the requirements on indexes such as efficiency, transient response speed, load regulation rate, linear regulation rate and the like of a DC-DC switching power supply are higher and higher, and when the DC-DC switching power supply enters a current-saving mode, transient disturbance of input reference voltage of differential pair transistors in the DC-DC switching power supply is easily caused due to transient reduction of tail current, so that misoperation of output signals is caused and is transmitted to the next stage of the differential pair transistors, and error response of the DC-DC switching power supply is caused.
Disclosure of Invention
The purpose of the embodiments of the present disclosure is to provide an input reference voltage adjusting circuit, which increases a bias circuit on a differential pair transistor, and when a tail current changes, reduces a disturbance amplitude of an input reference voltage by using a potential output by the bias circuit, thereby improving the stability of the circuit.
In order to achieve the above object, a first aspect of the embodiments of the present disclosure provides an input reference voltage adjustment circuit, including: the current control circuit comprises a current control circuit, a current mirror circuit, a bias circuit and a differential pair transistor. Wherein the current control circuit is configured to generate a first current signal and provide the first current signal to the current mirror circuit, the bias circuit via a first node; the current mirror circuit is configured to generate a first mirror signal of the first current signal and provide the first mirror signal to source voltages of the differential pair transistors via a second node; the bias circuit is configured to generate a second image signal of the first current signal and provide a bias voltage to the differential pair transistor via a third node based on the second image signal; the differential pair transistor is configured to reduce disturbance of the first image signal to the amplitude of an input reference voltage according to the coupling effect of the bias voltage and the source voltage on the input reference voltage at the same time, and the transient change of the bias voltage is opposite in polarity to the transient change of the source voltage.
In some embodiments of the present disclosure, the current control circuit comprises: a first transistor, a second transistor, a third transistor, and a first current source. A first pole of the first transistor is coupled to a first voltage terminal, a second pole of the first transistor is coupled to a first pole of the second transistor, and a control pole of the first transistor is coupled to a second pole of the second transistor and a second pole of the third transistor; the control electrode of the second transistor is coupled with the level control end; a first pole of the third transistor is coupled to the first voltage terminal, a second pole of the third transistor is coupled to a control pole of the third transistor, and the control pole of the third transistor is coupled to the first node; a first terminal of the first current source is coupled to the second pole of the third transistor, and a second terminal of the first current source is coupled to a second voltage terminal.
In some embodiments of the present disclosure, the differential pair transistor comprises: an eighth transistor and a ninth transistor. A control electrode of the eighth transistor is coupled to the input reference voltage terminal, a base electrode of the eighth transistor is coupled to the third node, a first electrode of the eighth transistor is coupled to the second node, and a second electrode of the eighth transistor is coupled to the first output terminal; a control electrode of the ninth transistor is coupled to the feedback voltage terminal, a base electrode of the ninth transistor is coupled to the third node, a first electrode of the ninth transistor is coupled to the second node, and a second electrode of the ninth transistor is coupled to the second output terminal.
In some embodiments of the present disclosure, when the eighth transistor and the ninth transistor are both PMOS transistors, the current mirror circuit includes: and a fifth transistor. A control electrode of the fifth transistor is coupled to the first node, a first electrode of the fifth transistor is coupled to the first voltage terminal, and a second electrode of the fifth transistor is coupled to the second node.
In some embodiments of the present disclosure, when the eighth transistor and the ninth transistor are both PMOS transistors, the bias circuit includes: a fourth transistor, a sixth transistor, a seventh transistor, and a first resistor. A control electrode of the fourth transistor is coupled to the first node, a first electrode of the fourth transistor is coupled to the first voltage terminal, and a second electrode of the fourth transistor is coupled to the first electrode of the sixth transistor; a control electrode of the sixth transistor is coupled to the first electrode of the sixth transistor and the control electrode of the seventh transistor, and a second electrode of the sixth transistor is coupled to the second voltage terminal; a first pole of the seventh transistor is coupled to the third node, and a second pole of the seventh transistor is coupled to the second voltage terminal; a first end of the first resistor is coupled to a first voltage end, and a second end of the first resistor is coupled to the third node.
In some embodiments of the present disclosure, when the eighth transistor and the ninth transistor are both NMOS transistors, the current mirror circuit includes: a tenth transistor, an eleventh transistor, and a twelfth transistor, wherein a control electrode of the tenth transistor is coupled to the first node, a first electrode of the tenth transistor is coupled to the first voltage terminal, and a second electrode of the tenth transistor is coupled to the first electrode of the eleventh transistor; a control electrode of the eleventh transistor is coupled to a first electrode of the eleventh transistor and a control electrode of the twelfth transistor, and a second electrode of the eleventh transistor is coupled to a second voltage terminal; a first pole of the twelfth transistor is coupled to the second node, and a second pole of the twelfth transistor is coupled to the second voltage terminal. In some embodiments of the present disclosure, when the eighth transistor and the ninth transistor are both NMOS transistors, the bias circuit includes: a thirteenth transistor and a second resistor, wherein a control electrode of the thirteenth transistor is coupled to the first node, a first electrode of the thirteenth transistor is coupled to a first voltage terminal, and a second electrode of the thirteenth transistor is coupled to the third node; a first end of the second resistor is coupled to the third node, and a second end of the second resistor is coupled to a second voltage terminal.
In some embodiments of the present disclosure, when the control electrode of the second transistor receives a high level signal input by the level control terminal, the second transistor is turned off, and the first current signal flowing through the third transistor is a preset current signal generated by the first current source; when the control electrode of the second transistor receives a low level signal input by the level control terminal, the second transistor is turned on, the first current signal flowing through the third transistor is a shunt current signal generated by the first current source, wherein the preset current signal is greater than the shunt current signal.
In some embodiments of the present disclosure, when the eighth transistor and the ninth transistor are both PMOS transistors and the control electrode of the second transistor receives that the input signal of the level control terminal changes from the high level signal to the low level signal, the first current signal changes from the preset current signal to the shunt current signal, the source voltage is transiently decreased, and the bias voltage is transiently increased; or when the control electrode of the second transistor receives the input signal of the level control end, the low level signal is changed into the high level signal, the first current signal is changed into the preset current signal from the shunt current signal, the source voltage is increased transiently, and the bias voltage is decreased transiently.
In some embodiments of the present disclosure, when the eighth transistor and the ninth transistor are both NMOS transistors and the control electrode of the second transistor receives the input signal of the level control terminal changed from the high level signal to the low level signal, the first current signal is changed from the preset current signal to the shunt current signal, the source voltage is transiently increased, and the bias voltage is transiently decreased; or when the control electrode of the second transistor receives the input signal of the level control end, the low level signal is changed into the high level signal, the first current signal is changed into the preset current signal from the shunt current signal, the source voltage is reduced in a transient state, and the bias voltage is increased in a transient state.
A second aspect of the embodiments of the present disclosure provides an input reference voltage adjustment circuit, including: first to ninth transistors, a first current source, and a first resistor. A first pole of the first transistor is coupled to a first voltage terminal, a second pole of the first transistor is coupled to a first pole of the second transistor, and a control pole of the first transistor is coupled to a second pole of the second transistor; a control electrode of the second transistor is coupled with a level control end; a control electrode of the third transistor is coupled to the first node, a first electrode of the third transistor is coupled to the first voltage terminal, and a second electrode of the third transistor is coupled to a second electrode of the second transistor; a first terminal of the first current source is coupled to the second pole of the second transistor, and a second terminal of the first current source is coupled to a second voltage terminal; a control electrode of the fourth transistor is coupled to the first node, a first electrode of the fourth transistor is coupled to the first voltage terminal, and a second electrode of the fourth transistor is coupled to a first electrode of the sixth transistor; a control electrode of the fifth transistor is coupled to the first node, a first electrode of the fifth transistor is coupled to a first voltage terminal, and a second electrode of the fifth transistor is coupled to the second node; a control electrode of the sixth transistor is coupled to the first electrode of the sixth transistor and the control electrode of the seventh transistor, and a second electrode of the sixth transistor is coupled to the second voltage terminal; a first pole of the seventh transistor is coupled to the third node, and a second pole of the seventh transistor is coupled to the second voltage terminal; a first end of the first resistor is coupled to a first voltage end, and a second end of the first resistor is coupled to the third node; a control electrode of the eighth transistor is coupled to the input reference voltage terminal, a base electrode of the eighth transistor is coupled to the third node, a first electrode of the eighth transistor is coupled to the second node, and a second electrode of the eighth transistor is coupled to the first output terminal; a control electrode of the ninth transistor is coupled to the feedback voltage terminal, a base electrode of the ninth transistor is coupled to the third node, a first electrode of the ninth transistor is coupled to the second node, and a second electrode of the ninth transistor is coupled to the second output terminal.
A third aspect of the embodiments of the present disclosure provides an input reference voltage adjustment circuit, including: first to third transistors, eighth to thirteenth transistors, a first current source, and a second resistor. A first pole of the first transistor is coupled to a first voltage terminal, a second pole of the first transistor is coupled to a first pole of the second transistor, and a control pole of the first transistor is coupled to a second pole of the second transistor; the control electrode of the second transistor is coupled with the level control end; a control electrode of the third transistor is coupled to the first node, a first electrode of the third transistor is coupled to the first voltage terminal, and a second electrode of the third transistor is coupled to a second electrode of the second transistor; a first terminal of the first current source is coupled to the second pole of the second transistor, and a second terminal of the first current source is coupled to a second voltage terminal; a control electrode of the eighth transistor is coupled to the input reference voltage terminal, a base electrode of the eighth transistor is coupled to the third node, a first electrode of the eighth transistor is coupled to the second node, and a second electrode of the eighth transistor is coupled to the first output terminal; a control electrode of the ninth transistor is coupled to the feedback voltage terminal, a base electrode of the ninth transistor is coupled to the third node, a first electrode of the ninth transistor is coupled to the second node, and a second electrode of the ninth transistor is coupled to the second output terminal; a control electrode of the tenth transistor is coupled to the first node, a first electrode of the tenth transistor is coupled to the first voltage terminal, and a second electrode of the tenth transistor is coupled to the first electrode of the eleventh transistor; a control electrode of the eleventh transistor is coupled to a first electrode of the eleventh transistor and a control electrode of the twelfth transistor, and a second electrode of the eleventh transistor is coupled to a second voltage terminal; a first pole of the twelfth transistor is coupled to the second node, and a second pole of the twelfth transistor is coupled to the second voltage terminal; a control electrode of the thirteenth transistor is coupled to the first node, a first electrode of the thirteenth transistor is coupled to a first voltage terminal, and a second electrode of the thirteenth transistor is coupled to the third node; a first end of the second resistor is coupled to the third node, and a second end of the second resistor is coupled to a second voltage terminal.
By the technical scheme, the bias circuit is added on the differential pair transistor, the reverse transient change of the bias voltage and the source voltage is utilized to reduce the coupled disturbance amplitude of the input reference voltage, and the stability of the circuit is improved.
Additional features and advantages of embodiments of the present disclosure will be described in detail in the detailed description which follows.
Drawings
The accompanying drawings, which are included to provide a further understanding of the embodiments of the disclosure and are incorporated in and constitute a part of this specification, illustrate embodiments of the disclosure and together with the detailed description serve to explain the embodiments of the disclosure, but are not intended to limit the embodiments of the disclosure. In the drawings:
FIG. 1 is an exemplary circuit diagram of a differential pair tube circuit;
FIG. 2 is a schematic block diagram of an input reference voltage adjustment circuit according to an embodiment of the present disclosure;
FIG. 3 illustrates an exemplary circuit diagram of an input reference voltage adjustment circuit according to an embodiment of the present disclosure;
fig. 4 illustrates another exemplary circuit diagram of an input reference voltage adjustment circuit according to an embodiment of the present disclosure.
The elements in the drawings are schematic and not drawn to scale.
Detailed Description
In order to make the objects, technical solutions and advantages of the embodiments of the present disclosure more clear, the technical solutions of the embodiments of the present disclosure will be clearly and completely described below with reference to the accompanying drawings. It is to be understood that the described embodiments are only a few embodiments of the present disclosure, and not all embodiments. All other embodiments, which can be derived by a person skilled in the art from the described embodiments of the disclosure without inventive step, are also within the scope of protection of the disclosure.
Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by one of ordinary skill in the art to which the presently disclosed subject matter belongs. It will be further understood that terms, such as those defined in commonly used dictionaries, should be interpreted as having a meaning that is consistent with their meaning in the context of the specification and relevant art and will not be interpreted in an idealized or overly formal sense unless expressly so defined herein. As used herein, the statement that two or more parts are "connected" or "coupled" together shall mean that the parts are joined together either directly or joined through one or more intermediate components.
In all embodiments of the present disclosure, since the sources and drains (emitters and collectors) of the transistors are symmetrical and the on-currents between the sources and drains (emitters and collectors) of the N-type transistors and the P-type transistors are opposite in direction, in the embodiments of the present disclosure, the controlled middle end of the transistor is referred to as a control electrode, and the remaining two ends of the transistor are referred to as a first electrode and a second electrode, respectively. In addition, terms such as "first" and "second" are only used to distinguish one element (or part of an element) from another element (or another part of an element).
Fig. 1 shows an exemplary circuit diagram of a differential pair transistor circuit 100. In the example of fig. 1, the current source a1 generates a current I1, and when the circuit enters the current-saving mode, the tail current I1 generated by the current source a1 decreases, and the source voltage Vs across the differential pair transistor is transiently decreased. Due to the coupling effect of the parasitic capacitance, transient changes of Vs can be coupled into the input reference voltage Vref, causing transient falling disturbances of Vref. If transient disturbance of Vref is large, the output signal is in error operation and is transmitted to the next stage, thereby causing the response of system error.
The embodiment of the disclosure provides an input reference voltage adjusting circuit, which increases a bias circuit on a differential pair transistor, and reduces the disturbance amplitude of the input reference voltage by using the potential output by the bias circuit when the tail current changes, so as to improve the stability of the circuit. Fig. 2 shows a schematic block diagram of an input reference voltage adjustment circuit 200 according to an embodiment of the present disclosure. As shown in fig. 2, the input reference voltage adjusting circuit 200 may include: current control circuit 210, current mirror circuit 220, bias circuit 230, and differential pair transistor 240.
The current control circuit 210 may couple the current mirror circuit 220 and the bias circuit 230. The current control circuit 210 is configured to generate a first current signal I1 and provide the first current signal I1 to the current mirror circuit 220, the bias circuit 230 via a first node N1.
The current mirror circuit 220 may be coupled to the current control circuit 210 and the differential pair transistor 240. The current mirror circuit 220 is configured to generate a first mirror signal I2 of the first current signal I1 and provide the first mirror signal I2 to the source voltage of the differential pair transistor 240 via a second node N2. Here, the first image signal I2 is a current signal. In some embodiments of the present disclosure, the first image signal I2 is an image signal of the first current signal I1.
The bias circuit 230 may be coupled to the current control circuit 210 and the differential pair transistor 240. The bias circuit 230 is configured to generate a second mirror signal I4 of the first current signal I1 and provide a bias voltage to the differential pair transistor 240 via a third node N3 based on the second mirror signal I4. Here, the second image signal I4 is a current signal.
The differential pair transistor 240 may be coupled to the current mirror circuit 220 and the bias circuit 230. The differential pair transistor 240 is configured to reduce a disturbance of the first image signal I2 to the magnitude of an input reference voltage Vref according to a coupling effect of the bias voltage and the source voltage on the input reference voltage Vref at the same time, and a transient change of the bias voltage is opposite in polarity to a transient change of the source voltage.
According to the input reference voltage adjusting circuit disclosed by the embodiment of the disclosure, the offset circuit is added on the differential pair transistor, and the disturbance amplitude of tail current to the input reference voltage is reduced by using the potential output by the offset circuit. Therefore, compared with the differential pair transistor circuit of fig. 1, the input reference voltage adjusting circuit according to the embodiment of the disclosure reduces the disturbance of the amplitude of the input reference voltage, and improves the circuit stability.
Fig. 3 illustrates an exemplary circuit diagram of an input reference voltage adjustment circuit 200 according to an embodiment of the present disclosure. As shown in fig. 3, the current control circuit 210 may include: a first transistor M1, a second transistor M2, a third transistor M3, and a first current source Ibias. A first pole of the first transistor M1 is coupled to the first voltage terminal V1, a second pole of the first transistor M1 is coupled to the first pole of the second transistor M2, and a control pole of the first transistor M1 is coupled to the second pole of the second transistor M2 and the second pole of the third transistor M3. The control electrode of the second transistor M2 is coupled to the level control terminal crl. Wherein, the input signal of the level control terminal crl includes a high level signal and a low level signal. A first pole of the third transistor M3 is coupled to the first voltage terminal V1, a second pole of the third transistor M3 is coupled to a control pole of the third transistor M3, and a control pole of the third transistor M3 is coupled to the first node N1. A first terminal of the first current source Ibias is coupled to the second terminal of the third transistor M3, and a second terminal of the first current source Ibias is coupled to the second voltage terminal V2. The example of fig. 3 does not limit the specific circuit structure of the first current source Ibias.
The differential pair transistors 240 may include: an eighth transistor M8 and a ninth transistor M9. A control electrode of the eighth transistor M8 is coupled to the input reference voltage terminal Vref, a base electrode of the eighth transistor M8 is coupled to the third node N3, a first electrode of the eighth transistor M8 is coupled to the second node N2, and a second electrode of the eighth transistor M8 is coupled to the first output terminal Vo 1. A control electrode of the ninth transistor M9 is coupled to the feedback voltage terminal Vfb, a base electrode of the ninth transistor M9 is coupled to the third node N3, a first electrode of the ninth transistor M9 is coupled to the second node N2, and a second electrode of the ninth transistor M9 is coupled to the second output terminal Vo 2.
The input reference voltage adjusting circuit provided by the embodiment of the disclosure may be applied to an operational amplifier circuit and a comparator circuit, and therefore, the first output Vo1 and the second output Vo2 may provide output current signals to other circuits in the operational amplifier circuit or the comparator circuit, and the circuit to which the first output Vo1 and the second output Vo2 are coupled is not limited in the embodiment of the disclosure.
In the exemplary circuit diagram shown in fig. 3, the eighth transistor M8 and the ninth transistor M9 are both PMOS transistors, and correspondingly, the current mirror circuit 220 in fig. 3 may include: and a fifth transistor M5. A control electrode of the fifth transistor M5 is coupled to the first node N1, a first electrode of the fifth transistor M5 is coupled to a first voltage terminal V1, and a second electrode of the fifth transistor M5 is coupled to the second node N2.
Correspondingly, the bias circuit 230 in fig. 3 may include: a fourth transistor M4, a sixth transistor M6, a seventh transistor M7, and a first resistor R1. A control electrode of the fourth transistor M4 is coupled to the first node N1, a first electrode of the fourth transistor M4 is coupled to a first voltage terminal V1, and a second electrode of the fourth transistor M4 is coupled to a first electrode of the sixth transistor M6. The control electrode of the sixth transistor M6 is coupled to the first electrode of the sixth transistor M6 and the control electrode of the seventh transistor M7, and the second electrode of the sixth transistor M6 is coupled to the second voltage terminal V2. A first pole of the seventh transistor M7 is coupled to the third node N3, and a second pole of the seventh transistor M7 is coupled to the second voltage terminal V2. A first end of the first resistor R1 is coupled to a first voltage terminal V1, and a second end of the first resistor R1 is coupled to the third node N3.
When both the eighth transistor M8 and the ninth transistor M9 are NMOS transistors, as shown in fig. 4, the current mirror circuit 220 may include: a tenth transistor M10, an eleventh transistor M11, and a twelfth transistor M12. A control electrode of the tenth transistor M10 is coupled to the first node N1, a first electrode of the tenth transistor M10 is coupled to the first voltage terminal V1, and a second electrode of the tenth transistor M10 is coupled to a first electrode of the eleventh transistor M11. A control electrode of the eleventh transistor M11 is coupled to the first electrode of the eleventh transistor M11 and the control electrode of the twelfth transistor M12, and a second electrode of the eleventh transistor M11 is coupled to the second voltage terminal V2. A first pole of the twelfth transistor M12 is coupled to the second node N2, and a second pole of the twelfth transistor M12 is coupled to the second voltage terminal V2.
Correspondingly, the bias circuit 230 may include: a thirteenth transistor M13 and a second resistor R2. A control electrode of the thirteenth transistor M13 is coupled to the first node N1, a first electrode of the thirteenth transistor M13 is coupled to the first voltage terminal V1, and a second electrode of the thirteenth transistor M13 is coupled to the third node N3. A first end of the second resistor R2 is coupled to the third node N3, and a second end of the second resistor R2 is coupled to a second voltage terminal V2.
In the example of fig. 3 and 4, the internal power supply Vdd in the DC-DC switching power supply is output from the first voltage terminal V1, and the second voltage terminal V2 is grounded. In the example in fig. 3, the first to fifth transistors M1 to M5 are PMOS transistors, and the sixth and seventh transistors M6 and M7 are NMOS transistors. In the example in fig. 4, the first to third transistors M1 to M3, the tenth transistor M10 and the thirteenth transistor M13 are PMOS transistors, and the eleventh transistor M11 and the twelfth transistor M12 are all NMOS transistors. Those skilled in the art will appreciate that variations to the circuits shown in fig. 3 and 4 based on the above inventive concepts are intended to fall within the scope of the present disclosure. In this modification, the above-described transistor and voltage terminal may also have different arrangements from the examples shown in fig. 3, 4.
The operation of the input reference voltage adjusting circuit 200 according to the embodiment of the disclosure is described below with reference to the example of fig. 3.
Because the second transistor M2 is a PMOS transistor and the PMOS transistor has the characteristics of turning off at a high level and turning on at a low level, when the control electrode of the second transistor M2 receives a high level signal inputted from the level control terminal crl, the second transistor M2 is turned off, and the first transistor M1 is also turned off, so that the preset current signal generated by the first current source Ibias flows through the third transistor M3, that is, the first current signal I1 is a preset current signal defined as Ia. When the control electrode of the second transistor M2 receives a low level signal inputted from the level control terminal crl, the second transistor is turned on, so that the preset current signal Ia generated by the first current source Ibias is shunted, one current signal passes through the branch of the first transistor M1 and the second transistor M2, and the other current signal passes through the branch of the third transistor M3, so that the first current signal I1 passing through the third transistor M3 is not the preset current signal Ia, but a shunt current signal, here defined as Ir, much smaller than the preset current signal Ia.
When the input reference voltage adjusting circuit provided by the embodiment of the disclosure is applied to a DC-DC switching power supply circuit, if the DC-DC switching power supply circuit is set to the current-saving mode, the input signal of the level control terminal crl received by the control electrode of the second transistor M2 is changed from the high level signal to the low level signal, and at this time, the first current signal I1 is changed from the preset current signal Ia to the shunt current signal Ir, since the third transistor M3 and the fifth transistor M5 form a current mirror, currents flowing through the third transistor M3 and the fifth transistor M5 are equal. Thus, the first mirror signal I2 of the shunt current signal Ir is output from the second pole of the fifth transistor M5. Since the first mirror signal I2 is changed from the predetermined current signal Ia to the shunt current signal Ir, the first mirror signal I2 is decreased, which results in a transient decrease of the source voltage VS in the differential pair transistor 240, and due to the coupling effect of the parasitic capacitor, the transient change of the source voltage VS is coupled to the input reference voltage Vref, causing a transient drop disturbance of the input reference voltage Vref.
In the bias circuit 230, the fourth transistor M4 and the third transistor M3 form a current mirror, so that the currents flowing through the third transistor M3 and the fourth transistor M4 are equal, and the current I3 flowing through the fourth transistor M4 is equal to the first current signal I1. In addition, since the current I3 flowing through the fourth transistor M4 flows into the sixth transistor M6, and the sixth transistor M6 and the seventh transistor M7 form a current mirror, the current flowing through the sixth transistor M6 and the seventh transistor M7 are equal to each other, that is, the current I3 flowing through the fourth transistor M4 is equal to the second mirror signal I4, that is, I1 ═ I3 ═ I4. When the first current signal I1 changes from the preset current signal Ia to the shunt current signal Ir, the second mirror signal I4 also changes from the preset current signal Ia to the shunt current signal Ir. That is, the current supplied to the first resistor R1 becomes small, the voltage division transient of the first resistor R1 becomes small, and the voltage on the bias voltage VB transiently rises. The parasitic capacitor is coupled to the base voltage terminal and the input reference voltage terminal, and since the polarity of the transient variation of the bias voltage VB acting on the base voltage terminal is opposite to the polarity of the transient variation of the source voltage VS, the bias voltage VB can counteract part of the falling amplitude of the source voltage VS, so that the voltage amplitude of the source voltage VS coupled to the input reference voltage Vref is reduced. Meanwhile, the bias voltage VB can also be coupled to the input reference voltage end to counteract the descending trend of part of the input reference voltage Vref. Thus, the reverse transient variation of the bias voltage VB and the source voltage VS can reduce the disturbance amplitude of the input reference voltage Vref by coupling.
Similarly, when the DC-DC switching power supply circuit is set from the current-saving mode to the normal operation mode, the input signal of the level control terminal crl received by the control electrode of the second transistor M2 is changed from the low level signal to the high level signal, and at this time, the first current signal I1 is changed from the shunt current signal Ir to the preset current signal Ia, so that the first image signal I2 is changed from the shunt current signal Ir to the preset current signal Ia, and the first image signal I2 is increased, which results in a transient increase of the source voltage VS in the differential pair transistor 240, because of the coupling effect of the parasitic capacitor, the transient change of the source voltage VS is coupled to the input reference voltage Vref, causing a transient increase disturbance of the input reference voltage Vref. In the bias circuit 230, when the first current signal I1 is changed from the shunt current signal Ir to the predetermined current signal Ia, the second mirror signal I4 is also changed from the shunt current signal Ir to the predetermined current signal Ia. That is, the current supplied to the first resistor R1 becomes large, the voltage division transient of the first resistor R1 becomes large, and the voltage on the bias voltage VB transiently drops. The parasitic capacitor is coupled to the base voltage terminal and the input reference voltage terminal, and the bias voltage VB acting on the base voltage terminal has the polarity of transient change opposite to that of transient change of the source voltage VS, so that the bias voltage VB can counteract part of the rising amplitude of the source voltage VS, and the voltage amplitude of the source voltage VS coupled to the input reference voltage Vref is improved. Meanwhile, the bias voltage VB can also be coupled to the input reference voltage end to counteract the rising trend of part of the input reference voltage Vref. Thus, the reverse transient variation of the bias voltage VB and the source voltage VS can reduce the disturbance amplitude of the input reference voltage Vref by coupling.
If the operation of the input reference voltage adjusting circuit 200 according to the embodiment of the disclosure is described with reference to the example of fig. 4, when the control electrode of the second transistor M2 receives the low level signal inputted from the level control terminal crl, the second transistor is turned on, so that the preset current signal Ia generated by the first current source Ibias is shunted, and the first current signal I1 flowing through the third transistor M3 is not the preset current signal Ia, but the shunt current signal Ir which is much smaller than the preset current signal Ia. When the input signal of the level control terminal crl received by the control electrode of the second transistor M2 changes from the high level signal to the low level signal, the first current signal I1 changes from the preset current signal Ia to the shunt current signal Ir, and since the third transistor M3 and the tenth transistor M10 form a current mirror, the currents flowing through the third transistor M3 and the tenth transistor M10 are equal. Thus, the mirror signal I5 of the shunt current signal Ir is output from the second pole of the tenth transistor M10. In addition, since the eleventh transistor M11 and the twelfth transistor M12 constitute a current mirror, the first mirror signal I6 output from the second pole of the twelfth transistor M12 is equal to the shunt current signal Ir. Since the first mirror signal I6 is changed from the predetermined current signal Ia to the shunt current signal Ir, the first mirror signal I6 is decreased, which results in a transient increase of the source voltage VS in the differential pair transistor 240, and due to the coupling effect of the parasitic capacitance, the transient change of the source voltage VS is coupled to the input reference voltage Vref, causing a transient rising disturbance of the input reference voltage Vref.
In the bias circuit 230 shown in fig. 4, since the thirteenth transistor M13 and the third transistor M3 form a current mirror, the currents flowing through the third transistor M3 and the thirteenth transistor M13 are equal, and the second current mirror signal I7 flowing through the thirteenth transistor M13 is equal to the first current signal I1. When the first current signal I1 changes from the preset current signal Ia to the shunt current signal Ir, the second mirror signal I7 also changes from the preset current signal Ia to the shunt current signal Ir. That is, the current supplied to the second resistor R2 becomes small, the voltage division transient of the second resistor R2 becomes small, and the voltage transient on the bias voltage VB becomes small. The parasitic capacitor is coupled to the base voltage terminal and the input reference voltage terminal, and since the polarity of the transient variation of the bias voltage VB acting on the base voltage terminal is opposite to the polarity of the transient variation of the source voltage VS, the bias voltage VB can counteract part of the rising amplitude of the source voltage VS, so that the voltage amplitude of the source voltage VS coupled to the input reference voltage Vref is reduced. Meanwhile, the bias voltage VB can also be coupled to the input reference voltage end to counteract the rising trend of part of the input reference voltage Vref. Thus, the reverse transient variation of the bias voltage VB and the source voltage VS can reduce the disturbance amplitude of the input reference voltage Vref by coupling.
Similarly, when the DC-DC switching power supply circuit is set from the current-saving mode to the normal operation mode, the input signal of the level control terminal crl received by the control electrode of the second transistor M2 is changed from the low level signal to the high level signal, and at this time, the first current signal I1 is changed from the shunt current signal Ir to the preset current signal Ia, so that the first image signal I6 is changed from the shunt current signal Ir to the preset current signal Ia, and the first image signal I6 is increased, which results in a transient decrease of the source voltage VS in the differential pair transistor 240, because of the coupling effect of the parasitic capacitor, the transient change of the source voltage VS is coupled to the input reference voltage Vref, causing a transient drop disturbance of the input reference voltage Vref. In the bias circuit 230, when the first current signal I1 is changed from the shunt current signal Ir to the predetermined current signal Ia, the second mirror signal I7 is also changed from the shunt current signal Ir to the predetermined current signal Ia. That is, the current supplied to the second resistor R2 becomes large, the voltage division transient of the second resistor R2 becomes large, and the voltage on the bias voltage VB transiently rises. The parasitic capacitor is coupled to the base voltage terminal and the input reference voltage terminal, and the bias voltage VB acting on the base voltage terminal has a transient change polarity opposite to that of the source voltage VS, so that the bias voltage VB can counteract part of the falling amplitude of the source voltage VS, and the voltage amplitude of the source voltage VS coupled to the input reference voltage Vref is increased. Meanwhile, the bias voltage VB can also be coupled to the input reference voltage end to counteract the descending trend of part of the input reference voltage Vref. Thus, the reverse transient variation of the bias voltage VB and the source voltage VS can reduce the disturbance amplitude of the input reference voltage Vref by coupling.
In summary, the input reference voltage adjusting circuit according to the embodiment of the disclosure reduces the coupled disturbance amplitude of the input reference voltage Vref, avoids the malfunction of the output signal, and improves the stability of the circuit.
The flowchart and block diagrams in the figures illustrate the architecture, functionality, and operation of possible implementations of apparatus and methods according to various embodiments of the present disclosure. In this regard, each block in the flowchart or block diagrams may represent a module, segment, or portion of instructions, which comprises one or more executable instructions for implementing the specified logical function(s). In some alternative implementations, the functions noted in the block may occur out of the order noted in the figures. For example, two blocks shown in succession may, in fact, be executed substantially concurrently, or the blocks may sometimes be executed in the reverse order, depending upon the functionality involved. It will also be noted that each block of the block diagrams and/or flowchart illustration, and combinations of blocks in the block diagrams and/or flowchart illustration, can be implemented by special purpose hardware-based systems which perform the specified functions or acts, or combinations of special purpose hardware and computer instructions.
As used herein and in the appended claims, the singular forms of words include the plural and vice versa, unless the context clearly dictates otherwise. Thus, when reference is made to the singular, it is generally intended to include the plural of the corresponding term. Similarly, the terms "comprising" and "including" are to be construed as being inclusive rather than exclusive. Likewise, the terms "include" and "or" should be construed as inclusive unless such an interpretation is explicitly prohibited herein. Where the term "example" is used herein, particularly when it comes after a set of terms, it is merely exemplary and illustrative and should not be considered exclusive or extensive.
Further aspects and ranges of adaptability will become apparent from the description provided herein. It should be understood that various aspects of the present application may be implemented alone or in combination with one or more other aspects. It should also be understood that the description and specific examples are intended for purposes of illustration only and are not intended to limit the scope of the present disclosure.
Several embodiments of the present disclosure have been described in detail above, but it is apparent that various modifications and variations can be made to the embodiments of the present disclosure by those skilled in the art without departing from the spirit and scope of the present disclosure. The scope of the present disclosure is defined by the appended claims.
Claims (12)
1. An input reference voltage regulation circuit, comprising: a current control circuit, a current mirror circuit, a bias circuit, and a differential pair transistor,
wherein the current control circuit is configured to generate a first current signal and provide the first current signal to the current mirror circuit, the bias circuit via a first node;
the current mirror circuit is configured to generate a first mirror signal of the first current signal and provide the first mirror signal to a source voltage of the differential pair transistor via a second node;
the bias circuit is configured to generate a second image signal of the first current signal and provide a bias voltage to the differential pair transistor via a third node based on the second image signal;
the differential pair transistor is configured to reduce disturbance of the first image signal to the amplitude of an input reference voltage according to the coupling effect of the bias voltage and the source voltage on the input reference voltage at the same time, and the transient change of the bias voltage is opposite in polarity to the transient change of the source voltage.
2. The input-reference voltage adjustment circuit of claim 1, wherein the current control circuit comprises: a first transistor, a second transistor, a third transistor, and a first current source,
a first pole of the first transistor is coupled to a first voltage terminal, a second pole of the first transistor is coupled to a first pole of the second transistor, and a control pole of the first transistor is coupled to a second pole of the second transistor and a second pole of the third transistor;
the control electrode of the second transistor is coupled with the level control end;
a first pole of the third transistor is coupled to the first voltage terminal, a second pole of the third transistor is coupled to a control pole of the third transistor, and the control pole of the third transistor is coupled to the first node;
a first terminal of the first current source is coupled to the second pole of the third transistor, and a second terminal of the first current source is coupled to a second voltage terminal.
3. The input-reference voltage adjustment circuit of claim 2, wherein the differential pair transistor comprises: an eighth transistor and a ninth transistor,
a control electrode of the eighth transistor is coupled to the input reference voltage terminal, a base electrode of the eighth transistor is coupled to the third node, a first electrode of the eighth transistor is coupled to the second node, and a second electrode of the eighth transistor is coupled to the first output terminal;
a control electrode of the ninth transistor is coupled to the feedback voltage terminal, a base electrode of the ninth transistor is coupled to the third node, a first electrode of the ninth transistor is coupled to the second node, and a second electrode of the ninth transistor is coupled to the second output terminal.
4. The input-reference-voltage adjustment circuit according to claim 3, wherein when the eighth transistor and the ninth transistor are both PMOS transistors, the current mirror circuit includes: a fifth transistor for controlling the operation of the transistor,
a control electrode of the fifth transistor is coupled to the first node, a first electrode of the fifth transistor is coupled to the first voltage terminal, and a second electrode of the fifth transistor is coupled to the second node.
5. The input-reference voltage adjustment circuit of claim 3, wherein when the eighth transistor and the ninth transistor are both PMOS transistors, the bias circuit comprises: a fourth transistor, a sixth transistor, a seventh transistor, and a first resistor,
a control electrode of the fourth transistor is coupled to the first node, a first electrode of the fourth transistor is coupled to a first voltage terminal, and a second electrode of the fourth transistor is coupled to a first electrode of the sixth transistor;
a control electrode of the sixth transistor is coupled to the first electrode of the sixth transistor and the control electrode of the seventh transistor, and a second electrode of the sixth transistor is coupled to the second voltage terminal;
a first pole of the seventh transistor is coupled to the third node, and a second pole of the seventh transistor is coupled to the second voltage terminal;
the first end of the first resistor is coupled to a first voltage end, and the second end of the first resistor is coupled to the third node.
6. The input reference voltage adjustment circuit according to claim 3, wherein when the eighth transistor and the ninth transistor are both NMOS transistors, the current mirror circuit includes: a tenth transistor, an eleventh transistor, and a twelfth transistor,
a control electrode of the tenth transistor is coupled to the first node, a first electrode of the tenth transistor is coupled to the first voltage terminal, and a second electrode of the tenth transistor is coupled to the first electrode of the eleventh transistor;
a control electrode of the eleventh transistor is coupled to a first electrode of the eleventh transistor and a control electrode of the twelfth transistor, and a second electrode of the eleventh transistor is coupled to a second voltage terminal;
a first pole of the twelfth transistor is coupled to the second node, and a second pole of the twelfth transistor is coupled to the second voltage terminal.
7. The input-reference voltage adjustment circuit of claim 3, wherein when the eighth transistor and the ninth transistor are both NMOS transistors, the bias circuit comprises: a thirteenth transistor and a second resistor,
a control electrode of the thirteenth transistor is coupled to the first node, a first electrode of the thirteenth transistor is coupled to the first voltage terminal, and a second electrode of the thirteenth transistor is coupled to the third node;
a first end of the second resistor is coupled to the third node, and a second end of the second resistor is coupled to a second voltage terminal.
8. The input reference voltage adjustment circuit of claim 3,
when the control electrode of the second transistor receives a high level signal input by the level control end, the second transistor is turned off, and the first current signal flowing through the third transistor is a preset current signal generated by the first current source;
when the control electrode of the second transistor receives a low level signal input by the level control terminal, the second transistor is turned on, the first current signal flowing through the third transistor is a shunt current signal generated by the first current source,
wherein the preset current signal is greater than the shunt current signal.
9. The input-reference voltage adjustment circuit of claim 8, wherein when the eighth transistor and the ninth transistor are both PMOS transistors and a control electrode of the second transistor receives the input signal of the level control terminal changing from the high level signal to the low level signal, the first current signal changes from the preset current signal to the shunt current signal, the source voltage is transiently decreased, and the bias voltage is transiently increased; or
When the control electrode of the second transistor receives the input signal of the level control end, the low level signal is changed into the high level signal, the first current signal is changed into the preset current signal from the shunt current signal, the source voltage is increased in a transient state, and the bias voltage is reduced in a transient state.
10. The input-reference voltage adjustment circuit of claim 8, wherein when the eighth transistor and the ninth transistor are both NMOS transistors and a control electrode of the second transistor receives the input signal of the level control terminal changing from the high level signal to the low level signal, the first current signal changes from the preset current signal to the shunt current signal, the source voltage is transiently increased, and the bias voltage is transiently decreased; or
When the control electrode of the second transistor receives the input signal of the level control end, the low level signal is changed into the high level signal, the first current signal is changed into the preset current signal from the shunt current signal, the source voltage is reduced in a transient state, and the bias voltage is increased in a transient state.
11. An input reference voltage regulation circuit, comprising: first to ninth transistors, a first current source, and a first resistor,
a first pole of the first transistor is coupled to a first voltage terminal, a second pole of the first transistor is coupled to a first pole of the second transistor, and a control pole of the first transistor is coupled to a second pole of the second transistor;
the control electrode of the second transistor is coupled with the level control end;
a control electrode of the third transistor is coupled to the first node, a first electrode of the third transistor is coupled to the first voltage terminal, and a second electrode of the third transistor is coupled to a second electrode of the second transistor;
a first terminal of the first current source is coupled to the second pole of the second transistor, and a second terminal of the first current source is coupled to a second voltage terminal;
a control electrode of the fourth transistor is coupled to the first node, a first electrode of the fourth transistor is coupled to the first voltage terminal, and a second electrode of the fourth transistor is coupled to a first electrode of the sixth transistor;
a control electrode of the fifth transistor is coupled to the first node, a first electrode of the fifth transistor is coupled to a first voltage terminal, and a second electrode of the fifth transistor is coupled to the second node;
a control electrode of the sixth transistor is coupled to the first electrode of the sixth transistor and the control electrode of the seventh transistor, and a second electrode of the sixth transistor is coupled to the second voltage terminal;
a first pole of the seventh transistor is coupled to the third node, and a second pole of the seventh transistor is coupled to the second voltage terminal;
a first end of the first resistor is coupled to a first voltage end, and a second end of the first resistor is coupled to the third node;
a control electrode of the eighth transistor is coupled to the input reference voltage terminal, a base electrode of the eighth transistor is coupled to the third node, a first electrode of the eighth transistor is coupled to the second node, and a second electrode of the eighth transistor is coupled to the first output terminal;
a control electrode of the ninth transistor is coupled to the feedback voltage terminal, a base electrode of the ninth transistor is coupled to the third node, a first electrode of the ninth transistor is coupled to the second node, and a second electrode of the ninth transistor is coupled to the second output terminal.
12. An input reference voltage regulation circuit, comprising: first to third transistors, eighth to thirteenth transistors, a first current source, and a second resistor,
a first pole of the first transistor is coupled to a first voltage terminal, a second pole of the first transistor is coupled to a first pole of the second transistor, and a control pole of the first transistor is coupled to a second pole of the second transistor;
the control electrode of the second transistor is coupled with the level control end;
a control electrode of the third transistor is coupled to the first node, a first electrode of the third transistor is coupled to the first voltage terminal, and a second electrode of the third transistor is coupled to a second electrode of the second transistor;
a first terminal of the first current source is coupled to the second pole of the second transistor, and a second terminal of the first current source is coupled to a second voltage terminal;
a control electrode of the eighth transistor is coupled to the input reference voltage terminal, a base electrode of the eighth transistor is coupled to the third node, a first electrode of the eighth transistor is coupled to the second node, and a second electrode of the eighth transistor is coupled to the first output terminal;
a control electrode of the ninth transistor is coupled to the feedback voltage terminal, a base electrode of the ninth transistor is coupled to the third node, a first electrode of the ninth transistor is coupled to the second node, and a second electrode of the ninth transistor is coupled to the second output terminal;
a control electrode of the tenth transistor is coupled to the first node, a first electrode of the tenth transistor is coupled to the first voltage terminal, and a second electrode of the tenth transistor is coupled to the first electrode of the eleventh transistor;
a control electrode of the eleventh transistor is coupled to a first electrode of the eleventh transistor and a control electrode of the twelfth transistor, and a second electrode of the eleventh transistor is coupled to a second voltage terminal;
a first pole of the twelfth transistor is coupled to the second node, and a second pole of the twelfth transistor is coupled to the second voltage terminal;
a control electrode of the thirteenth transistor is coupled to the first node, a first electrode of the thirteenth transistor is coupled to a first voltage terminal, and a second electrode of the thirteenth transistor is coupled to the third node;
a first end of the second resistor is coupled to the third node, and a second end of the second resistor is coupled to a second voltage terminal.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202210886190.6A CN115113682B (en) | 2022-07-26 | 2022-07-26 | Input reference voltage adjusting circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202210886190.6A CN115113682B (en) | 2022-07-26 | 2022-07-26 | Input reference voltage adjusting circuit |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN115113682A true CN115113682A (en) | 2022-09-27 |
| CN115113682B CN115113682B (en) | 2024-03-15 |
Family
ID=83334638
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN202210886190.6A Active CN115113682B (en) | 2022-07-26 | 2022-07-26 | Input reference voltage adjusting circuit |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN115113682B (en) |
Citations (8)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2002064343A (en) * | 2000-08-21 | 2002-02-28 | New Japan Radio Co Ltd | Defferential amplifier circuit |
| US6509795B1 (en) * | 2001-09-26 | 2003-01-21 | Texas Instruments Incorporated | CMOS input stage with wide common-mode range |
| US20050275462A1 (en) * | 2004-06-15 | 2005-12-15 | Heightley John D | Low voltage differential amplifier circuit and a sampled low power bias control technique enabling accommodation of an increased range of input levels |
| CN1713520A (en) * | 2004-06-15 | 2005-12-28 | 茂德科技股份有限公司 | Differential amplifier circuit and method for controlling differential amplifier circuit |
| CN101556482A (en) * | 2008-04-07 | 2009-10-14 | 半导体元件工业有限责任公司 | Method for adjusting threshold voltage and circuit therefor |
| CN110266186A (en) * | 2019-06-14 | 2019-09-20 | 思力科（深圳）电子科技有限公司 | Low-leakage current charge pump circuit |
| CN112148060A (en) * | 2019-06-26 | 2020-12-29 | 圣邦微电子（北京）股份有限公司 | Input stage substrate voltage control circuit of crossover-distortion-free operational amplifier |
| CN112803721A (en) * | 2020-12-30 | 2021-05-14 | 合肥视涯技术有限公司 | Voltage converter |
-
2022
- 2022-07-26 CN CN202210886190.6A patent/CN115113682B/en active Active
Patent Citations (8)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2002064343A (en) * | 2000-08-21 | 2002-02-28 | New Japan Radio Co Ltd | Defferential amplifier circuit |
| US6509795B1 (en) * | 2001-09-26 | 2003-01-21 | Texas Instruments Incorporated | CMOS input stage with wide common-mode range |
| US20050275462A1 (en) * | 2004-06-15 | 2005-12-15 | Heightley John D | Low voltage differential amplifier circuit and a sampled low power bias control technique enabling accommodation of an increased range of input levels |
| CN1713520A (en) * | 2004-06-15 | 2005-12-28 | 茂德科技股份有限公司 | Differential amplifier circuit and method for controlling differential amplifier circuit |
| CN101556482A (en) * | 2008-04-07 | 2009-10-14 | 半导体元件工业有限责任公司 | Method for adjusting threshold voltage and circuit therefor |
| CN110266186A (en) * | 2019-06-14 | 2019-09-20 | 思力科（深圳）电子科技有限公司 | Low-leakage current charge pump circuit |
| CN112148060A (en) * | 2019-06-26 | 2020-12-29 | 圣邦微电子（北京）股份有限公司 | Input stage substrate voltage control circuit of crossover-distortion-free operational amplifier |
| CN112803721A (en) * | 2020-12-30 | 2021-05-14 | 合肥视涯技术有限公司 | Voltage converter |
Also Published As
| Publication number | Publication date |
|---|---|
| CN115113682B (en) | 2024-03-15 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| US9553548B2 (en) | Low drop out voltage regulator and method therefor | |
| TWI411903B (en) | Low drop out voltage regulator | |
| EP1111493A1 (en) | Low drop voltage regulators with low quiescent current | |
| US20130241504A1 (en) | Self-calibrating, stable ldo regulator | |
| US9146570B2 (en) | Load current compesating output buffer feedback, pass, and sense circuits | |
| JP2004005670A (en) | Low dropout regulator comprising current feedback amplifier and compound feedback loop | |
| US11644854B2 (en) | LDO, MCU, fingerprint module and terminal device | |
| US20040212421A1 (en) | Standard voltage generation circuit | |
| CN116185113A (en) | Soft start circuit, low dropout linear voltage regulator, chip and electronic equipment | |
| CN107171650B (en) | Variable gain amplifier circuit | |
| KR20090048327A (en) | Voltage regulator | |
| US6720836B2 (en) | CMOS relaxation oscillator circuit with improved speed and reduced process/temperature variations | |
| CN115268546B (en) | Bandgap reference circuit with transient enhancement | |
| CN116736922A (en) | Low-dropout linear voltage regulator | |
| CN115113682B (en) | Input reference voltage adjusting circuit | |
| CN107256055B (en) | Capacitor LDO circuit outside a kind of no piece | |
| CN115549675A (en) | Oscillator circuit | |
| US20220035394A1 (en) | Regulator | |
| CN115065226A (en) | Soft start circuit for DC-DC converter | |
| CN115840483A (en) | Low dropout regulator with transient enhancement characteristic | |
| CN115328244A (en) | Upper clamping circuit of operational amplifier | |
| CN115390606A (en) | Voltage regulator | |
| US8987949B1 (en) | Linear regulator with multiple outputs and local feedback | |
| CN115268547B (en) | Band gap reference circuit | |
| US20240113612A1 (en) | Gate driver for a low dropout voltage regulator |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PB01 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| GR01 | Patent grant | ||
| GR01 | Patent grant |