CN107171650B - Variable gain amplifier circuit - Google Patents
Variable gain amplifier circuit Download PDFInfo
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- CN107171650B CN107171650B CN201610129741.9A CN201610129741A CN107171650B CN 107171650 B CN107171650 B CN 107171650B CN 201610129741 A CN201610129741 A CN 201610129741A CN 107171650 B CN107171650 B CN 107171650B
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03G—CONTROL OF AMPLIFICATION
- H03G3/00—Gain control in amplifiers or frequency changers
- H03G3/20—Automatic control
- H03G3/30—Automatic control in amplifiers having semiconductor devices
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03F—AMPLIFIERS
- H03F3/00—Amplifiers with only discharge tubes or only semiconductor devices as amplifying elements
- H03F3/45—Differential amplifiers
- H03F3/45071—Differential amplifiers with semiconductor devices only
- H03F3/45479—Differential amplifiers with semiconductor devices only characterised by the way of common mode signal rejection
- H03F3/45632—Differential amplifiers with semiconductor devices only characterised by the way of common mode signal rejection in differential amplifiers with FET transistors as the active amplifying circuit
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Abstract
A variable gain amplifier circuit is used for amplifying a voltage difference between a first input signal and a second input signal so as to generate an amplified differential output signal. The variable gain amplifier circuit comprises an operational amplifier, an input element, a feedback element, a dynamic bias circuit and a transconductance amplifier. The dynamic bias circuit is used for generating a bias current according to a set value. The transconductance amplifier is used for converting the voltage difference between the first input signal and the second input signal to generate an analog output current flowing through the feedback element. The analog output current varies in accordance with the bias current.
Description
Technical Field
The present invention relates to a variable gain amplifier circuit.
Background
The variable gain amplifying circuit is used for amplifying or attenuating an input signal according to a gain control signal. Fig. 1 is a schematic diagram of a conventional variable gain amplifier circuit. The variable gain Amplifier circuit 100 includes a differential Operational Amplifier (Operational Amplifier)12, resistors R1A and R1B having fixed resistance values, and resistors R2A and R2B having variable resistance values.
As shown in FIG. 1, each of the resistors R2A and R2B has a plurality of circuit units connected in parallel, wherein each circuit unit is composed of a transistor switch and a resistor connected in series. A gain controller 14 generates logic signals to the transistor switches in resistor R2A and a gain controller 16 generates logic signals to the transistor switches in resistor R2B. The resistances of the resistors R2A and R2B are determined by the on state of the transistor switch. Therefore, by turning on and off the switches, the resistances of the resistors R2A and R2B are changed, thereby changing the gain of the variable gain amplifier circuit 100.
In this way, when the resistance of the resistor R1A is equal to the resistance of the resistor R1B, and the resistance of the resistor R2A is equal to the resistance of the resistor R2B, the gain of the variable gain amplifier circuit 100 is determined by the ratio of the resistance of the resistor R2A to the resistance of the resistor R1A. When the gain of the variable gain amplification circuit 100 requires N-stage variation, the circuit unit in each of the resistors R2A and R2B requires N transistor switches and N resistors. Therefore, the chip area of the variable gain amplifier circuit 100 increases with the number of stages N.
Disclosure of Invention
According to an embodiment of the present invention, a variable gain amplifier circuit is used for amplifying a voltage difference between a first input signal and a second input signal to generate an amplified differential output signal. The variable gain amplifier circuit comprises an operational amplifier, a first input element, a feedback element, a dynamic bias circuit and a transconductance amplifier. The operational amplifier has a first input terminal, a second input terminal and an output terminal for providing the amplified differential output signal. The first input element has a first terminal for receiving the first input signal and a second terminal coupled to the first input terminal of the operational amplifier. The feedback element has a first terminal coupled to the first input terminal of the operational amplifier and a second terminal coupled to the output terminal of the operational amplifier. The dynamic bias circuit is used for generating a bias current according to a set value. The transconductance amplifier is used for converting the voltage difference between the first input signal and the second input signal to generate an analog output current. The analog output current flows through the feedback element. The first input element has a fixed resistance. The analog output current of the transconductance amplifier varies according to the bias current.
Drawings
Fig. 1 is a schematic diagram of a conventional variable gain amplifier circuit.
FIG. 2 is a block diagram of a variable gain amplifier circuit incorporating an embodiment of the present invention.
Fig. 3 shows a circuit diagram of the variable gain amplifier circuit incorporating an embodiment of the present invention.
FIG. 4 is a block diagram of a variable gain amplifier circuit incorporating another embodiment of the present invention.
Fig. 5 shows a circuit diagram of a variable gain amplifier circuit incorporating another embodiment of the present invention.
FIG. 6 is a block diagram of a variable gain amplifier circuit capable of increasing gain according to another embodiment of the present invention.
Fig. 7 shows an operation of the variable gain amplifier circuit shown in fig. 6.
FIG. 8 is a block diagram of a variable gain amplifier circuit capable of increasing gain according to still another embodiment of the present invention.
Fig. 9 shows a circuit diagram of the variable gain amplifier circuit incorporating an embodiment of the present invention.
[ notation ] to show
100 variable gain amplifying circuit
12 differential operational amplifier
14 gain controller
16 gain controller
200 variable gain amplifying circuit
22 gain amplifier
224 operational amplifier
24, 24' transconductance amplifier
26, 26' dynamic bias circuit
262 current generating circuit
2622 operational amplifier
264 current mirror circuit
400 variable gain amplifying circuit
42 gain amplifier
424 operation amplifier
48 detection circuit
49 charge pump
600 variable gain amplifying circuit
64 switching unit
66 switching unit
68 detection circuit
800 variable gain amplifying circuit
82 detection circuit
C1, CH capacitance
I1, I2 current source
N1-N5 transistor
P1-P5 transistor
R1A, R2A, R1B and R2B resistors
R1-R4 resistor
RLEL resistor
SW1, SW2 switch
Detailed Description
Certain terms are used throughout the description and following claims to refer to particular components. As one skilled in the art will appreciate, manufacturers may refer to a component by different names. This description and the appended claims do not intend to distinguish between components that differ in name but not function. In the following description and in the claims, the terms "include" and "comprise" are used in an open-ended fashion, and thus should be interpreted to mean "include, but not limited to. Also, the term "coupled" is used herein to encompass any direct or indirect electrical connection. Thus, if a first device couples to a second device, that connection may be through a direct electrical connection, or through an indirect electrical connection via other devices and connections.
Fig. 2 shows a block diagram of a variable gain amplifier circuit 200 incorporating an embodiment of the invention. Referring to fig. 2, the variable gain amplifier circuit 200 includes a gain amplifier 22, a transconductance amplifier 24, and a dynamic bias circuit 26.
The gain amplifier 22 is configured to receive an analog input signal VI to generate an analog output signal VO. In the present embodiment, the gain amplifier 22 is composed of a single-ended input single-ended output operational amplifier 224, a resistor R1 with a fixed resistance value, and a resistor R2 with a fixed resistance value. When transconductance amplifier 24 is not supplying current to resistor R2, gain G of gain amplifier 22 is determined by equation (1).
G＝R2/R1 (1)
However, a new gain G' of the gain amplifier 22 may be obtained by changing the net current through resistor R2. Referring to fig. 2, transconductance amplifier 24 is configured to convert the difference between input voltage VI and reference voltage VREF to generate an analog output current IGM. Then, transconductance amplifier 24 provides the analog output current IGM to gain amplifier 22, thereby adjusting gain G' of gain amplifier 22. Note that a bias current IDYN of transconductance amplifier 24 is derived from dynamic bias circuit 26. The bias current IDYN may vary according to an input signal VLEL.
Fig. 3 shows a circuit diagram of the variable gain amplifier circuit 200 incorporating an embodiment of the present invention. Referring to fig. 3, the dynamic bias circuit 26 includes a current generation circuit 262 and a current mirror circuit 264. The current generating circuit 262 is composed of an operational amplifier 2622, an NMOS transistor N1 and a resistor RLEL. The operational amplifier 2622 has a positive input terminal for receiving the input signal VLEL, a negative input terminal coupled to the resistor RLEL, and an output terminal coupled to a gate of the NMOS transistor N1. With this structure, the current IN1 flowing through the NMOS transistor N1 can be determined by equation (2).
IN1＝VLEL/RLEL (2)
Referring to fig. 3, the current mirror circuit 264 is composed of PMOS transistors P1, P2, and P3. The PMOS transistor P1 receives the current IN1 flowing through the NMOS transistor N1, and the PMOS transistors P2 and P3 generate a current proportional to the current IN1 according to a width-to-length ratio (W/L ratio). The current of the PMOS transistor P3 is used as the upper bias current of the transconductance amplifier 24. The current flowing through the PMOS transistor P2 flows to the NMOS transistor N2, and then the NMOS transistor N3 generates a current proportional to the NMOS transistor N2 according to the aspect ratio as the lower bias current of the transconductance amplifier 24.
The transconductance amplifier 24 includes an input transistor pair consisting of a PMOS transistor P1 and an NMOS transistor N4 connected in series, and a PMOS transistor P5 and an NMOS transistor N5 connected in series. Referring to fig. 3, the PMOS transistor P4 and the NMOS transistor N4 are connected in series between the PMOS transistor P3 and the NMOS transistor N3, and the PMOS transistor P5 and the NMOS transistor N5 are connected in series between the PMOS transistor P3 and the NMOS transistor N3.
Referring to fig. 3, the gates of the PMOS transistor P4 and the NMOS transistor N4 are configured to receive the analog input signal VI, and the gates of the PMOS transistor P5 and the NMOS transistor N5 are configured to receive the reference voltage VREF. Therefore, the analog output current IGM of the transconductance amplifier 24 has a value proportional to the difference between the input voltage VI and the reference voltage VREF. In addition, the gain of the transconductance amplifier 24 corresponds to the bias current value of the PMOS transistor P3 or the NMOS transistor N3.
An operation of the variable gain amplifier circuit 200 is described below with reference to fig. 3. As the voltage level of the input signal VLEL increases, the current flowing through the resistor RLEL also increases. Since current mirror 264 generates a replica current that is proportional to the current through resistor RLEL. Therefore, the bias current values of the PMOS transistor P3 and the PMOS transistor P3 are increased. When VI > VREF, transconductance amplifier 24 generates the analog output current IGM, which carries away the current that would otherwise flow through resistor R2, so that the net current flowing through resistor R2 decreases, which decreases the gain of gain amplifier circuit 22.
In fig. 3, a single-ended input single-ended output operational amplifier 224 is used in the gain amplifier 22. However, the present invention should not be limited to this type of operational amplifier. The gain amplifier 22 may also be of the differential input differential output amplifier type. Fig. 4 shows a block diagram of a variable gain amplifier circuit 400 incorporating another embodiment of the present invention. Referring to fig. 4, the variable gain amplifier circuit 400 includes a gain amplifier 42, a transconductance amplifier 24 ', a dynamic bias circuit 26', a detection circuit 48, and a charge pump 49. Elements in fig. 4 similar to those in fig. 2 are indicated by similar reference numerals, and details of the circuit will not be repeated.
In the present embodiment the gain amplifier 42 is of the type of a two-terminal differential input two-terminal differential output amplifier. The gain amplifier 42 receives complementary analog input signals VIP and VIN to produce complementary analog output signals VOP and VON. As shown in FIG. 4, the gain amplifier 42 is composed of a differential operational amplifier 424 and resistors R1, R2, R3, R4 with fixed resistance. When the resistance of the resistor R1 is equal to the resistance of the resistor R2, and the resistance of the resistor R3 is equal to the resistance of the resistor R4, the gain G of the gain amplifier 42 is determined by the equation (3) under the condition that the transconductance amplifier 24' does not supply current to the resistor R3.
G＝R3/R1 (3)
In this case, when the input voltage VIP is greater than the input voltage VIN, the direction of the current flowing through the resistor R3 and the direction of the current flowing through the resistor R4 are shown as solid lines in fig. 4. As the difference between the input voltage VIP and the input voltage VIN increases, the current flowing through the resistors R3 and R4 also increases.
On the other hand, when the detection circuit 48 detects that the output voltage of the variable gain amplifier circuit 400 is not within a predetermined range, the gain of the gain amplifier 42 may start to be adjusted. An operation of the variable gain amplifier circuit 400 is described below with reference to fig. 5. When the detection circuit 48 detects that the output voltages VOP, VON of the variable gain amplifier circuit 400 are not within the predetermined range, the detection circuit 48 generates complementary control signals UP and DN to the charge pump 49. The charge pump 49 is used to generate the signal VLEL. As shown in fig. 5, the charge pump 49 includes an upper bias current source I1, a lower bias current source I2, two switches SW1 and SW2, and a capacitor C1.
The charge pump 49 charges the capacitor C1 according to the control signal UP, so that the voltage value of the signal VLEL rises; the charge pump 49 discharges the capacitor C1 according to the control signal DN, so that the voltage of the signal VLEL decreases. When the detection circuit 48 detects that the output voltage VOP, VON of the variable gain amplifier circuit 400 is not within the predetermined range, the charge pump 49 charges the capacitor C1. Therefore, the voltage of the signal VLEL increases, and the current flowing through the resistor RLEL also increases. As the current through the resistor RLEL increases, the bias current value of the PMOS transistor P3 or the NMOS transistor N3 also increases, so that the analog output currents IJ1 and IJ2 of the transconductance amplifier 24 increase. Therefore, the net current through resistors R3 and R4 will drop, which causes the gain of the gain amplifier 42 to drop. Note that the analog output currents IJ1 and IJ2 are in opposite current directions. When the gain of the gain amplifier 42 is decreased, the output voltages VOP, VON of the variable gain amplifier circuit 400 are finally returned to the predetermined range, so that the signal VLEL does not continuously increase and maintains a stable value.
The variable gain amplification circuits of fig. 2 and 4 may be used in many communication systems and signal processing units. For example, the variable gain amplifier circuit 200 may be used in a volume control unit to increase or attenuate an input audio signal. FIG. 6 is a block diagram of a variable gain amplifier circuit 600 incorporating another embodiment of the present invention. Referring to fig. 6, the variable gain amplifier circuit 600 includes a gain amplifier 42, a transconductance amplifier 24 ', a switching unit 64, a switching unit 66, a dynamic bias circuit 26', a detection circuit 68, and a charge pump 49. Elements in fig. 6 that are similar to those in fig. 4 are shown with similar reference numerals.
The operation of the variable gain amplifier circuit 600 will now be described. When the detection circuit 68 detects that the output voltages VOP and VON of the variable gain amplifier circuit 600 are not within a higher predetermined range (e.g., 4V), the switch in the switching unit 64 is turned on and the switch in the switching unit 66 is turned off. Therefore, the transconductance amplifier 24' generates output currents IJ1 and IJ2 according to the difference between the input voltage VIP and the input voltage VIN. The charge pump 49 then charges the capacitor C1 to increase the voltage level of the signal VLEL. As the voltage value of the signal VLEL increases, the net current through resistors R3 and R4 decreases, which causes the gain of the gain amplifier 42 to decrease. In this way, when the output voltages VOP and VON of the variable gain amplification circuit 600 are not within the upper predetermined range, the variable gain amplification circuit 600 can reduce the gain.
On the other hand, when the detection circuit 48 detects that the output voltage VOP, VON of the variable gain amplifier circuit 400 is not within a lower predetermined range (e.g., 0.5V), the switch in the switching unit 64 is turned off and the switch in the switching unit 66 is turned on. Therefore, the transconductance amplifier 24' generates output currents IJ1 and IJ2 according to the difference between the input voltage VIP and the input voltage VIN. In this case, the voltage level of the signal VLEL increases. As shown in fig. 7, the net current through resistors R3 and R4 increases, which causes the gain of the gain amplifier 42 to increase.
Fig. 8 is a block diagram of a variable gain amplifier circuit 800 incorporating yet another embodiment of the present invention. Referring to fig. 8, the variable gain amplifier circuit 800 includes a gain amplifier 42, a transconductance amplifier 24 ', a dynamic bias circuit 26', a detection circuit 82, a switch SW and a capacitor CH. The gain adjustment of the variable gain amplification circuit 200 in fig. 2 and the variable gain amplification circuit 400 in fig. 4 is not defined at the zero crossing of the input voltage or the output voltage. Therefore, even if the amplifier gain is adjusted slightly by introducing small currents IGM to the gain amplifier 22 or by introducing small currents IJ1 and IJ2 to the gain amplifier 42, audible transients (audible transients) may still be caused at the top of the analog input voltage. Sound transients are a problem for high quality audio devices. To solve this problem, the variable gain amplifier circuit 800 may need the detection circuit 72 to detect the zero crossing (zero crossing) of the input voltage or the output voltage, for example, when the input voltage or the output voltage transits from a positive value to a negative value or from a negative value to a positive value, a zero crossing signal is generated to indicate that the signal enters the zero crossing.
Fig. 9 shows a circuit diagram of the variable gain amplification circuit 800 incorporating an embodiment of the present invention. Elements in fig. 9 that are similar to those in fig. 5 are shown with similar reference numerals. Referring to fig. 9, in the present embodiment, the detection circuit 82 receives the complementary analog output signals VOP and VON and generates a zero-crossing signal ZC at the zero-crossing of the output signals VOP and VON. The switch SW is turned on only when the zero-cross signal ZC is generated to transfer the voltage level of the signal VLEL to the capacitor CH. The dynamic bias circuit 26 'then generates an upper bias current and a lower bias current that are provided to the transconductance amplifier 24' based on the voltage VD across the capacitor CH. In this manner, the gain amplifier 42 adjusts the gain value only when the detection circuit 82 detects a zero crossing point.
While the technical content and the technical features of the invention have been disclosed, those skilled in the art can make various substitutions and modifications based on the teaching and the disclosure of the invention without departing from the spirit of the invention. Therefore, the scope of the present invention should not be limited to the embodiments disclosed, but should include various alternatives and modifications without departing from the present invention, which are encompassed by the following claims.
Claims (12)
1. A variable gain amplifier circuit for amplifying a voltage difference between a first input signal and a second input signal to generate an amplified differential output signal, the variable gain amplifier circuit comprising:
an operational amplifier having a first input terminal, a second input terminal and an output terminal for providing the amplified differential output signal;
a first input element having a first terminal for receiving the first input signal and a second terminal coupled to the first input terminal of the operational amplifier;
a feedback element having a first terminal coupled to the first input terminal of the operational amplifier and a second terminal coupled to the output terminal of the operational amplifier;
a detection circuit for receiving one of the first input signal and the second input signal or the amplified differential output signal to generate a zero crossing signal;
a switch;
a dynamic bias circuit for generating a bias current according to a set value; and
a transconductance amplifier for converting the voltage difference between the first input signal and the second input signal to generate an analog output current;
wherein the switch is turned on when the zero crossing signal is generated;
when the switch is turned on, the dynamic bias circuit receives the set value;
wherein the analog output current flows through the feedback element;
wherein the first input element has a fixed resistance; and is
Wherein the analog output current of the transconductance amplifier varies according to the bias current.
2. The variable gain amplifier circuit of claim 1, further comprising a charge pump, wherein the detection circuit is configured to generate a first detection signal when the amplified differential output signal is greater than a first predetermined value, and the charge pump is configured to generate the set value according to the first detection signal.
3. The variable gain amplification circuit of claim 1, wherein as the set point increases, the bias current increases, whereby the analog output current increases such that the net current through the feedback element decreases.
4. The variable gain amplifier circuit of claim 2, wherein when the amplified differential output signal is greater than the first predetermined value, the set value is increased, thereby increasing the bias current to increase the analog output current, wherein the increase in the analog output current decreases a net current through the feedback element.
5. The variable gain amplifier circuit of claim 2, wherein the detection circuit generates a second detection signal when the amplified differential output signal is less than a second predetermined value, the charge pump generating the setting value according to the second detection signal, wherein the first predetermined value is greater than the second predetermined value.
6. The variable gain amplification circuit of claim 5, wherein when the amplified differential output signal is less than the second predetermined value, the set value is increased such that the net current through the feedback element is increased.
7. The variable gain amplifier circuit of claim 1, wherein the dynamic bias circuit comprises:
a current generating circuit having an input terminal receiving the set value and a second terminal generating an output current; and
a current mirror for generating the bias current according to the output current of the current generating circuit;
wherein the output current of the current generating circuit varies according to the set value.
8. The variable gain amplification circuit of claim 1, wherein the transconductance amplifier comprises:
the first PMOS transistor and the first NMOS transistor are connected in series between a first node and a second node; and
a second PMOS transistor and a second NMOS transistor connected in series between the first node and the second node;
wherein the first node is configured to receive the bias current;
the grid electrode of the first PMOS transistor and the grid electrode of the first NMOS transistor are used for receiving the first input signal;
the grid electrode of the second PMOS transistor and the grid electrode of the second NMOS transistor are used for receiving the second input signal; and
wherein the analog output current is generated at an intersection of the first PMOS transistor and the first NMOS transistor.
9. The variable gain amplification circuit of claim 1, wherein the detection circuit generates the zero-crossing signal at a zero-crossing point of the amplified differential output signal.
10. The variable gain amplification circuit of claim 1, wherein the detection circuit generates the zero crossing signal at a zero crossing of the one of the first input signal and the second input signal.
11. The variable gain amplifier circuit of claim 9, wherein the operational amplifier is a single-ended input single-ended output type amplifier, and wherein the second end of the operational amplifier receives the second input signal.
12. The variable gain amplification circuit of claim 1, further comprising:
a second input element having a first terminal for receiving the second input signal and a second terminal coupled to the second input terminal of the operational amplifier;
the operational amplifier is of a double-end input and double-end output type.
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| CN201610129741.9A CN107171650B (en) | 2016-03-08 | 2016-03-08 | Variable gain amplifier circuit |
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| CN201610129741.9A CN107171650B (en) | 2016-03-08 | 2016-03-08 | Variable gain amplifier circuit |
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| CN107171650B true CN107171650B (en) | 2020-04-17 |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| US11271535B2 (en) * | 2019-02-28 | 2022-03-08 | SiliconIntervention Inc. | Analog computer with variable gain |
| DE102019108192A1 (en) * | 2019-03-29 | 2020-10-01 | Inficon Gmbh | Amplifier device for amplifying small currents |
| CN112187249A (en) * | 2019-07-03 | 2021-01-05 | 瑞昱半导体股份有限公司 | Bias circuit system and bias method |
| KR102472150B1 (en) | 2019-08-15 | 2022-11-28 | 선전 구딕스 테크놀로지 컴퍼니, 리미티드 | Amplifier circuits, chips and electronics |
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| US5138280A (en) * | 1991-12-05 | 1992-08-11 | Ford Motor Company | Multichannel amplifier with gain matching |
| US5844444A (en) * | 1997-02-14 | 1998-12-01 | Macronix International Co., Ltd. | Wide dynamic input range transconductor-based amplifier circuit for speech signal processing |
| US5936470A (en) * | 1997-12-10 | 1999-08-10 | Delco Electronics Corporation | Audio amplifier having linear gain control |
| CN101826843A (en) * | 2010-05-06 | 2010-09-08 | 复旦大学 | Variable gain amplifier for linearity optimization at low gain |
| CN101995900A (en) * | 2010-10-13 | 2011-03-30 | 苏州科山微电子科技有限公司 | Gradient voltage generator used for continuous variable gain amplifier |
| CN102790596A (en) * | 2011-05-20 | 2012-11-21 | 杭州中科微电子有限公司 | Automatic gain control amplifier for canceling direct current offset |
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2016
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|---|---|---|---|---|
| US5138280A (en) * | 1991-12-05 | 1992-08-11 | Ford Motor Company | Multichannel amplifier with gain matching |
| US5844444A (en) * | 1997-02-14 | 1998-12-01 | Macronix International Co., Ltd. | Wide dynamic input range transconductor-based amplifier circuit for speech signal processing |
| US5936470A (en) * | 1997-12-10 | 1999-08-10 | Delco Electronics Corporation | Audio amplifier having linear gain control |
| CN101826843A (en) * | 2010-05-06 | 2010-09-08 | 复旦大学 | Variable gain amplifier for linearity optimization at low gain |
| CN101995900A (en) * | 2010-10-13 | 2011-03-30 | 苏州科山微电子科技有限公司 | Gradient voltage generator used for continuous variable gain amplifier |
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