CN115268546B - Bandgap reference circuit with transient enhancement - Google Patents
Bandgap reference circuit with transient enhancement Download PDFInfo
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- CN115268546B CN115268546B CN202210932171.2A CN202210932171A CN115268546B CN 115268546 B CN115268546 B CN 115268546B CN 202210932171 A CN202210932171 A CN 202210932171A CN 115268546 B CN115268546 B CN 115268546B
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- G—PHYSICS
- G05—CONTROLLING; REGULATING
- G05F—SYSTEMS FOR REGULATING ELECTRIC OR MAGNETIC VARIABLES
- G05F1/00—Automatic systems in which deviations of an electric quantity from one or more predetermined values are detected at the output of the system and fed back to a device within the system to restore the detected quantity to its predetermined value or values, i.e. retroactive systems
- G05F1/10—Regulating voltage or current
- G05F1/46—Regulating voltage or current wherein the variable actually regulated by the final control device is dc
- G05F1/56—Regulating voltage or current wherein the variable actually regulated by the final control device is dc using semiconductor devices in series with the load as final control devices
- G05F1/561—Voltage to current converters
Abstract
Embodiments of the present disclosure provide a bandgap reference circuit with transient enhancement. The circuit comprises: the device comprises a pre-voltage stabilizing circuit, a band gap reference core circuit, a frequency compensation circuit and a filter circuit. Wherein the pre-regulator circuit is configured to generate a clamped secondary supply voltage when the supply voltage transient increases and to provide the clamped secondary supply voltage to the bandgap reference core circuit via a first node; the bandgap reference core circuit is configured to output a corresponding reference voltage in accordance with the clamped secondary supply voltage; the frequency compensation circuit is configured to provide frequency compensation to the bandgap reference core circuit and the pre-regulator circuit via a second node; the filtering circuit is configured to filter the bandgap reference core circuit via the first node. The embodiment of the disclosure is applicable to the processing procedure of the reference voltage in the band gap reference circuit.
Description
Technical Field
Embodiments of the present disclosure relate to the field of integrated circuit technology, and in particular, to a bandgap reference circuit with transient enhancement.
Background
The bandgap reference circuit is often used as a stable reference voltage in a switching power supply chip because its output voltage does not vary with the supply voltage and has good temperature characteristics. However, with the development of the power supply technology of the switching power supply chip, the requirements of users on the stability and the recovery speed of the reference voltage are higher and higher, so that the common band-gap reference circuit is difficult to meet the requirements of users, particularly when the power supply voltage suddenly and instantaneously increases, the reference voltage can overshoot greatly, the speed of the overshoot voltage recovering to a normal value is very slow, and a subsequent series of comparators based on the reference voltage are caused to judge to be wrong, and logic errors are caused.
At present, for the problem of overshoot of the reference voltage caused by sudden increase of the power supply voltage, an RC filter circuit is added at all subsequent tap points based on the reference voltage, and the overshoot peak of the reference voltage is filtered out by reasonably setting the time constant of the RC filter circuit, but the RC filter circuit generally consumes a larger chip area and cannot solve the problem of slower recovery speed of the overshoot voltage.
Disclosure of Invention
An object of embodiments of the present disclosure is to provide a bandgap reference circuit with transient enhancement, which solves the problem of overshoot spike of a reference voltage caused by sudden and instantaneous increase of a power supply voltage, reduces the overshoot amplitude of the reference voltage, and simultaneously accelerates the overshoot recovery speed thereof by a transient response enhancement technique.
To achieve the above object, a first aspect of embodiments of the present disclosure provides a bandgap reference circuit with transient enhancement, comprising: the device comprises a pre-voltage stabilizing circuit, a band gap reference core circuit, a frequency compensation circuit and a filter circuit. Wherein the pre-regulator circuit is configured to generate a clamped secondary supply voltage when the supply voltage transient increases and to provide the clamped secondary supply voltage to the bandgap reference core circuit via a first node; the bandgap reference core circuit is configured to output a corresponding reference voltage in accordance with the clamped secondary supply voltage; the frequency compensation circuit is configured to provide frequency compensation to the bandgap reference core circuit and the pre-regulator circuit via a second node; the filtering circuit is configured to filter the bandgap reference core circuit via the first node.
In some embodiments of the present disclosure, the pre-voltage stabilizing circuit includes: a first transistor, a second transistor, a third transistor, a fourth transistor, and a fifth transistor. The control electrode of the first transistor is coupled with the third voltage end, the first electrode of the first transistor is coupled with the first voltage end, and the second electrode of the first transistor is coupled with the control electrode of the second transistor; a first pole of the second transistor is coupled to the first voltage terminal, and a second pole of the second transistor is coupled to the first node; the control electrode of the third transistor is coupled with the second node, the first electrode of the third transistor is coupled with the first node, and the second electrode of the third transistor is coupled with the control electrode of the fourth transistor and the control electrode of the second transistor; a first pole of the fourth transistor is coupled to the first node, and a second pole of the fourth transistor is coupled to a second voltage terminal; the control electrode of the fifth transistor is coupled to the fourth voltage terminal, the first electrode of the fifth transistor is coupled to the control electrode of the second transistor, and the second electrode of the fifth transistor is coupled to the second voltage terminal.
In some embodiments of the present disclosure, the bandgap reference core circuit includes: a sixth transistor, a seventh transistor, an eighth transistor, a ninth transistor, a tenth transistor, an eleventh transistor, a twelfth transistor, a thirteenth transistor, a first resistor, a second resistor, a third resistor, and a fourth resistor. Wherein a control electrode of the sixth transistor is coupled to the control electrode of the seventh transistor, a first electrode of the sixth transistor is coupled to the first node, and a second electrode of the sixth transistor is coupled to the first electrode of the eighth transistor; a first pole of the seventh transistor is coupled to the first node, and a second pole of the seventh transistor is coupled to a first pole of a ninth transistor; the control electrode of the eighth transistor is coupled with the fifth voltage end, and the second electrode of the eighth transistor is coupled with the first electrode of the tenth transistor and the control electrode of the sixth transistor; a control electrode of the ninth transistor is coupled to the fifth voltage terminal, and a second electrode of the ninth transistor is coupled to the second node; the control electrode of the tenth transistor is coupled with the fourth voltage end, and the second electrode of the tenth transistor is coupled with the second voltage end; the control electrode of the eleventh transistor is coupled to the fourth voltage terminal, the first electrode of the eleventh transistor is coupled to the second node, and the second electrode of the eleventh transistor is coupled to the second voltage terminal; the control electrode of the twelfth transistor is coupled with the output end of the reference voltage, the first electrode of the twelfth transistor is coupled with the second electrode of the sixth transistor, and the second electrode of the twelfth transistor is coupled with the first end of the first resistor; a control electrode of the thirteenth transistor is coupled to the output end of the reference voltage, a first electrode of the thirteenth transistor is coupled to a second electrode of the seventh transistor, and a second electrode of the thirteenth transistor is coupled to a first end of the second resistor; the second end of the first resistor is coupled to the first end of the second resistor; a second end of the second resistor is coupled to the second voltage end; a first end of the third resistor is coupled with the first node, and a second end of the third resistor is coupled with an output end of the reference voltage; the first end of the fourth resistor is coupled to the output end of the reference voltage, and the second end of the fourth resistor is coupled to the second voltage end.
In some embodiments of the present disclosure, the frequency compensation circuit includes: a first capacitor. The first end of the first capacitor is coupled to the second node, and the second end of the first capacitor is coupled to the second voltage end.
In some embodiments of the present disclosure, the filter circuit includes: and a second capacitor. The first end of the second capacitor is coupled to the first node, and the second end of the second capacitor is coupled to the second voltage end.
In some embodiments of the present disclosure, the third voltage terminal and the fourth voltage terminal are coupled to a first constant voltage source and a second constant voltage source, respectively.
In some embodiments of the present disclosure, the fourth voltage terminal and the fifth voltage terminal are coupled to a second constant voltage source and a third constant voltage source, respectively.
In some embodiments of the present disclosure, wherein the first, second and third transistors are PMOS transistors and the fourth and fifth transistors are NMOS transistors.
In some embodiments of the disclosure, the sixth transistor, the seventh transistor, the eighth transistor, and the ninth transistor are PMOS transistors, the tenth transistor and the eleventh transistor are NMOS transistors, and the twelfth transistor and the thirteenth transistor are NPN bipolar transistors.
A second aspect of embodiments of the present disclosure provides a bandgap reference circuit with transient enhancement, comprising: first to thirteenth transistors, first to fourth resistors, first capacitance, and second capacitance. The control electrode of the first transistor is coupled with the third voltage end, the first electrode of the first transistor is coupled with the first voltage end, and the second electrode of the first transistor is coupled with the control electrode of the second transistor; a first pole of the second transistor is coupled to the first voltage terminal, and a second pole of the second transistor is coupled to the first node; the control electrode of the third transistor is coupled with the second node, the first electrode of the third transistor is coupled with the first node, and the second electrode of the third transistor is coupled with the control electrode of the fourth transistor and the control electrode of the second transistor; a first pole of the fourth transistor is coupled to the first node, and a second pole of the fourth transistor is coupled to a second voltage terminal; the control electrode of the fifth transistor is coupled to a fourth voltage terminal, the first electrode of the fifth transistor is coupled to the control electrode of the second transistor, and the second electrode of the fifth transistor is coupled to the second voltage terminal; the control electrode of the sixth transistor is coupled to the control electrode of the seventh transistor, the first electrode of the sixth transistor is coupled to the first node, and the second electrode of the sixth transistor is coupled to the first electrode of the eighth transistor; a first pole of the seventh transistor is coupled to the first node, and a second pole of the seventh transistor is coupled to a first pole of a ninth transistor; the control electrode of the eighth transistor is coupled with the fifth voltage end, and the second electrode of the eighth transistor is coupled with the first electrode of the tenth transistor and the control electrode of the sixth transistor; a control electrode of the ninth transistor is coupled to the fifth voltage terminal, and a second electrode of the ninth transistor is coupled to the second node; a control electrode of the tenth transistor is coupled to the fourth voltage terminal, and a second electrode of the tenth transistor is coupled to the second voltage terminal; the control electrode of the eleventh transistor is coupled to the fourth voltage terminal, the first electrode of the eleventh transistor is coupled to the second node, and the second electrode of the eleventh transistor is coupled to the second voltage terminal; the control electrode of the twelfth transistor is coupled with the output end of the reference voltage, the first electrode of the twelfth transistor is coupled with the second electrode of the sixth transistor, and the second electrode of the twelfth transistor is coupled with the first end of the first resistor; a control electrode of the thirteenth transistor is coupled to the output end of the reference voltage, a first electrode of the thirteenth transistor is coupled to a second electrode of the seventh transistor, and a second electrode of the thirteenth transistor is coupled to a first end of the second resistor; the second end of the first resistor is coupled to the first end of the second resistor; a second end of the second resistor is coupled to the second voltage end; a first end of the third resistor is coupled with the first node, and a second end of the third resistor is coupled with an output end of the reference voltage; the first end of the fourth resistor is coupled with the output end of the reference voltage, and the second end of the fourth resistor is coupled with the second voltage end; the first end of the first capacitor is coupled with the second node, and the second end of the first capacitor is coupled with the second voltage end; the first end of the second capacitor is coupled to the first node, and the second end of the second capacitor is coupled to the second voltage end.
Through the technical scheme, the transient response enhancement technology is adopted, the problem of overshoot peak of the reference voltage caused by sudden and instant increase of the power supply voltage is solved, the overshoot amplitude of the reference voltage is reduced, and meanwhile, the overshoot recovery speed is increased.
Additional features and advantages of embodiments of the present disclosure will be set forth in the detailed description which follows.
Drawings
The accompanying drawings are included to provide a further understanding of embodiments of the disclosure and are incorporated in and constitute a part of this specification, illustrate embodiments of the disclosure and together with the description serve to explain, without limitation, the embodiments of the disclosure. In the drawings:
FIG. 1 is an exemplary circuit diagram of a bandgap reference circuit;
FIG. 2 is a schematic block diagram of a bandgap reference circuit 200 with transient enhancement in accordance with an embodiment of the present disclosure;
fig. 3 is an exemplary circuit diagram of a bandgap reference circuit 200 with transient enhancement in accordance with an embodiment of the present disclosure.
Elements in the figures are illustrated schematically and not drawn to scale.
Detailed Description
In order to make the objects, technical solutions and advantages of the embodiments of the present disclosure more apparent, the technical solutions of the embodiments of the present disclosure will be clearly and completely described below with reference to the accompanying drawings. It will be apparent that the described embodiments are some, but not all, of the embodiments of the present disclosure. All other embodiments, which can be made by those skilled in the art based on the described embodiments of the present disclosure without the need for creative efforts, are also within the scope of the protection of the present disclosure.
Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by one of ordinary skill in the art to which the presently disclosed subject matter belongs. It will be further understood that terms, such as those defined in commonly used dictionaries, should be interpreted as having a meaning that is consistent with their meaning in the context of the specification and relevant art and will not be interpreted in an idealized or overly formal sense unless expressly so defined herein. As used herein, a statement that two or more parts are "connected" or "coupled" together shall mean that the parts are joined together either directly or joined through one or more intermediate parts.
In all embodiments of the present disclosure, since the source and drain of the fet are symmetrical and the on-current directions between the source and drain of the N-type fet and the P-type fet are opposite, in embodiments of the present disclosure, the controlled middle end of the fet is referred to as the control electrode and the remaining two ends of the fet are referred to as the first and second electrodes, respectively. In addition, terms such as "first" and "second" are used merely to distinguish one component (or portion of a component) from another component (or another portion of a component).
Fig. 1 shows an exemplary circuit diagram of a bandgap reference circuit 100. In the example of fig. 1, when the power supply voltage VIN suddenly increases, the current flowing through the PMOS transistor Mp2 is larger than the current flowing through the PMOS transistor Mp5, the current difference between the two currents rapidly charges the capacitor C1, the voltage of the secondary power supply VREG increases instantaneously, the reference voltage VBG rises instantaneously under the action of the voltage dividing resistors Rf1 and Rf2, the overshoot voltage on the capacitor C1 needs to be discharged to a normal value in the subsequent recovery process due to the action of the large capacitor C1, but the static current is generally smaller in the low-power consumption design, so that the discharging speed of the capacitor C1 is slow, and therefore, when the bandgap reference circuit shown in fig. 1 generates the transient response of the power supply voltage, the overshoot voltage is high and the recovery speed is slow.
Embodiments of the present disclosure provide a bandgap reference circuit with transient enhancement. The circuit solves the problem of overshoot peak of the reference voltage caused by sudden and instant increase of the power supply voltage through a transient response enhancement technology, reduces the overshoot amplitude of the reference voltage, and simultaneously accelerates the overshoot recovery speed. Fig. 2 shows a schematic block diagram of a bandgap reference circuit 200 with transient enhancement in accordance with an embodiment of the present disclosure. As shown in fig. 2, the bandgap reference circuit 200 with transient enhancement may include: a pre-voltage stabilizing circuit 210, a bandgap reference core circuit 220, a frequency compensation circuit 230 and a filter circuit 240.
The pre-voltage stabilizing circuit 210 may be coupled to the bandgap reference core circuit 220, the frequency compensation circuit 230, the filtering circuit 240, the first voltage terminal V1, the second voltage terminal V2, the third voltage terminal V3, and the fourth voltage terminal V4. The pre-voltage regulator circuit 210 may be configured to generate a clamped secondary supply voltage V when the supply voltage transient increases REG And provides the clamped secondary supply voltage V to the bandgap reference core circuit 220 via a first node N1 REG 。
The bandgap reference core circuit 220 may be coupled to the pre-voltage stabilizing circuit 210, the frequency compensating circuit 230, the filtering circuit 240, the second voltage terminal V2, the fourth voltage terminal V4, the fifth voltage terminal V5 and the output terminal V of the reference voltage BG . The bandgap reference core circuit 220 may be configured to output a corresponding reference voltage V in accordance with the clamped secondary supply voltage BG 。
The frequency compensation circuit 230 may be coupled to the pre-voltage stabilizing circuit 210, the bandgap reference core circuit 220, and the second voltage terminal V2. The frequency compensation circuit 230 may be configured to provide frequency compensation to the bandgap reference core circuit and the pre-voltage stabilizing circuit via the second node N2, ensuring stability of the circuit under various conditions.
The filter circuit 240 may be coupled to the pre-voltage stabilizing circuit 210, the bandgap reference core circuit 220, and the second voltage terminal V2. The filtering circuit 240 may be configured to filter the bandgap reference core circuit 220 via the first node N1.
According to the band-gap reference circuit with transient enhancement, when the power supply voltage is increased in a transient mode through a transient response enhancement technology, the clamped secondary power supply voltage is generated, so that the reference voltage response speed is higher, and the overshoot amplitude is smaller.
Fig. 3 shows an exemplary circuit diagram of a bandgap reference circuit 200 with transient enhancement in accordance with an embodiment of the disclosure. As shown in fig. 3, the pre-voltage stabilizing circuit 210 may include: the first transistor M1, the second transistor M2, the third transistor M3, the fourth transistor M4, and the fifth transistor M5. The control electrode of the first transistor M1 is coupled to the third voltage terminal V3, the first electrode of the first transistor M1 is coupled to the first voltage terminal V1, and the second electrode of the first transistor M1 is coupled to the control electrode of the second transistor M2. A first pole of the second transistor M2 is coupled to the first voltage terminal V1, and a second pole of the second transistor M2 is coupled to the first node N1. The control electrode of the third transistor M3 is coupled to the second node N2, the first electrode of the third transistor M3 is coupled to the first node N1, and the second electrode of the third transistor M3 is coupled to the control electrode of the fourth transistor M4 and the control electrode of the second transistor M2. The first pole of the fourth transistor M4 is coupled to the first node N1, and the second pole of the fourth transistor M4 is coupled to the second voltage terminal V2. The control electrode of the fifth transistor M5 is coupled to the fourth voltage terminal V4, the first electrode of the fifth transistor M5 is coupled to the control electrode of the second transistor M2, and the second electrode of the fifth transistor M5 is coupled to the second voltage terminal V2.
The bandgap reference core circuit 220 may include: the sixth transistor M6, the seventh transistor M7, the eighth transistor M8, the ninth transistor M9, the tenth transistor M10, the eleventh transistor M11, the twelfth transistor Q12, the thirteenth transistor Q13, the first resistor R1, the second resistor R2, the third resistor R3, and the fourth resistor R4. The control electrode of the sixth transistor M6 is coupled to the control electrode of the seventh transistor M7, the first electrode of the sixth transistor M6 is coupled to the first node N1, and the second electrode of the sixth transistor M6 is coupled to the first electrode of the eighth transistor M8. A first pole of the seventh transistor M7 is coupled to the first node N1, and a second pole of the seventh transistor M7 is coupled to a first pole of the ninth transistor M9. The control electrode of the eighth transistor M8 is coupled to the fifth voltage terminal V5, and the second electrode of the eighth transistor M8 is coupled to the first electrode of the tenth transistor M10 and the control electrode of the sixth transistor M6. The control electrode of the ninth transistor M9 is coupled to the fifth voltage terminal V5, and the second electrode of the ninth transistor M9 is coupled to the second node N2. The control electrode of the tenth transistor M10 is coupled to the fourth voltage terminal V4, and the second electrode of the tenth transistor M10 is coupled to the second voltage terminal V2. The control electrode of the eleventh transistor M11 is coupled to the fourth voltage terminal V4, the first electrode of the eleventh transistor M11 is coupled to the second node N2, and the second electrode of the eleventh transistor M11 is coupled to the second voltage terminal V2. The control electrode of the twelfth transistor Q12 is coupled to the output terminal V of the reference voltage BG A first pole of the twelfth transistor Q12 is coupled to the second pole of the sixth transistor M6, and a second pole of the twelfth transistor Q12 is coupled to the first end of the first resistor R1. The control electrode of the thirteenth transistor Q13 is coupled to the output terminal V of the reference voltage BG The first pole of the thirteenth transistor Q13 is coupled to the second pole of the seventh transistor M7, and the second pole of the thirteenth transistor Q13 is coupled to the first end of the second resistor R2. The second end of the first resistor R1 is coupled to the first end of the second resistor R2. The second end of the second resistor R2 is coupled to the second voltage end V2. A first end of the third resistor R3 is coupled to the first node N1, and a second end of the third resistor R3 is coupled to the output end V of the reference voltage BG . The first end of the fourth resistor R4 is coupled to the output end V of the reference voltage BG The second terminal of the fourth resistor R4 is coupled to the second voltage terminal V2.
The frequency compensation circuit 230 may include: a first capacitor C1. The first end of the first capacitor C1 is coupled to the second node N2, and the second end of the first capacitor C1 is coupled to the second voltage end V2.
The filter circuit 240 may include: and a second capacitor C2. The first end of the second capacitor C2 is coupled to the first node N1, and the second end of the second capacitor C2 is coupled to the second voltage end V2.
In the example of fig. 3, the power voltage is input from the first voltage terminal V1, the second voltage terminal V2 is grounded, the third voltage terminal V3 is coupled to the first constant voltage source, the fourth voltage terminal V4 is coupled to the second constant voltage source, and the fifth voltage terminal V5 is coupled to the third constant voltage source. Wherein the first constant voltage source is a fixed voltage source which is 800mV lower than the power supply voltage, the second constant voltage source is a fixed voltage source which is 800mV higher than the ground voltage, and the third constant voltage source is a fixed voltage source which is 800mV or 900mV lower than the secondary power supply voltage. The first transistor M1, the second transistor M2, the third transistor M3, and the sixth transistor M6 to the ninth transistor M9 are PMOS transistors. The fourth transistor M4, the fifth transistor M5, the tenth transistor M10 and the eleventh transistor M11 are NMOS transistors. The twelfth transistor Q12 and the thirteenth transistor Q13 are NPN bipolar transistors. It will be appreciated by those skilled in the art that variations to the circuit shown in fig. 3 based on the above inventive concepts are also within the scope of the present disclosure. In this modification, the above-described transistor and voltage terminal may also have different settings from the example shown in fig. 3.
The operation of bandgap reference circuit 200 with transient enhancement according to an embodiment of the present disclosure is described below in conjunction with the example of fig. 3.
The second transistor M2, the third transistor M3, and the fourth transistor M4 in the pre-voltage stabilizing circuit 210 constitute a transient response enhancing circuit, which is also a negative feedback clamp circuit. When the power supply voltage input at the first voltage terminal V1 increases transiently, the sum of the current flowing through the second transistor M1 and the current flowing through the third transistor M3 is larger than the current flowing through the fifth transistor M5, the voltage at the node a is raised, the NMOS transistor M4 is turned on, and the excessive current is drained through the fourth transistor M4, i.e. the increase of the current on the second transistor M2 is clamped to the current value of the fourth transistor M4, so that the charging current of the second capacitor C2 at the overshoot moment is limited. Meanwhile, after the fourth transistor M4 is turned on, the secondary power voltage V of the first node N1 REG The overshoot voltage which has occurred accelerates the discharge, and finally reduces the reference voltage V BG And the overshoot recovery speed is increased.
In summary, according to the band gap reference circuit with transient enhancement according to the embodiment of the disclosure, a transistor is added to form a transient response enhancement circuit, and the reference voltage is pulled down through negative feedback at the moment of sudden increase of the power supply voltage so as to reduce the overshoot amplitude of the reference voltage, so that the circuit structure is simple.
The flowcharts and block diagrams in the figures illustrate the architecture, functionality, and operation of possible implementations of apparatus and methods according to various embodiments of the present disclosure. In this regard, each block in the flowchart or block diagrams may represent a module, segment, or portion of instructions, which comprises one or more executable instructions for implementing the specified logical function(s). In some alternative implementations, the functions noted in the block may occur out of the order noted in the figures. For example, two blocks shown in succession may, in fact, be executed substantially concurrently, or the blocks may sometimes be executed in the reverse order, depending upon the functionality involved. It will also be noted that each block of the block diagrams and/or flowchart illustration, and combinations of blocks in the block diagrams and/or flowchart illustration, can be implemented by special purpose hardware-based systems which perform the specified functions or acts, or combinations of special purpose hardware and computer instructions.
As used herein and in the appended claims, the singular forms of words include the plural and vice versa, unless the context clearly dictates otherwise. Thus, when referring to the singular, the plural of the corresponding term is generally included. Similarly, the terms "comprising" and "including" are to be construed as being inclusive rather than exclusive. Likewise, the terms "comprising" and "or" should be interpreted as inclusive, unless such an interpretation is expressly prohibited herein. Where the term "example" is used herein, particularly when it follows a set of terms, the "example" is merely exemplary and illustrative and should not be considered exclusive or broad.
Further aspects and scope of applicability will become apparent from the description provided herein. It is to be understood that various aspects of the application may be implemented alone or in combination with one or more other aspects. It should also be understood that the description and specific examples are intended for purposes of illustration only and are not intended to limit the scope of the present disclosure.
While several embodiments of the present disclosure have been described in detail, it will be apparent to those skilled in the art that various modifications and variations can be made to the embodiments of the present disclosure without departing from the spirit and scope of the disclosure. The scope of the present disclosure is defined by the appended claims.
Claims (9)
1. A bandgap reference circuit with transient enhancement, comprising: a pre-voltage stabilizing circuit, a band gap reference core circuit, a frequency compensation circuit and a filter circuit,
wherein the pre-regulator circuit is configured to generate a clamped secondary supply voltage when the supply voltage transient increases and to provide the clamped secondary supply voltage to the bandgap reference core circuit via a first node;
the bandgap reference core circuit is configured to output a corresponding reference voltage in accordance with the clamped secondary supply voltage;
the frequency compensation circuit is configured to provide frequency compensation to the bandgap reference core circuit and the pre-regulator circuit via a second node;
the filtering circuit is configured to filter the bandgap reference core circuit via the first node,
wherein, the pre-voltage stabilizing circuit includes: a first transistor, a second transistor, a third transistor, a fourth transistor, and a fifth transistor,
the control electrode of the first transistor is coupled with the third voltage end, the first electrode of the first transistor is coupled with the first voltage end, and the second electrode of the first transistor is coupled with the control electrode of the second transistor;
a first pole of the second transistor is coupled to the first voltage terminal, and a second pole of the second transistor is coupled to the first node;
the control electrode of the third transistor is coupled with the second node, the first electrode of the third transistor is coupled with the first node, and the second electrode of the third transistor is coupled with the control electrode of the fourth transistor and the control electrode of the second transistor;
a first pole of the fourth transistor is coupled to the first node, and a second pole of the fourth transistor is coupled to a second voltage terminal;
the control electrode of the fifth transistor is coupled to the fourth voltage terminal, the first electrode of the fifth transistor is coupled to the control electrode of the second transistor, and the second electrode of the fifth transistor is coupled to the second voltage terminal.
2. The bandgap reference circuit with transient enhancement according to claim 1, wherein said bandgap reference core circuit comprises: a sixth transistor, a seventh transistor, an eighth transistor, a ninth transistor, a tenth transistor, an eleventh transistor, a twelfth transistor, a thirteenth transistor, a first resistor, a second resistor, a third resistor, and a fourth resistor,
wherein a control electrode of the sixth transistor is coupled to the control electrode of the seventh transistor, a first electrode of the sixth transistor is coupled to the first node, and a second electrode of the sixth transistor is coupled to the first electrode of the eighth transistor;
a first pole of the seventh transistor is coupled to the first node, and a second pole of the seventh transistor is coupled to a first pole of a ninth transistor;
the control electrode of the eighth transistor is coupled with the fifth voltage end, and the second electrode of the eighth transistor is coupled with the first electrode of the tenth transistor and the control electrode of the sixth transistor;
a control electrode of the ninth transistor is coupled to the fifth voltage terminal, and a second electrode of the ninth transistor is coupled to the second node;
the control electrode of the tenth transistor is coupled with the fourth voltage end, and the second electrode of the tenth transistor is coupled with the second voltage end;
the control electrode of the eleventh transistor is coupled to the fourth voltage terminal, the first electrode of the eleventh transistor is coupled to the second node, and the second electrode of the eleventh transistor is coupled to the second voltage terminal;
the control electrode of the twelfth transistor is coupled with the output end of the reference voltage, the first electrode of the twelfth transistor is coupled with the second electrode of the sixth transistor, and the second electrode of the twelfth transistor is coupled with the first end of the first resistor;
a control electrode of the thirteenth transistor is coupled to the output end of the reference voltage, a first electrode of the thirteenth transistor is coupled to a second electrode of the seventh transistor, and a second electrode of the thirteenth transistor is coupled to a first end of the second resistor;
the second end of the first resistor is coupled to the first end of the second resistor;
a second end of the second resistor is coupled to the second voltage end;
a first end of the third resistor is coupled with the first node, and a second end of the third resistor is coupled with an output end of the reference voltage;
the first end of the fourth resistor is coupled to the output end of the reference voltage, and the second end of the fourth resistor is coupled to the second voltage end.
3. The band gap reference circuit with transient enhancement of claim 1, wherein the frequency compensation circuit comprises: the first capacitance of the first capacitor is used to control the first capacitance,
the first end of the first capacitor is coupled to the second node, and the second end of the first capacitor is coupled to the second voltage end.
4. The band gap reference circuit with transient enhancement of claim 1, wherein the filter circuit comprises: a second capacitor is provided between the first capacitor and the second capacitor,
the first end of the second capacitor is coupled to the first node, and the second end of the second capacitor is coupled to the second voltage end.
5. The bandgap reference circuit with transient enhancement according to claim 1, wherein said third voltage terminal and said fourth voltage terminal are coupled to a first constant voltage source and a second constant voltage source, respectively.
6. The bandgap reference circuit with transient enhancement according to claim 2, wherein said fourth voltage terminal and said fifth voltage terminal are respectively coupled to a second constant voltage source and a third constant voltage source.
7. The bandgap reference circuit with transient enhancement according to claim 1, wherein said first, second and third transistors are PMOS transistors and said fourth and fifth transistors are NMOS transistors.
8. The bandgap reference circuit with transient enhancement according to claim 2, wherein said sixth, seventh, eighth and ninth transistors are PMOS transistors, said tenth and eleventh transistors are NMOS transistors, and said twelfth and thirteenth transistors are NPN bipolar transistors.
9. A bandgap reference circuit with transient enhancement, comprising: first to thirteenth transistors, first to fourth resistors, first capacitance, and second capacitance,
the control electrode of the first transistor is coupled with the third voltage end, the first electrode of the first transistor is coupled with the first voltage end, and the second electrode of the first transistor is coupled with the control electrode of the second transistor;
a first pole of the second transistor is coupled to the first voltage terminal, and a second pole of the second transistor is coupled to a first node;
the control electrode of the third transistor is coupled with a second node, the first electrode of the third transistor is coupled with the first node, and the second electrode of the third transistor is coupled with the control electrode of the fourth transistor and the control electrode of the second transistor;
a first pole of the fourth transistor is coupled to the first node, and a second pole of the fourth transistor is coupled to a second voltage terminal;
the control electrode of the fifth transistor is coupled to a fourth voltage terminal, the first electrode of the fifth transistor is coupled to the control electrode of the second transistor, and the second electrode of the fifth transistor is coupled to the second voltage terminal;
the control electrode of the sixth transistor is coupled to the control electrode of the seventh transistor, the first electrode of the sixth transistor is coupled to the first node, and the second electrode of the sixth transistor is coupled to the first electrode of the eighth transistor;
a first pole of the seventh transistor is coupled to the first node, and a second pole of the seventh transistor is coupled to a first pole of a ninth transistor;
the control electrode of the eighth transistor is coupled with the fifth voltage end, and the second electrode of the eighth transistor is coupled with the first electrode of the tenth transistor and the control electrode of the sixth transistor;
a control electrode of the ninth transistor is coupled to the fifth voltage terminal, and a second electrode of the ninth transistor is coupled to the second node;
a control electrode of the tenth transistor is coupled to the fourth voltage terminal, and a second electrode of the tenth transistor is coupled to the second voltage terminal;
the control electrode of the eleventh transistor is coupled to the fourth voltage terminal, the first electrode of the eleventh transistor is coupled to the second node, and the second electrode of the eleventh transistor is coupled to the second voltage terminal;
the control electrode of the twelfth transistor is coupled with the output end of the reference voltage, the first electrode of the twelfth transistor is coupled with the second electrode of the sixth transistor, and the second electrode of the twelfth transistor is coupled with the first end of the first resistor;
a control electrode of the thirteenth transistor is coupled to the output end of the reference voltage, a first electrode of the thirteenth transistor is coupled to a second electrode of the seventh transistor, and a second electrode of the thirteenth transistor is coupled to a first end of the second resistor;
the second end of the first resistor is coupled to the first end of the second resistor;
a second end of the second resistor is coupled to the second voltage end;
a first end of the third resistor is coupled with the first node, and a second end of the third resistor is coupled with an output end of the reference voltage;
the first end of the fourth resistor is coupled with the output end of the reference voltage, and the second end of the fourth resistor is coupled with the second voltage end;
the first end of the first capacitor is coupled with the second node, and the second end of the first capacitor is coupled with the second voltage end;
the first end of the second capacitor is coupled to the first node, and the second end of the second capacitor is coupled to the second voltage end.
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| CN202210932171.2A CN115268546B (en) | 2022-08-04 | 2022-08-04 | Bandgap reference circuit with transient enhancement |
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| CN202210932171.2A CN115268546B (en) | 2022-08-04 | 2022-08-04 | Bandgap reference circuit with transient enhancement |
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| CN115268546B true CN115268546B (en) | 2023-09-26 |
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| CN115599155B (en) * | 2022-12-05 | 2023-03-10 | 深圳市微源半导体股份有限公司 | Band gap reference circuit |
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| CN115268546A (en) | 2022-11-01 |
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