KR20070000177A - Low power flip-flop - Google Patents

Abstract

A low power flip flop is provided to minimize power consumption by using a clock signal having small swing width, and prevent a specific node of the flip flop from being unnecessarily switched. According to a low power flip flop, a first PMOS transistor(51) is located between a power supply voltage and a first node. A first and a second NMOS transistor(52,53) are serially connected between a first node and a ground. A second and a third PMOS transistor(54,55) are serially connected between the power supply voltage and the first node. A third and a fourth NMOS transistor(56,57) are serially connected between the first node and the ground. A fourth PMOS transistor(58) is connected between the power supply voltage and a second node. A fifth and a sixth NMOS transistor(59,60) are serially connected between the second node and the ground. A latch(61) inverts an output of the second node and then latches the inverted output. A gate of the first PMOS transistor and gates of the second and the fourth NMOS transistor are connected in common to receive an input signal. Gates of the first and the fifth NMOS transistor and the third PMOS are connected in common to receive a clock signal. A gate of the fourth PMOS transistor and a gate of the sixth NMOS transistor are connected in common, and are connected to the first node. The input signal is transferred to the latch in response to the clock signal.

Description

Low power flip-flop

The present invention relates to a flip-flop, and more particularly to a flip-flop device with reduced power consumption.

Recently, as mobile devices such as notebook computers have emerged as main products, the importance of low power semiconductor memory chips is increasing. The low power problem is different depending on the type and role of each circuit. Here, the flip-flop which is widely used in memory chips will be discussed.

1 is an example of a flip-flop of a sense amplifier type that is conventionally used.

The flip-flop operation of FIG. 1 is generally as follows.

First, when the clock signal CLK is low, the nodes SB and RB go high. Since the nodes SB and RB are high, the output node OUT maintains its original value due to the inverter type latch. Assuming that the input signal in is applied high, when the clock signal CLK transitions high, the transistors M8 to M10 are turned off, and the transistors M3, M5, and M7 are turned on and the node SB is turned on. Is pulled down, and the node RB remains high because transistor M2 is turned on and transistor M6 is turned off, and the output signal becomes high. Once the node SB is pulled down, the transistor M4 is turned off so that the output is not affected even if the input signal in changes. In this state, when the clock signal CLK goes low, the nodes SB and RB become high again, and the above operation is repeated.

On the contrary, if the input signal in is low, it can be seen that the node SB is high and the node RB is low by the same principle as described above, so that the output is low.

However, referring to the circuit operation of FIG. 1, one of the nodes SB and RB repeats precharge and discharge every clock (at the rising edge of the clock signal CLK) regardless of the input and output states. It can be seen. This results in a problem that leads to unnecessary power consumption. That is, when the clock signal CLK toggles while the input signal in enters the same level for a predetermined time, there is a problem in that power consumption increases due to unnecessary transition of a specific internal node.

The present invention provides a flip-flop that minimizes unnecessary transitions of internal nodes in order to solve the above problems.

In addition, the present invention provides a flip-flop device using a small clock signal having a swing width in order to minimize power consumption.

The low power flip-flop device of the present invention includes a first PMOS transistor 51 between a power supply voltage and a first node X, and first and second NMOS transistors 52 connected in series between an upper first node X and a ground. 53, second and third PMOS transistors 54 and 55 connected in series between the power supply voltage and the first node X, and third and third connected in series between the first node X and ground. Fourth NMOS transistors 56 and 57, a fourth PMOS transistor 58 connected between the power supply voltage and a second node Y, and fifth and fifth connected in series between the second node Y and ground; 6 NMOS transistors 59 and 60 and a latch 61 for receiving, inverting and latching the output of the second node Y. The gate and the second gate of the first PMOS transistor 51 are provided. And gates of the fourth NMOS transistors 53 and 57 are commonly connected to receive input signals, and the first and fifth NMOS transistors 52 and 59 are connected to each other. The gate of the third PMOS transistor 55 is commonly connected to receive a clock signal, and the gate of the fourth PMOS transistor 58 and the gate of the sixth NMOS transistor 60 are connected in common to the first node X. The input signal is transmitted to the latch in response to the clock signal.

In the present invention, the clock signal generator for generating the clock signal is further provided, wherein the high level of the clock signal is lower than the power supply voltage.

In the present invention, the clock generator includes a delay unit for receiving an external clock, and an exclusive oar gate for receiving an output signal of the external clock and the delay unit.

In the present invention, the frequency of the clock signal is twice the frequency of the external clock.

(Example)

Hereinafter, embodiments of the present invention will be described with reference to the drawings.

In general, in order to implement low power consumption of the memory chip, power consumption may be reduced by applying a clock voltage VCK lower than an external power supply voltage VDD to a circuit using a clock signal. Here, the clock voltage VCK may be externally applied or generated internally.

2 is an example of a memory chip using a clock voltage VCK.

As can be seen in Figure 2, by using the clock voltage (VCK) separately from the power supply voltage (VDD), it is possible to significantly reduce the power consumption of the circuit operating in conjunction with the clock. For reference, this will be fully understood from the description of FIGS. 3 and 4.

3 is an example of an internal clock signal generator according to the present invention.

As shown, the internal clock signal generator includes a delay unit for delaying the external clock signal CLK for a predetermined time, and an exclusive or gate for receiving the output signal and the external clock signal of the delay unit. Here, since the delay unit and the exclusive oar gate are driven by the clock voltage VCK lower than the power supply voltage VDD, the voltage level of the clock signal output to the output terminal P of the exclusive oar gate is the power supply voltage ( Lower than VDD).

As shown, the output stage P of the exclusive oar gate is applied to a plurality of flip-flops and used as a clock.

An example of the internal clock signal generator of FIG. 3 is illustrated in FIG. 4.

4 illustrates an internal clock signal generator for receiving an external clock signal CLK and outputting an internal clock of the present invention.

In FIG. 4, CLKD is a signal delayed from an external clock signal CLK.

As shown, the internal clock signal generator includes an inverter 40 for receiving the external clock signal CLK, an inverter 41 for receiving the output signal of the inverter 40, a node a and a node c. PMOS transistors 42 connected between them, NMOS transistors 43 connected between nodes c and b, and PMOS transistors 44 and NMOS transistors connected in parallel between nodes c and d. 45 and an inverter 46 for receiving the signal of the node c.

In FIG. 4, the inverters 40, 41, and 46 use the clock voltage VCLK lower than the power supply voltage VDD as the driving voltage, and the gate of the PMOS transistor 44 is connected to the node a and the NMOS. The gate of transistor 45 is connected to node b. In addition, the thrust signal P of the inverter 46 is the clock signal mentioned in FIG. 3, and the waveform is shown in FIG.

As can be seen in FIG. 4, the pulse signal output from the internal clock generator is the result of the operation of the exclusive OR of the clock signals CLK and CLKD. Therefore, the pulse signal P is generated at the rising edge and the falling edge of the clock signal CLK, respectively. Therefore, the period of the pulse signal P is 1/2 of the clock signal CLK, and the frequency is twice. The pulse width of the pulse signal P is determined by the delay unit. The pulse signal P is applied to the flip-flop device of FIG. 5 proposed in the present invention.

FIG. 5 is a specific example of the flip-flop F / F briefly mentioned in FIG. 3 as an example of the flip-flop device of the present invention.

The flip-flop of Fig. 5 is as follows.

PMOS transistor 51 connected between voltage and node X, two NMOS transistors 52 and 53 connected in series between node X and ground, and two PMOS transistors connected in series between voltage and node X. (54, 55), two NMOS transistors 56, 57 connected in series between node X and ground, and PMOS transistor 58 connected between power supply and node Y, between node Y and ground. Two NMOS transistors 59 and 60 connected in series with each other, and a latch 61 for receiving and inverting the output Q of the node Y and latching it. The output signal QB of the latch is an inverted signal of the output Q.

In FIG. 5, the gate of the PMOS transistor 51 and the gates of the NMOS transistors 53 and 57 are commonly connected and receive an input signal A. In FIG. The gates of the NMOS transistors 52 and 59 and the PMOS transistor 55 are connected in common and receive a clock signal P. The gate of the PMOS transistor 58 and the gate of the NMOS transistor 60 are connected in common and are connected to the node X. The node Y is connected to the gate of the PMOS transistor 54 and the NMOS transistor 56. For reference, the clock signal P in FIG. 5 is a clock signal generated in FIGS. 3 and 4.

In operation, when the input signal A remains high, the internal node X transitions low and thus the output Q transitions high. Once node X goes low, the feedback from output Q creates a path that connects node X to ground, so node X continues as long as input A does not go low. Keep low.

If input A remains at a high level for several clock cycles, there is no change at node X. That is, it maintains a high level without voltage toggling of internal nodes. For this reason, the flip-flop proposed by the present invention reduces power consumption than the conventional sense amplifier flip-flop.

Likewise, if input A remains low for several clock cycles, internal node X remains high and output Q goes low.

The flip-flop device proposed by the present invention described so far has the following advantages over the prior art.

 First, since the internal clock P, a control signal of the flip-flop, is generated at both edges of the external clock signal CLK, the external clock frequency can be reduced in half while maintaining the same data processing speed as the conventional flip-flop. That is, in the past, the flip-flop was operated using an external clock signal having a frequency fo. However, in the present invention, when the frequency of the internal clock P is fo, the operating frequency of the external clock signal may be set to fo / 2. As is well known, power consumption is proportional to frequency. Reducing the frequency of the external clock signal means that power consumption can be reduced.

In addition, since the flip-flop of the present invention removes unnecessary transition of the internal node unlike the conventional flip-flop, it can be seen that there is a gain in power consumption when the same data is applied for several clocks.

Finally, it can be seen that the flip-flop of the present invention reduces power consumption by using the clock voltage VCK lower than the power supply voltage VDD.

When using the flip-flop of the present invention, the power consumption of the memory device can be significantly reduced, and in particular, the power consumption of the flip-flop can be greatly reduced.

1 is an example of a flip-flop of a sense amplifier type that is conventionally used.

2 is an example of a memory chip using a clock voltage VCK.

3 is an example of an internal clock signal generator according to the present invention.

4 illustrates an internal clock signal generator for receiving an external clock signal CLK and outputting an internal clock of the present invention.

5 is an example of a flip-flop device of the present invention.

Claims (4)

In a low power flip-flop device, A first PMOS transistor 51 between the power supply voltage and the first node X, First and second NMOS transistors 52 and 53 connected in series between an additional first node X and ground; Second and third PMOS transistors 54 and 55 connected in series between the power supply voltage and the first node X, Third and fourth NMOS transistors 56 and 57 connected in series between the first node X and ground; A fourth PMOS transistor 58 connected between the power supply voltage and a second node Y; Fifth and sixth NMOS transistors 59 and 60 connected in series between the second node Y and ground; A latch 61 for receiving and inverting the output of the second node Y and latching the output; The gate of the first PMOS transistor 51 and the gates of the second and fourth NMOS transistors 53 and 57 are commonly connected to receive an input signal. The gates of the first and fifth NMOS transistors 52 and 59 and the third PMOS transistor 55 are commonly connected to receive a clock signal. The gate of the fourth PMOS transistor 58 and the gate of the sixth NMOS transistor 60 are connected in common to the first node X. And transmitting the input signal to the latch in response to the clock signal. The method of claim 1, Further comprising a clock signal generator for generating the clock signal, And the high level of the clock signal is lower than the power supply voltage. The method of claim 2, The clock generator A delay unit for receiving an external clock, An exclusive oar gate configured to receive an output signal of the external clock and the delay unit; And the output of the exclusive oar gate is the clock signal. The method of claim 3, wherein The frequency of the clock signal is a low power flip-flop device, characterized in that twice the frequency of the external clock.