KR980012366A - Lead frame for transistor package to prevent solder flow - Google Patents

Abstract

The present invention relates to a lead frame for a transistor package, and more particularly, to a lead frame for a transistor package, which is capable of preventing a solder interposed between a semiconductor chip and a die pad from flowing to an edge portion of a die pad in a die- To a lead frame for a transistor package.

Description

Lead frame for transistor package to prevent solder flow

The present invention relates to a lead frame for a transistor package, and more particularly, to a lead frame for a transistor package, which is capable of preventing a solder interposed between a semiconductor chip and a die pad from flowing down to an edge portion of a die pad in a die- To a lead frame for a transistor package.

1, the lead frame includes a die pad 1, a heat sink 5 formed on one side of the die pad 1, and a heat sink 5 formed on the other side The inner leads 6, 7 and 8 and the inner leads in the state in which the transistor package is manufactured are connected to the outer leads 10, 11, and 12 extending to the outside of the molding resin 9 . Here, the inner leads 7 are integrally connected to the die pad 1.

The upper surface of the die pad 1 of the lead frame described above and the lower surface of the semiconductor chip 2 are bonded to each other by a conductive solder (not shown). At this time, An electrode pad (not shown) formed on the surface is bonded to the internal lead 7 so as to be electrically connected. The electrode pads 3 and 4 formed on the upper surface of the semiconductor chip 2 are electrically connected to the internal leads 6 and 8 by conductive wires 13, respectively.

The semiconductor chip 2, the die pad 1, the wire 13 and the inner leads 6, 7, and 8 are molded by the molding resin 9.

Since the solder interposed between the die pad 1 and the semiconductor chip 2 has flowability, the upper surface of the die pad 1 and the lower surface of the semiconductor chip 2 are electrically connected to each other through conductive solder There is a problem that the size of the semiconductor chip that can be mounted on the die pad is limited due to the solder flowing down to the edge portion of the upper surface of the die pad 1. [

In addition, there has been a problem that corrosion or cracking of the transistor package occurs due to moisture penetration into the package.

In order to solve the above problems, a lead frame used in a transistor package as shown in FIG. 2 has been manufactured.

Fig. 2 (A) is a plan view of a lead frame for a conventional transistor package, Fig. 2 (B) is a cross-sectional view taken along line AA 'and Fig.

A dimple 22 having a predetermined depth is arranged on the upper surface of the lead frame 24 except for the edge portion of the die pad 1 on which the semiconductor chip 2 is mounted. And a swage saw 20 having a stepped portion of a predetermined height is formed on both end portions thereof with a predetermined length.

A groove 21 having a predetermined depth is formed inward of the swage 20 on the upper surface of the die pad 1 except for the edge portion on the upper side of the die pad 1 connected to the heat sink 5 The internal leads 6, 7, 8, and 8 are formed, except that a double groove 23 is formed at a connection portion between the heat sink 5 and the die pad 1, The heat sink 5 and the outer leads 10, 11, 12 are the same as those of the lead frame shown in FIG.

Here, the transistor package manufactured as described above has an advantage that groove, dimple, and swage are formed on the die pad, thereby solving the problem of corrosion and crack inside the package and improving reliability of package assembly.

The solder interposed between the die pad 1 and the semiconductor chip 2 in the step of bonding the upper surface of the die pad 1 and the lower surface of the semiconductor chip 2 with the conductive solder during the semiconductor manufacturing process, The dimples 22, the swage 20 having the steps, and the amount of the adhesive that flows into the groove 21 and flows down to the edge portion of the die pad 1 can be reduced to some extent.

However, as the size of the semiconductor chip becomes larger, the distance between the four sides of the semiconductor chip and the four sides of the die pad becomes short, and therefore, the solder interposed between the die pad and the lower surface of the semiconductor chip, There is still a problem of flowing down to the part.

In addition, according to the above-described problems, the size of a semiconductor chip that can be mounted on the die pad is limited, and even if the thickness of the die pad is as thick as about 1 mm, it is difficult to form a groove for forming a stamping method There was difficulty.

SUMMARY OF THE INVENTION Accordingly, the present invention has been made in view of the above problems, and it is an object of the present invention to provide a semiconductor device and a method of manufacturing the semiconductor device, which can prevent the solder interposed between the semiconductor chip and the die pad from flowing to the edge portion of the die pad, And to provide a lead frame for a transistor package.

Figure 1 is a partially cut away perspective view of a typical flange package.

Fig. 2 (A) is a plan view of a lead frame for a conventional transistor package, Fig. 2 (B) is a cross-sectional view taken along the line A-A ', and Fig.

(A) is a plan view of a lead frame for a transistor package according to an embodiment of the present invention, (B) is a cross-sectional view taken along line A-A ' - >

(B) is a cross-sectional view taken along the line A-A ', (C) is a cross-sectional view taken along line B-B', and (D) is a cross- ) Is a cross-sectional view of line C-C '.

DESCRIPTION OF THE REFERENCE NUMERALS

1: die pad 2: semiconductor chip

3,4: electrode pad 5: heat sink

6, 7, 8: inner lead 9: molding resin

10, 11, 12: outer lead 13: wire

22: dimple 23: double groove

30: lead frame 31: first swage

33: groove 32: second swage

Hereinafter, embodiments of the present invention will be described in detail with reference to the accompanying drawings 3 and 4.

3 (A) is a plan view of a lead frame for a transistor package according to an embodiment of the present invention, (B) is a cross-sectional view taken along the line A-A ' - >

The lead frame 30 includes the die pad 1, the inner leads 6, 7, 8, the heat sink 5 and the outer leads 10, 11 And a plurality of dimples 22 are arranged on the upper surface of the die pad 1 on which the semiconductor chip 2 is mounted.

Except for the region where the semiconductor chip 2 is mounted, except for the area connected to the heat sink 5 on the upper surface of the die pad 1, has a step height of a predetermined height with respect to the upper surface of the die pad, A first swage 31 is formed. In addition, a groove 33 having a predetermined depth is formed on the surface of the first swage 31.

Preferably, the first swage 31 has a height of about 1/3 of the thickness of the die pad 1, and the groove 33 has a height of 1/5 to 1/8 of the thickness of the die pad 1 Respectively.

4A is a plan view of a lead frame for a transistor package, FIG. 4B is a cross-sectional view taken along the line A-A ', FIG. 4C is a cross-sectional view taken along the line B- (D) is a cross-sectional view taken along the line C-C '.

In this embodiment, the first swage 31 is formed at the edge of the upper surface of the die pad 1 so that the first swage 31 has a step height of about 1/3 from the upper surface of the die pad. The difference is that a step at a predetermined height from the first swage 31 surface is formed at a position spaced from the end of the first swage 31 by a predetermined distance in the direction of the center of the die pad 1 And the second swage is formed.

Preferably, the second swage 32 has a step height of about 1/5 of the thickness of the die pad 1, and the distance from the end of the first swage 31 to the center of the die pad 1 is in the range of 0.2 - And is located at a distance of about 0.3 mm.

The die pad 1 is made of a copper material and is electrically connected to the electrode pad formed on the lower surface of the semiconductor chip 2 and the heat generated from the semiconductor chip through the heat sink 5 to the outside It plays a role of diverging.

Reference numeral 5 'denotes a mounting hole for mechanically mounting the transistor package to an automobile or the like.

A method of manufacturing a lead frame for a transistor package for preventing solder flow according to the present invention will now be described.

First, a dimple 22 having a predetermined depth is formed on an upper surface of the lead frame 30 except the four edge portions of the die pad 1. A stepped portion having a depth of about 1/3 of the thickness of the die pad 1 is formed at the edge of the die pad 1 excluding a portion where the semiconductor chip 2 is mounted, So that the first swage 31 is extended by a predetermined length. Next, a groove 32 having a depth of 1/5 to 1/8 of the thickness of the die pad 1 is formed on the surface of the first swage 31.

The second swage 32 shown in Fig. 4 is formed in the die pad 1 at a distance of about 0.2 to 0.3 mm from the end of the first swage 31 toward the center of the die pad 1, as shown in Fig. 3 is the same as the lead frame manufacturing method of FIG. 3, except that the second swaging process is performed so that a step of about 1/5 of the thickness of the pad 1 is obtained.

Here, the first swage 31, the groove 33, and the second swage 32 are manufactured using a stamping method.

In the process of bonding the semiconductor chip 2 to the upper surface of the die pad 1 of the lead frames 30 and 40 manufactured as described above during the semiconductor manufacturing process by using the solder, The solder interposed between the first swage 31 and the first swage 31 flows into the first swage 31 as shown in FIG. 3, and the solder on the first swage 31 is completely introduced into the groove 33 Therefore, the amount of solder flowing down to the edge portion of the upper surface of the die pad 1 can be reduced. Also in FIG. 4, the amount of solder flowing down to the edge portion of the upper surface of the die pad 1 can be similarly reduced.

As described above, the lead frame for preventing the solder flow according to the present invention can maximize the size of the semiconductor chip mounted on the die pad. In addition, in the edge portion excluding the region connected to the heat sink, It is advantageous to form a first swage having a stepped height with respect to the surface and a groove or a second swage on the swage surface, which is advantageous in the process of manufacturing a lead frame.

Claims (7)

A die pad on which the semiconductor chip is mounted; a heat sink formed on one side of the die pad on the die pad; an inner lead arranged on the other side of the die pad; and an outer lead extended from the inner lead In the lead frame, solder flow preventing means having a dual structure is formed at the edge of the die pad surface except for a region connected to the heat sink, so that the solder flows to the edge portion of the die pad at the die attaching time of the semiconductor chip Wherein the solder layer is formed on the lead frame. 2. The semiconductor device according to claim 1, wherein the solder flow preventing means comprises: a second swage formed at an edge of the upper surface of the die pad, the step having a predetermined height from the upper surface of the die pad; Wherein the first swage has a first swage portion and a second swage portion. The soldering apparatus according to claim 1, wherein the solder flow preventing means comprises a first swage having a stepped portion at a predetermined height at an edge of the upper surface of the die pad, and a groove having a predetermined depth on the first swage surface. Lead frame for transistor package for flow protection. The lead frame for a transistor package according to claim 2, wherein the first swage has a level difference of about 1/3 of the thickness of the die pad from the die pad surface. 3. The method of claim 2, wherein the end of the second swage is located 0.2 to 0.3 mm from the first swage end to the center of the die pad and has a depth of about 1/5 of the thickness of the die pad. Lead frame for transistor package for flow protection. The lead frame for a transistor package according to claim 3, wherein the groove has a depth of about 1/5 to 1/8 of the thickness of the die pad. The semiconductor device according to any one of claims 1 to 6, wherein a dimple is formed on the surface of the die pad excluding the edge of the die pad except the edge of the die pad. Lead frame for package. ※ Note: It is disclosed by the contents of the first application.