KR980012318A - Floating Chip Package - Google Patents

Floating Chip Package Download PDF

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Publication number
KR980012318A
KR980012318A KR1019960026723A KR19960026723A KR980012318A KR 980012318 A KR980012318 A KR 980012318A KR 1019960026723 A KR1019960026723 A KR 1019960026723A KR 19960026723 A KR19960026723 A KR 19960026723A KR 980012318 A KR980012318 A KR 980012318A
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KR
South Korea
Prior art keywords
chip
floating
package
chip package
paddle
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KR1019960026723A
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Korean (ko)
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KR100214489B1 (en
Inventor
이병우
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문정환
엘지반도체 주식회사
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Priority to KR1019960026723A priority Critical patent/KR100214489B1/en
Publication of KR980012318A publication Critical patent/KR980012318A/en
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Publication of KR100214489B1 publication Critical patent/KR100214489B1/en

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/0555—Shape
    • H01L2224/05552—Shape in top view
    • H01L2224/05554—Shape in top view being square
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H01L2224/491—Disposition
    • H01L2224/4912—Layout
    • H01L2224/49175—Parallel arrangements
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73265—Layer and wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation

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  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Lead Frames For Integrated Circuits (AREA)

Abstract

본 발명은 플로팅 칩(FLOATING CHIP PACKAGE)에 관한 것으로, 종래의 반도체 패키지는 패들과 그 패들의 상면에 도포되는 접착제를 필수적으로 사용하여 원가절감을 하는데 한계가 있는 문제점이 있었다. 본 발명 플로팅 칩 패키지는 칩의 상면까지 타이바를 연장형성하고, 그 타이바와 칩 사이에 양면접착테이프를 개재하여 구성한 것으로, 종래의 패들과 그 패들의 상면에 칩을 부착할 때 사용하던 접착제를 배제하여 원가절감을 이룰 수 있는 효과가 있고, 따라서 생산성도 향상되는 효과가 있다.BACKGROUND OF THE INVENTION 1. Field of the Invention [0002] The present invention relates to a floating chip package. In the conventional semiconductor package, a paddle and an adhesive applied on the upper surface of the paddle are essentially used. The floating chip package of the present invention is constructed by extending a tie bar to the upper surface of a chip and sandwiching a double-sided adhesive tape between the tie bar and the chip. The adhesive used for attaching chips to the upper surface of the conventional paddle So that it is possible to achieve cost reduction, and therefore productivity is improved.

Description

플로팅 칩 패키지Floating Chip Package

본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음Since this is a trivial issue, I did not include the contents of the text.

제1도는 종래 반도체 패키지의 구성을 보인 것으로, (가)는 종단면도, (나)는 내측을 보인 평면도.FIG. 1 is a longitudinal sectional view of a conventional semiconductor package, and FIG. 2 (b) is a plan view of the inside of the semiconductor package.

제2도는 본 발명 플로팅 칩 패키지의 구성을 보인 것으로, (가)는 종단면도, (나)는 내측을 보인 평면도.Fig. 2 shows the structure of the floating chip package of the present invention. Fig. 2 (a) is a longitudinal sectional view, and Fig. 2 (b) is a plan view showing the inside.

* 도면의 주요부분에 대한 부호의 설명DESCRIPTION OF THE REFERENCE NUMERALS

11 : 칩 11a : 패드11: chip 11a: pad

12a : 인너리드 13 : 금속와이어12a: inner lead 13: metal wire

15,15' : 타이바 16 : 양면접착테이프15,15 ': Tie bar 16: Double-sided adhesive tape

본 발명은 플로팅 칩 패키지(FLOATING CHIP PACKAGE)에 관한 것으로, 특히 패들 및 접착제를 배제하여 원가절감을 할 수 있도록 한 것을 특징으로 하는 플로팅 칩 패키지에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention [0001] The present invention relates to a floating chip package, and more particularly, to a floating chip package which is capable of reducing costs by eliminating paddles and adhesives.

제1도는 종래 반도체 패키지의 구성을 보인 것으로, (가)는 종단면도이고, (나)는 내측을 보인 평면도이다.FIG. 1 shows a structure of a conventional semiconductor package. FIG. 2 (A) is a longitudinal sectional view, and FIG. 2 (B) is a plan view showing the inside.

도시된 바와 같이, 종래 반도체 패키지는 반도체 칩(1)과, 그 칩(1)의 하면에 접착제(2)로 부착되는 패들(3a)과, 상기 칩(1)의 주변에 형성되는 다수개의 인너리드(3b)와, 상기 칩(1)에 형성된 다수개의 패드(1a)와 상기 다수개의 인너리드(3b)를 각각 연결하는 금속와이어(4)와, 상기 칩(1), 패들(3a), 금속와이어(4), 인너리드(3b)의 일정부분을 에폭시로 몰딩한 몸체(5)와, 상기 다수개의 인너리드(3b)에 연장되며 상기 몸체(5)의 외측에 일정한 형태로 성형된 아웃리드(3c)로 구성된다. 그리고, 상기 패들(3a)은 전, 후에 설치된 타이바(6)(6')에 의하여 지지되어 있다.As shown in the figure, a conventional semiconductor package includes a semiconductor chip 1, paddles 3a attached to the lower surface of the chip 1 with an adhesive 2, and a plurality of inner A metal wire 4 connecting the plurality of pads 1a formed on the chip 1 and the plurality of inner leads 3b and a plurality of pads 3a formed on the pads 3a, A body 5 formed by molding a certain part of the metal wire 4 and the inner lead 3b with epoxy and a plurality of inner leads 3b extending outwardly from the outer periphery of the body 5, And a lead 3c. The paddles 3a are supported by tie bars 6 and 6 'that are installed before and after.

상기와 같이 구성되어 있는 종래 반도체 패키지의 제조방법을 설명하면 다음과 같다.A conventional method of manufacturing the semiconductor package having the above structure will now be described.

먼저, 패들(3a)의 상면에 접착제(2)를 용하여 반도체 칩(1)을 부착하고, 그 반도체 칩(1)의 패드(1a)와 상기 다수개의 인너리드(3b)를 각각 금속와이어(4)로 연결하며, 상기 칩(1), 패들(3a), 금속와이어(4), 인너리드(3b)의 일정부분을 몰딩하여 몸체(5)를 형성하며, 마지막으로 상기 몸체(5)의 외측으로 돌출형성된 아웃리드(3c)를 소정의 형태로 절곡하여 패키지를 완성한다.First, the semiconductor chip 1 is attached to the upper surface of the paddle 3a by using the adhesive 2 and the pad 1a of the semiconductor chip 1 and the plurality of inner leads 3b are connected to the metal wires 4 And a body 5 is formed by molding a certain portion of the chip 1, the paddle 3a, the metal wire 4 and the inner lead 3b. Finally, the outer side of the body 5 The outer lead 3c protruding from the outer lead 3c is bent in a predetermined shape to complete the package.

그러나, 상기와 같은 종래의 반도체 패키지는 칩(1)을 지지하는 패들(3a)과 그 패들(3a)의 상면에 칩(1)을 부착하기 위한 접착제(2)를 필수적으로 사용하여야 하기 때문에 그로인한 원가절감에 한계가 있는 문제점이 있었다.However, in the conventional semiconductor package as described above, since the paddle 3a supporting the chip 1 and the adhesive 2 for attaching the chip 1 to the upper surface of the paddle 3a must be used, There is a limitation in cost reduction.

상기와 같은 문제점을 감안하여 안출한 본 발명의 목적은 패들 및 접착제의 사용을 배제하여 원가를 절감할 수 있도록 하는데 적합한 플로팅 칩 패키지를 제공함에 있다.SUMMARY OF THE INVENTION The present invention has been made in view of the above-mentioned problems, and it is an object of the present invention to provide a floating chip package suitable for reducing the cost by eliminating the use of paddles and adhesives.

상기와 같은 본 발명의 목적을 달성하기 위하여 반도체 칩의 주변에 다수개의 인너리드가 형성되어 있고, 상기 칩과 다수개의 인너리드는 각각 금속와이어로 연결되어 있는 패키지에 있어서, 상기 칩의 상면까지 타이바를 연장형성하고, 그 타이바와 칩 사이에 양면접착테이프를 개재하여서 구성된 것을 특징으로 하는 플로팅 칩 패키지가 제공된다.In order to achieve the object of the present invention as described above, a plurality of inner leads are formed in the periphery of a semiconductor chip, and the chip and the plurality of inner leads are connected to each other by metal wires. Wherein a bar is extended and a double-sided adhesive tape is interposed between the tie bar and the chip.

이하, 상기와 같이 구성되어 있는 본 발명 플로팅 칩 패키지를 첨부된 도면의 실시예를 참고하여 보다 상세히 설명하면 다음과 같다.Hereinafter, the floating chip package of the present invention constructed as above will be described in more detail with reference to embodiments of the accompanying drawings.

제2도는 본 발명 플로팅 칩 패키지의 구성을 보인 것으로, (가)는 종단면도이고, (나)는 내측을 보인 평면도이다.Fig. 2 shows the structure of the floating chip package of the present invention. Fig. 2 (a) is a longitudinal sectional view, and Fig. 2 (b) is a plan view showing the inside.

도시된 바와 같이, 본 발명 플로팅 칩 패키지는 반도체 칩(11)과, 그 칩(11)의 주변에 설치되는 다수개의 인너리드(12a)와, 그 다수개의 인너리드(12a)와 상기 칩(11)의 상면에 형성된 다수개의 패드(11a)를 각각 전기적으로 연결한 금속와이어(13)와, 상기 칩(11), 금속와이어(13), 인너리드(12a)의 일정부분을 에폭시로 몰딩한 몸체(14)와, 상기 다수개의 인너리드(12a)에 각각 연장되며 상기 몸체(14)의 외측에 소정형상으로 절곡된 아웃리드(12b)로 구성된다.As shown in the figure, the floating chip package of the present invention includes a semiconductor chip 11, a plurality of inner leads 12a provided around the chip 11, a plurality of inner leads 12a, A metal wire 13 electrically connected to a plurality of pads 11a formed on an upper surface of the chip 11 and a body of epoxy 11 molded on a certain portion of the chip 11, And an outer lead 12b extending from the plurality of inner leads 12a and bent in a predetermined shape on the outer side of the body 14. [

그리고, 상기 칩(11)의 상면까지 타이바(15)(15')가 연장형성되고, 그 타이바(15)(15')와 상기 칩(11) 사이에는 절연성 양면접착테이프(16)가 개재된다.The tie bars 15 and 15 'are extended to the upper surface of the chip 11. An insulating double-sided adhesive tape 16 is provided between the tie bars 15 and 15' .

상기 양면테이프(16)는 폴리이미드 테이프인 것을 특징으로 한다.The double-sided tape 16 is a polyimide tape.

상기와 같이 구성되어 있는 본 발명 플로팅 칩 패키지의 제조방법을 설명하면 다음과 같다.The method of manufacturing the floating chip package of the present invention having the above-described structure will now be described.

먼저, 연장형성된 타이바(15)(15')의 하면에 절연성 양면접착테이프(16)인 폴리이미드 테이프를 부착하고, 그 양면접착테이프(16)의 하면에 반도체 칩(11)을 부착한다. 그런 다음, 상기 반도체 칩(11)의 상면에 형성되어 있는 다수개의 패드(11a)와 다수개의 인너리드(12a)를 금속와이어(13)로 각각 연결한다. 이와 같이 와이어본딩이 끝나면, 상기 칩(11), 금속와이어(13), 인너리드(12a)에 연장되며 몸체(14)의 외측으로 돌출된 아웃리드(12b)를 소정의 형태로 절곡하여 패키지를 완성한다.First, a polyimide tape as an insulating double-sided adhesive tape 16 is attached to the lower surface of the extended tie bar 15 (15 '), and the semiconductor chip 11 is attached to the lower surface of the double-sided adhesive tape 16. The plurality of pads 11a formed on the upper surface of the semiconductor chip 11 and the plurality of inner leads 12a are connected to the metal wires 13, respectively. When the wire bonding is finished, the out lead 12b extending to the chip 11, the metal wire 13, and the inner lead 12a and protruding outward of the body 14 is bent in a predetermined shape, It completes.

이상에서 상세히 설명한 바와 같이 본 발명 플로팅 칩 패키지는 칩의 상면까지 타이바를 연장형성하고, 그 타이바와 칩 사이에 양면접착테이프를 개재하여 구성한 것으로, 종래의 패들과 그 패들의 상면에 칩을 부착할 때 사용하던 접착제를 배제하여 원가절감을 이룰 수 있는 효과가 있고, 따라서 생산성도 향상되는 효과가 있다.As described in detail above, the floating chip package of the present invention is constructed by extending a tie bar to the top surface of the chip, and interposing a double-sided adhesive tape between the tie bar and the chip. The chip is attached to the upper surface of the conventional paddle There is an effect that the cost can be reduced by eliminating the adhesive used at the time of use, and the productivity is also improved.

Claims (2)

반도체 칩의 주변에 다수개의 인너리드가 형성되어 있고, 상기 칩과 다수개의 인너리드는 각각 금속와이어로 연결되어 있는 반도체 패키지에 있어서, 상기 칩의 상면까지 타이바를 연장형성하고, 그 타이바와 칩사이에 양면접착테이프를 개재하여서 구성된 것을 특징으로 하는 플로팅 칩 패키지.A semiconductor package comprising a plurality of inner leads formed around a semiconductor chip, wherein the chip and a plurality of inner leads are connected to each other by a metal wire, wherein a tie bar is extended to an upper surface of the chip, And a double-sided adhesive tape. 제1항에 있어서, 상기 양면접착테이프는 폴리이미드인 것을 특징으로 하는 플로팅 칩 패키지.The floating chip package according to claim 1, wherein the double-sided adhesive tape is polyimide. ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.※ Note: It is disclosed by the contents of the first application.
KR1019960026723A 1996-07-02 1996-07-02 Floating chip package KR100214489B1 (en)

Priority Applications (1)

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KR1019960026723A KR100214489B1 (en) 1996-07-02 1996-07-02 Floating chip package

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KR1019960026723A KR100214489B1 (en) 1996-07-02 1996-07-02 Floating chip package

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KR980012318A true KR980012318A (en) 1998-04-30
KR100214489B1 KR100214489B1 (en) 1999-08-02

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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR20160050731A (en) 2014-10-30 2016-05-11 린나이코리아 주식회사 Body and heat exchanger having the same

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR20160050731A (en) 2014-10-30 2016-05-11 린나이코리아 주식회사 Body and heat exchanger having the same

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KR100214489B1 (en) 1999-08-02

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