KR950007769Y1 - Semiconductor package - Google Patents

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Publication number
KR950007769Y1
KR950007769Y1 KR92024357U KR920024357U KR950007769Y1 KR 950007769 Y1 KR950007769 Y1 KR 950007769Y1 KR 92024357 U KR92024357 U KR 92024357U KR 920024357 U KR920024357 U KR 920024357U KR 950007769 Y1 KR950007769 Y1 KR 950007769Y1
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KR
South Korea
Prior art keywords
lead
power
chip
semiconductor package
package
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KR92024357U
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Korean (ko)
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KR940017910U (en
Inventor
홍성학
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김주용
현대전자산업 주식회사
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Priority to KR92024357U priority Critical patent/KR950007769Y1/en
Publication of KR940017910U publication Critical patent/KR940017910U/en
Application granted granted Critical
Publication of KR950007769Y1 publication Critical patent/KR950007769Y1/en

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/02—Containers; Seals
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32245—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/48257—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a die pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73265—Layer and wire connectors

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  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Lead Frames For Integrated Circuits (AREA)

Abstract

내용 없음.No content.

Description

반도체 패키지Semiconductor package

제1도는 종래의 패키지에서 몰딩수지를 생략한 상태의 부분사시도.1 is a partial perspective view of a molding resin omitted from a conventional package.

제2도는 종래의 다른 패키지에서 몰딩수지를 생략한 상태의 부분사시도.2 is a partial perspective view of a molding resin omitted from another conventional package.

제3도는 본 고안에 사용되는 리드프레임의 일예를 나타낸 요부평면도.Figure 3 is a plan view of the main portion showing an example of the lead frame used in the present invention.

제4도는 본 고안 몰딩수지를 생략한 상태의 요부사시도.Figure 4 is a yabu perspective view of a state in which the molding resin of the present invention is omitted.

제5도는 본 고안에 사용되는 리드프레임의 다른예를 보인 요부평면도이다.5 is a plan view of main parts showing another example of the lead frame used in the present invention.

* 도면의 주요부분에 대한 부호의 설명* Explanation of symbols for main parts of the drawings

2 : 칩 11 : 파워리드2: chip 11: power lead

12 : 받침리드 13 : 공간12: supporting lead 13: space

본 고안은 반도체 패키지에 관한 것으로, 특히 본딩패드(패들)을 없애고 파워리드와 연결된 받침리드를 사용하여 칩을 어태치하도록 한것이다.The present invention relates to a semiconductor package, and in particular, to remove the bonding pad (paddle) and to attach the chip using the support lead connected to the power lead.

일반적으로 반도체 패키지는 리드프레임의 패들에 칩을 어태치하고 칩과 내부리드를 와이어본딩한 다음 몰딩성형시켜 패키지를 제조한다. 이 경우 몰딩시키기 직전의 상태는 제1도과 같이 도시할 수 있는바, 패들(1)에 칩(2)을 어태치하고, 칩(2)과 내부리드(3)를 와이어(4)로 와이어본딩한 것이다. 이때 패들(1)은 타이바(5)에 의하여 리드프레임의 사이드레일(도시하지 않음)과 연결되어 지탱되며, 내부리드(3)를 가로지르는 일점쇄선은 몰딩부위를 의미한다. 그러나 이러한 타입은 대용량 패키지 제조에는 한계가 있어 패들을 내부리드에 접착테이프를 개재하여 직업 어태치하는 칩온리드(Chip On Lead)방식의 패키지가 개발되었다. 이는 제2도와 같이 내부리드(3)와 칩(2) 사이에 첩착테이프(6)를 위치시켜 칩(2)을 어태치하고, 칩(2)과 내부리드(3)를 와이어(4)로 와이어본딩시킨 다음, 몰딩시켜 패키지를 제조하는 것이다(몰딩부위는 일점쇄선 내부부위이다). 그러나 이 방식은 대용량을 가능케는 하나, 내부리드(3)와 접착테이프(6)의 접착에 따른 보이드(Void)생성의 문제점이 있어 신뢰성이 저하될 뿐만 아니라, 하이파워용 패키지를 구현함에 있어서는 칩의 설계가 힘든 단점이 있다.In general, a semiconductor package manufactures a package by attaching a chip to a paddle of a leadframe, wire bonding the chip and the inner lead, and molding the mold. In this case, the state immediately before molding may be illustrated as shown in FIG. 1, in which the chip 2 is attached to the paddle 1, and the chip 2 and the inner lead 3 are wire bonded to the wire 4. It is. At this time, the paddle 1 is connected to and supported by the side rails (not shown) of the lead frame by the tie bar 5, and the one-dot chain line crossing the inner lead 3 means a molding part. However, this type has a limitation in manufacturing a large-capacity package, and a chip-on-lead package has been developed that attaches a paddle to an inner lead by attaching a job. As shown in FIG. 2, the adhesive tape 6 is attached between the inner lead 3 and the chip 2 to attach the chip 2, and the chip 2 and the inner lead 3 to the wire 4. After wire bonding and molding, the package is manufactured (the molding part is the one-dot chain line part). However, this method enables a large capacity, but there is a problem of void generation due to the adhesion of the inner lead 3 and the adhesive tape 6, so that the reliability is lowered and the chip in the implementation of a high power package is realized. Its design is difficult.

본 고안은 이를 감안하여 개발한 것으로, 전원공급용 파워리드의 일부를 확장시킨 받침리드에서 칩이 어태치 되도록 하여 하이파워용 패키지 구현이 용이하게 함을 특징으로 한다. 즉, 반도체 패키지에서, 패들을 없애고 전원선 연결용 파워리드와 연결되는 받침리드가 패들부위에 형성된 것이다.The present invention has been developed in consideration of this, and it is characterized in that the package for the high-power can be easily implemented by attaching the chip in the supporting lead that extends a part of the power supply power lead. That is, in the semiconductor package, a support lead is formed in the paddle portion to remove the paddle and to be connected to the power lead for power line connection.

이하 도면을 참조하여 상세히 설명하면 다음과 같다.When described in detail with reference to the drawings as follows.

제3도는 본 고안에 사용되는 리드프레임(10)의 일예를 나타낸 평면도로, 내부리드(3)와 별도의 파워리드(11)를 내부리드(3) 사이에서 크게 하여 받침리드(12)로 구성한 것이다. 필요에 따라서 파워리드(11)는 받침리드(12)의 임의위치에 형성할 수 있다.3 is a plan view showing an example of the lead frame 10 used in the present invention, wherein the inner lead 3 and the separate power lead 11 are enlarged between the inner lead 3 to constitute the supporting lead 12. will be. The power lead 11 may be formed at any position of the support lead 12 as necessary.

제4도는 본고안의 리드프레임(10)을 사용하여 칩(2)을 어태치하고 와이어(4)로 와이어본딩한 부분사시도이다. 이 경우 내부리드(3) 사이의 임의 위치에 파워리드(11)가 형성되고, 파워리드(11)는 받침리드(12)와 연결되어 있어, 칩(2)의 파워패드(2-1) 설계가 용이하다. 이는 파워리드(11)를 여러개소에 형성할 수 있다. 일단 형성된 파워리드(11) 상호간은 받침리드(12)에 의하여 상호 도통되므로 파워패드(2-1)를 근접한 파워리드(11)에서 와이어본딩할 수 있고, 와이어본딩 되지 않은 파워리드에도 파워를 인가하면 받침리드(12) 및 와이어(4)를 통해 칩(2)의 파워패드(2-1)로 파워가 인가될 수 있기 때문이다. 아울러 필요에 따라서는 파워리드(11)를 Vcc와 Vss전용으로 구분할 수도 있는바, 제5도와 같이 공간(13)을 두고 받침리드(12)가 양분하여, 일측은 Vcc용으로 다른측은 Vss용으로 구분하고, 양분된 받침리드(12)와 결합된 파워리드(11)에도 설정된 파워를 제공토록 한다. 이경우 파워리드(11)에 어태치되는 칩(2)은 파워리드(11)에 에폭시 접착제(14)를 도포한 후 경화시켜 어태치되며, 에폭시접착제(14)는 점도가 있어서 쉽게 흘러내리지 않아 접착이 용이하다. 따라서 받침리드(12)는 파워리드(11)에서 전원문제를 해결하므로 그라운드용 와이어본딩 등이 필요치 않고 단순히 칩(2)을 받쳐주기만 하면 되어 내부리드(3)와 받침리드(12) 간격이 상대적으로 가깝게 설계가능하여, 패키지의 크기를 소형화 시킬 수 있다.4 is a partial perspective view in which the chip 2 is attached and wire-bonded with the wire 4 using the lead frame 10 of the present invention. In this case, the power lead 11 is formed at an arbitrary position between the inner leads 3, and the power lead 11 is connected to the support lead 12, thereby designing the power pad 2-1 of the chip 2. Is easy. This can form the power lead 11 in several places. Since the power leads 11 once formed are electrically connected to each other by the supporting leads 12, the power pads 2-1 can be wire-bonded in the adjacent power lead 11, and power is applied to the power leads that are not wire-bonded. This is because power may be applied to the power pad 2-1 of the chip 2 through the support lead 12 and the wire 4. In addition, if necessary, the power lead 11 may be divided into V cc and V ss exclusively. As shown in FIG. 5, the supporting lead 12 is divided into two spaces, and one side is for V cc and the other side is Separated for V ss , the set power is also provided to the power lead 11 coupled with the divided support lead 12. In this case, the chip 2 attached to the power lead 11 is attached to the power lead 11 by applying an epoxy adhesive 14 and then hardened. This is easy. Therefore, since the support lead 12 solves the power problem in the power lead 11, there is no need for ground wire bonding and the like, and simply supports the chip 2 so that the distance between the inner lead 3 and the support lead 12 is relatively high. It can be designed as close as possible, making the package smaller in size.

이상과 같이 본 고안은 패들을 없앤 대신 파워리드 부위를 크게 한 받침리드에서 칩을 어태치할 수 있도록 하고, 받침리드와 연결되는 파워리드를 여러개소에 만들경우 받침리드에 어태치되는 칩의 파워패드 설계가 용이하고, 받침리드를 분리형성할 경우 파워(Vcc, Vss)에 따른 파워리드도 분리되어 편리하게 칩을 와이어 본딩 시킬 수 있을뿐 아니라 칩의 크기와 일치하도록 받침리드를 형성하면 되므로 와이어 본딩되는 본딩와이어이 길이가 짧아져서 경제적이며, 패키지의 크기도 그만큼 축소시킬 수 있다.As described above, the present invention enables attaching a chip in a support lead with a large power lead area instead of removing the paddle, and when the power lead connected to the support lead is made in several places, the power of the chip attached to the support lead is increased. The pad design is easy, and if the supporting lead is separated, the power lead according to the power (V cc , V ss ) is separated, so that the chip can be conveniently bonded to the chip, and the supporting lead is formed to match the size of the chip. Therefore, the bonding wire to be bonded is shorter in length and economical, the size of the package can be reduced accordingly.

Claims (3)

반도체 패키지를 구성함에 있어서, 패들을 없애고 전원선 연결용 파워리드(11)와 연결되는 받침리드(12)가 패들기능을 수행토록 형성된 것을 특징으로 하는 반도체 패키지.In constructing the semiconductor package, the semiconductor package, characterized in that the paddle is removed and the support lead (12) connected to the power lead for power line connection (11) to perform the paddle function. 제1항에 있어서, 받침리드(12)는 길이방향 중앙에서 일정폭의 공간(13)을 두고 분리되도록 이루어짐을 특징으로 하는 반도체 패키지.The semiconductor package according to claim 1, wherein the support lead (12) is separated from the center in the longitudinal direction with a space (13) of a predetermined width. 제1항에 있어서, 받침리드(12)에는 적어도 하나의 파워리드(11)가 연결됨을 특징으로 하는 반도체 패키지.The semiconductor package according to claim 1, wherein at least one power lead (11) is connected to the support lead (12).
KR92024357U 1992-12-04 1992-12-04 Semiconductor package KR950007769Y1 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
KR92024357U KR950007769Y1 (en) 1992-12-04 1992-12-04 Semiconductor package

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
KR92024357U KR950007769Y1 (en) 1992-12-04 1992-12-04 Semiconductor package

Publications (2)

Publication Number Publication Date
KR940017910U KR940017910U (en) 1994-07-28
KR950007769Y1 true KR950007769Y1 (en) 1995-09-21

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Application Number Title Priority Date Filing Date
KR92024357U KR950007769Y1 (en) 1992-12-04 1992-12-04 Semiconductor package

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KR940017910U (en) 1994-07-28

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