KR980006423A - Manufacturing method of semiconductor device - Google Patents

Manufacturing method of semiconductor device Download PDF

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Publication number
KR980006423A
KR980006423A KR1019960023457A KR19960023457A KR980006423A KR 980006423 A KR980006423 A KR 980006423A KR 1019960023457 A KR1019960023457 A KR 1019960023457A KR 19960023457 A KR19960023457 A KR 19960023457A KR 980006423 A KR980006423 A KR 980006423A
Authority
KR
South Korea
Prior art keywords
polysilicon layer
forming
oxide film
semiconductor device
manufacturing
Prior art date
Application number
KR1019960023457A
Other languages
Korean (ko)
Other versions
KR100199365B1 (en
Inventor
김봉길
Original Assignee
김주용
현대전자산업 주식회사
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 김주용, 현대전자산업 주식회사 filed Critical 김주용
Priority to KR1019960023457A priority Critical patent/KR100199365B1/en
Publication of KR980006423A publication Critical patent/KR980006423A/en
Application granted granted Critical
Publication of KR100199365B1 publication Critical patent/KR100199365B1/en

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Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/027—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34
    • H01L21/0271—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising organic layers
    • H01L21/0273—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising organic layers characterised by the treatment of photoresist layers
    • H01L21/0274—Photolithographic processes
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
    • H01L21/32055—Deposition of semiconductive layers, e.g. poly - or amorphous silicon layers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing

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  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Semiconductor Memories (AREA)
  • Non-Volatile Memory (AREA)

Abstract

본 발명은 반도체 소자의 제조방법을 제공하는 것으로, 필드산화막 상에서 제1 폴리실리콘층 패턴시 제1 폴리실리콘층이 필드산화막과 많이 중첩되게하여 플로팅 게이트 및 컨트롤 게이트간 접촉면적을 증가시키므로써 패캐시터의 커플링비를 크게하여 낮은 구동전압에서도 안정적으로 소자가 동작하게 되고, 이는 챠지펌프 회로를 작게 형성하므로써 고집적화를 실현할 수 있은 효과가 있다.The present invention provides a method for manufacturing a semiconductor device, the pattern of the first polysilicon layer on the field oxide film, the first polysilicon layer overlaps the field oxide film to increase the contact area between the floating gate and the control gate to increase the patch By increasing the coupling ratio of the rotor, the device operates stably even at a low driving voltage. This makes it possible to realize high integration by forming a small charge pump circuit.

Description

반도체 소자의 제조방법Manufacturing method of semiconductor device

본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음As this is a public information case, the full text was not included.

제3도는 본 발명에 따른 플래쉬 메모리셀의 레이아웃도.3 is a layout diagram of a flash memory cell according to the present invention.

Claims (2)

반도체 소자의 제조방법에 있어서, 필드산화막이 형성된 실리콘기판상에 터널산화막을 형성한 후 상기 실리콘기판의 전체 상부면에 제1 폴리실리콘층 및 유전체막을 형성하는 단계와, 상기 단계로부터 상기 유전체막상에 절연막을 형성한 후 그 위에 감광막 패턴을 형성하는 단계와, 상기 단계로부터 상기 감광막 패턴을 마스크로 이용하여 상기 유전체막이 노출되도록 상기 절연막을 경사지게 식각한 후 상기 감광막 패턴을 제거하는 단계와, 상기 단계로부터 상기 절연막을 마스크로 이용하여 상기 유전체막 및 제1 폴리실리콘층을 소정깊이 식각한 후 상기 절연막을 제거하는 단계와, 상기 단계로부터 산화공정으로 소정깊이 식각된 상기 제1 폴리실리콘층의 공간이 메워지도록 산화막을 형성한 후 상기 실리콘기판의 전체 상부면에 제2 폴리실리콘층을 형성하는 단계와, 상기 단계로부터 상기 제2 폴리실리콘층, 유전체막 및 제1 폴리실리콘층을 자기정합 식각방법으로 식각하는 단계로 이루어지는 것을 특징으로 하는 반도체 소자의 제조방법.A method of manufacturing a semiconductor device, comprising: forming a tunnel oxide film on a silicon substrate on which a field oxide film is formed, and then forming a first polysilicon layer and a dielectric film on the entire upper surface of the silicon substrate; Forming an insulating film thereon and forming a photoresist pattern thereon; using the photoresist pattern as a mask from the step, etching the insulating film inclinedly so that the dielectric film is exposed, and then removing the photoresist pattern from the step; Etching the dielectric film and the first polysilicon layer by a predetermined depth using the insulating film as a mask, and then removing the insulating film, and filling the space of the first polysilicon layer etched by the oxidation process from the step. Second polysilicon on the entire upper surface of the silicon substrate after forming an oxide film Phase and a method of manufacturing a semiconductor device of the second polysilicon layer, the dielectric layer and the first polysilicon layer from part characterized in that the magnetic made of etching with an etching method to form the matching. 제1항에 있어서, 상기 절연막은 중간온도 산화막인 것을 특징으로 하는 반도체 소자의 제조방법.The method of claim 1, wherein the insulating film is an intermediate temperature oxide film.
KR1019960023457A 1996-06-25 1996-06-25 Fabrication method of semiconductor device KR100199365B1 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
KR1019960023457A KR100199365B1 (en) 1996-06-25 1996-06-25 Fabrication method of semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
KR1019960023457A KR100199365B1 (en) 1996-06-25 1996-06-25 Fabrication method of semiconductor device

Publications (2)

Publication Number Publication Date
KR980006423A true KR980006423A (en) 1998-03-30
KR100199365B1 KR100199365B1 (en) 1999-06-15

Family

ID=19463207

Family Applications (1)

Application Number Title Priority Date Filing Date
KR1019960023457A KR100199365B1 (en) 1996-06-25 1996-06-25 Fabrication method of semiconductor device

Country Status (1)

Country Link
KR (1) KR100199365B1 (en)

Also Published As

Publication number Publication date
KR100199365B1 (en) 1999-06-15

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